)]}'
{
  "commit": "26ff4d8c8d9826e6f6d7e1f4cdcaf9e3cf40eea7",
  "tree": "ee70ed1d96fe0a1c0e6542a4820b46bead55dd1a",
  "parents": [
    "94ec2c41fe2c4bf6476eeb8ed477cf2565785029"
  ],
  "author": {
    "name": "dineshannayya",
    "email": "dinesh.annayya@gmail.com",
    "time": "Thu Jan 13 09:04:49 2022 +0530"
  },
  "committer": {
    "name": "dineshannayya",
    "email": "dinesh.annayya@gmail.com",
    "time": "Thu Jan 13 09:04:49 2022 +0530"
  },
  "message": "riscv synth update\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "723d4c442cb01b95466c863ceb885699e9b684ce",
      "old_mode": 33188,
      "old_path": "verilog/rtl/syntacore/scr1/synth/Makefile",
      "new_id": "f8cd450bf9ad034042ce246009964a139785b02f",
      "new_mode": 33188,
      "new_path": "verilog/rtl/syntacore/scr1/synth/Makefile"
    },
    {
      "type": "modify",
      "old_id": "f71d243539196f372e0164fce2b8fd9dcc0d4123",
      "old_mode": 33261,
      "old_path": "verilog/rtl/syntacore/scr1/synth/synth.tcl",
      "new_id": "1a3050312a4922f3a3a9a8a8168a0bba88bc0e1b",
      "new_mode": 33261,
      "new_path": "verilog/rtl/syntacore/scr1/synth/synth.tcl"
    }
  ]
}
