diff --git a/checks/.full_log.log.swp b/checks/.full_log.log.swp
new file mode 100644
index 0000000..7b64fd1
--- /dev/null
+++ b/checks/.full_log.log.swp
Binary files differ
diff --git a/checks/full_log.log b/checks/full_log.log
new file mode 100644
index 0000000..26e484c
--- /dev/null
+++ b/checks/full_log.log
@@ -0,0 +1,22 @@
+FULL RUN LOG:
+ Executing Step 0 of 8: Extracting GDS Files
+Step 0 done without fatal errors.
+ Executing Step 1 of 8: Project License Check
+{{LICENSE COMPLIANCE PASSED}} Apache-2.0 LICENSE file was found in project root
+ No third party libraries found.
+Step 1 done without fatal errors.
+{{SPDX COMPLIANCE WARNING}} Found 527 non-compliant files with the SPDX Standard. Check full log for more information
+SPDX COMPLIANCE: NON-COMPLIANT FILES PREVIEW: ['/home/dinesha/workarea/opencore/git/yifive_r0/read.me', '/home/dinesha/workarea/opencore/git/yifive_r0/caravel/openlane/user_analog_project_wrapper_empty/or_ioplace.tcl', '/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/tbuart.v', '/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/spiflash.v', '/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v', '/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/mgmt_soc/qspi/qspi_tb.v', '/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v', '/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v', '/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/mgmt_soc/storage/storage_tb.v', '/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/mgmt_soc/caravan/caravan_tb.v', '/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v', '/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v', '/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v', '/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/rtl/simpleuart.v', '/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/rtl/picorv32.v', '/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/rtl/mgmt_soc.v', '/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/rtl/spimemio.v', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/default.cvcrc', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/config.1.tcl', '/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/config.tcl']
+ Executing Step 2 of 8: YAML File Check
+ YAML file valid!
+Step 2 done without fatal errors.
+ Detected Project Type is "digital"
+ Executing Step 3 of 8: Project Compliance Checks
+b'Going into /home/dinesha/workarea/efabless/caravel'
+b'Removing manifest'
+b'Fetching manifest'
+b'Running sha1sum checks'
+ Manifest Checks Failed. Please rebase your Repository to the latest Caravel master.
+verilog/rtl/mgmt_core.v: FAILED
+verilog/rtl/mgmt_soc.v: FAILED
+verilog/rtl/wb_intercon.v: FAILED
diff --git a/checks/manifest_check.log b/checks/manifest_check.log
new file mode 100644
index 0000000..94c2d81
--- /dev/null
+++ b/checks/manifest_check.log
@@ -0,0 +1,47 @@
+verilog/rtl/DFFRAM.v: OK
+verilog/rtl/DFFRAMBB.v: OK
+verilog/rtl/__uprj_analog_netlists.v: OK
+verilog/rtl/__uprj_netlists.v: OK
+verilog/rtl/__user_analog_project_wrapper.v: OK
+verilog/rtl/__user_project_wrapper.v: OK
+verilog/rtl/caravan.v: OK
+verilog/rtl/caravan_netlists.v: OK
+verilog/rtl/caravel.v: OK
+verilog/rtl/caravel_clocking.v: OK
+verilog/rtl/chip_io.v: OK
+verilog/rtl/chip_io_alt.v: OK
+verilog/rtl/clock_div.v: OK
+verilog/rtl/convert_gpio_sigs.v: OK
+verilog/rtl/counter_timer_high.v: OK
+verilog/rtl/counter_timer_low.v: OK
+verilog/rtl/digital_pll.v: OK
+verilog/rtl/digital_pll_controller.v: OK
+verilog/rtl/gpio_control_block.v: OK
+verilog/rtl/gpio_wb.v: OK
+verilog/rtl/housekeeping_spi.v: OK
+verilog/rtl/la_wb.v: OK
+verilog/rtl/mem_wb.v: OK
+verilog/rtl/mgmt_core.v: FAILED
+verilog/rtl/mgmt_protect.v: OK
+verilog/rtl/mgmt_protect_hv.v: OK
+verilog/rtl/mgmt_soc.v: FAILED
+verilog/rtl/mprj2_logic_high.v: OK
+verilog/rtl/mprj_ctrl.v: OK
+verilog/rtl/mprj_io.v: OK
+verilog/rtl/mprj_logic_high.v: OK
+verilog/rtl/pads.v: OK
+verilog/rtl/picorv32.v: OK
+verilog/rtl/ring_osc2x13.v: OK
+verilog/rtl/simple_por.v: OK
+verilog/rtl/simple_spi_master.v: OK
+verilog/rtl/simpleuart.v: OK
+verilog/rtl/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v: OK
+verilog/rtl/spimemio.v: OK
+verilog/rtl/sram_1rw1r_32_256_8_sky130.v: OK
+verilog/rtl/storage.v: OK
+verilog/rtl/storage_bridge_wb.v: OK
+verilog/rtl/sysctrl.v: OK
+verilog/rtl/wb_intercon.v: FAILED
+scripts/set_user_id.py: OK
+scripts/generate_fill.py: OK
+scripts/compositor.py: OK
diff --git a/checks/spdx_compliance_report.log b/checks/spdx_compliance_report.log
new file mode 100644
index 0000000..0f040f1
--- /dev/null
+++ b/checks/spdx_compliance_report.log
@@ -0,0 +1,529 @@
+FULL RUN LOG:
+SPDX NON-COMPLIANT FILES
+/home/dinesha/workarea/opencore/git/yifive_r0/read.me
+/home/dinesha/workarea/opencore/git/yifive_r0/caravel/openlane/user_analog_project_wrapper_empty/or_ioplace.tcl
+/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/tbuart.v
+/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/spiflash.v
+/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v
+/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/mgmt_soc/qspi/qspi_tb.v
+/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v
+/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v
+/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/mgmt_soc/storage/storage_tb.v
+/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/mgmt_soc/caravan/caravan_tb.v
+/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v
+/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v
+/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
+/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/rtl/simpleuart.v
+/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/rtl/picorv32.v
+/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/rtl/mgmt_soc.v
+/home/dinesha/workarea/opencore/git/yifive_r0/caravel/verilog/rtl/spimemio.v
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/default.cvcrc
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/config.1.tcl
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/config.tcl
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/config.tcl
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic_spice.tcl
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/opt.lib
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/trimmed.lib
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/tracks_copy.info
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/sky130_fd_sc_hd__tt_025C_1v80.no_pg.lib
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/synthesis/hierarchy.dot
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/synthesis/yosys.sdc
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/routing/20-tritonRoute.param
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/routing/20-tritonRoute.guide
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/routing/17-fastroute.guide
+/home/dinesha/workarea/opencore/git/yifive_r0/openlane/syntacore/runs/syntacore/tmp/magic/sky130_fd_sc_hd__conb_1.ext
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diff --git a/docs/source/_static/YiFive_Soc_BlockDiagram.odg b/docs/source/_static/YiFive_Soc_BlockDiagram.odg
deleted file mode 100644
index 50ecb7c..0000000
--- a/docs/source/_static/YiFive_Soc_BlockDiagram.odg
+++ /dev/null
Binary files differ
diff --git a/docs/source/_static/YiFve_Soc_Design_Document.docx b/docs/source/_static/YiFve_Soc_Design_Document.docx
deleted file mode 100644
index 0ddf5b2..0000000
--- a/docs/source/_static/YiFve_Soc_Design_Document.docx
+++ /dev/null
Binary files differ
diff --git a/openlane/glbl_cfg/base.sdc b/openlane/glbl_cfg/base.sdc
new file mode 100644
index 0000000..d57972b
--- /dev/null
+++ b/openlane/glbl_cfg/base.sdc
@@ -0,0 +1,62 @@
+set_units -time ns
+set ::env(WB_CLOCK_PERIOD) "10"
+set ::env(WB_CLOCK_PORT) "mclk"
+
+######################################
+# WB Clock domain input output
+######################################
+create_clock [get_ports $::env(WB_CLOCK_PORT)]  -name $::env(WB_CLOCK_PORT)  -period $::env(WB_CLOCK_PERIOD)
+set wb_input_delay_value [expr $::env(WB_CLOCK_PERIOD) * 0.6]
+set wb_output_delay_value [expr $::env(WB_CLOCK_PERIOD) * 0.6]
+puts "\[INFO\]: Setting wb output delay to:$wb_output_delay_value"
+puts "\[INFO\]: Setting wb input delay to: $wb_input_delay_value"
+
+
+set_input_delay 2.0 -clock [get_clocks $::env(WB_CLOCK_PORT)] {reset_n}
+
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port reg_cs*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port reg_wr*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port reg_addr*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port reg_wdata*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port reg_be*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port sdr_init_done*]
+
+set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port device_idcode*]
+set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port reg_rdata*]
+set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port reg_ack*]
+set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port fuse_mhartid*]
+set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port irq_lines*]
+set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port soft_irq*]
+set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port user_irq*]
+set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_width*]
+set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_colbits*]
+set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_tras_d*]
+set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_trp_d*]
+set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_trcd_d*]
+set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_en*]
+set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_req_depth*]
+set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_mode_reg*]
+set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_cas*]
+set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_trcar_d*]
+set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_twr_d*]
+set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_rfsh*]
+set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_cas*]
+set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_trcar_d*]
+set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_twr_d*]
+set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_rfsh*]
+
+
+# TODO set this as parameter
+set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
+set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load  $cap_load [all_outputs]
+
+## These are generated clock, only max delay added
+set_false_path -to [get_port sdram_clk] 
+set_false_path -to [get_port cpu_clk] 
+set_false_path -to [get_port rtc_clk] 
+
+#set_max_delay 2.0 [get_port sdram_clk]
+#set_max_delay 2.0 [get_port cpu_clk]
+#set_max_delay 2.0 [get_port rtc_clk]
diff --git a/openlane/glbl_cfg/config.tcl b/openlane/glbl_cfg/config.tcl
new file mode 100755
index 0000000..d17529f
--- /dev/null
+++ b/openlane/glbl_cfg/config.tcl
@@ -0,0 +1,61 @@
+# Global
+# ------
+
+set script_dir [file dirname [file normalize [info script]]]
+# Name
+set ::env(DESIGN_NAME) glbl_cfg
+set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
+
+#set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+
+# Timing configuration
+set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PORT) "mclk"
+
+set ::env(SYNTH_MAX_FANOUT) 4
+
+# Sources
+# -------
+
+# Local sources + no2usb sources
+set ::env(VERILOG_FILES) "\
+        $script_dir/../../verilog/rtl/lib/registers.v                  \
+        $script_dir/../../verilog/rtl/lib/clk_ctl.v                    \
+        $script_dir/../../verilog/rtl/digital_core/src/glbl_cfg.sv     \
+	"
+
+set ::env(SDC_FILE) "$script_dir/base.sdc"
+set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
+
+
+# Floorplanning
+# -------------
+
+set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 400 300"
+
+
+
+set ::env(FP_PDN_VPITCH) 50
+set ::env(PDN_CFG) $script_dir/pdn.tcl
+
+set ::env(FP_VERTICAL_HALO) 6
+set ::env(PL_TARGET_DENSITY) 0.52
+set ::env(PL_TARGET_DENSITY_CELLS) 0.38
+set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 1
+set ::env(CELL_PAD) 4
+
+set ::env(GLB_RT_ADJUSTMENT) 0
+set ::env(GLB_RT_L2_ADJUSTMENT) 0.2
+set ::env(GLB_RT_L3_ADJUSTMENT) 0.25
+set ::env(GLB_RT_L4_ADJUSTMENT) 0.2
+set ::env(GLB_RT_L5_ADJUSTMENT) 0.1
+set ::env(GLB_RT_L6_ADJUSTMENT) 0.1
+set ::env(GLB_RT_TILES) 14
+set ::env(GLB_RT_MAXLAYER) 5
+
+set ::env(DIODE_INSERTION_STRATEGY) 4
+
+
diff --git a/openlane/glbl_cfg/pdn.tcl b/openlane/glbl_cfg/pdn.tcl
new file mode 100644
index 0000000..1fe689b
--- /dev/null
+++ b/openlane/glbl_cfg/pdn.tcl
@@ -0,0 +1,49 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# Power nets
+set ::power_nets $::env(VDD_PIN)
+set ::ground_nets $::env(GND_PIN)
+
+set ::macro_blockage_layer_list "li1 met1 met2 met3 met4 met5"
+
+pdngen::specify_grid stdcell {
+    name grid
+    rails {
+	    met1 {width 0.48 pitch $::env(PLACE_SITE_HEIGHT) offset 0}
+    }
+    straps {
+	    met4 {width 1.6 pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)}
+	    met5 {width 1.6 pitch $::env(FP_PDN_HPITCH) offset $::env(FP_PDN_HOFFSET)}
+    }
+    connect {{met1 met4} {met4 met5}}
+}
+
+pdngen::specify_grid macro {
+    power_pins "VPWR"
+    ground_pins "VGND"
+    blockages "li1 met1 met2 met3 met4"
+    straps { 
+    } 
+    connect {{met4_PIN_ver met5}}
+}
+
+set ::halo 5
+
+# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
+set ::rails_start_with "POWER" ;
+
+# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
+set ::stripes_start_with "POWER" ;
diff --git a/openlane/glbl_cfg/pin_order.cfg b/openlane/glbl_cfg/pin_order.cfg
new file mode 100644
index 0000000..784fe9b
--- /dev/null
+++ b/openlane/glbl_cfg/pin_order.cfg
@@ -0,0 +1,47 @@
+#BUS_SORT
+
+#E
+cpu_clk
+rtc_clk
+cpu_rst_n
+irq_lines.*
+soft_irq
+fuse_mhartid.*
+
+#N
+mclk
+reset_n
+user_clock2
+spi_rst_n
+user_irq.*
+events_o.*
+device_idcode.*
+
+#W
+sdram_clk
+sdram_rst_n
+sdr_init_done
+cfg_sdr_width.*
+cfg_colbits.*
+cfg_sdr_tras_d.*
+cfg_sdr_trp_d.*
+cfg_sdr_trcd_d.*
+cfg_sdr_en.*
+cfg_req_depth.*
+cfg_sdr_mode_reg.*
+cfg_sdr_cas.*
+cfg_sdr_trcar_d.*
+cfg_sdr_twr_d.*
+cfg_sdr_rfsh.*
+cfg_sdr_rfmax.*
+
+
+#S
+reg_cs
+reg_wr
+reg_addr.*
+reg_be.*
+reg_wdata.*
+reg_rdata.*
+reg_ack
+
diff --git a/openlane/sdram/base.sdc b/openlane/sdram/base.sdc
new file mode 100644
index 0000000..9fd9ca2
--- /dev/null
+++ b/openlane/sdram/base.sdc
@@ -0,0 +1,84 @@
+set_units -time ns
+set ::env(WB_CLOCK_PERIOD) "10"
+set ::env(WB_CLOCK_PORT)   "wb_clk_i"
+
+set ::env(SDRAM_CLOCK_PERIOD) "20"
+set ::env(SDRAM_CLOCK_PORT)   "sdram_clk"
+
+set ::env(PAD_SDRAM_CLOCK_PERIOD) "20"
+set ::env(PAD_SDRAM_CLOCK_PORT)   "sdram_pad_clk"
+######################################
+# WB Clock domain input output
+######################################
+create_clock [get_ports $::env(WB_CLOCK_PORT)]  -name $::env(WB_CLOCK_PORT)  -period $::env(WB_CLOCK_PERIOD)
+set wb_input_delay_value [expr $::env(WB_CLOCK_PERIOD) * 0.6]
+set wb_output_delay_value [expr $::env(WB_CLOCK_PERIOD) * 0.6]
+puts "\[INFO\]: Setting wb output delay to:$wb_output_delay_value"
+puts "\[INFO\]: Setting wb input delay to: $wb_input_delay_value"
+
+
+set_input_delay 2.0 -clock [get_clocks $::env(WB_CLOCK_PORT)] {wb_rst_i}
+
+set_input_delay  3.0                     -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_stb_i*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_addr_i*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_we_i*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_dat_i*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_sel_i*]
+set_input_delay  3.0                     -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_cyc_i*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_cti_i*]
+
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_tras_d*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_trp_d*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_trcd_d*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_en*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_req_depth*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_mode_reg*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_cas*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_trcar_d*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_twr_d*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_rfsh*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_rfmax*]
+
+set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_dat_o*]
+set_output_delay 3.0                     -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_ack_o*]
+set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port sdr_init_done*]
+
+######################################
+# SDRAM Clock domain input output
+######################################
+create_clock [get_ports $::env(SDRAM_CLOCK_PORT)]  -name $::env(SDRAM_CLOCK_PORT)  -period $::env(SDRAM_CLOCK_PERIOD)
+set sdram_input_delay_value [expr $::env(SDRAM_CLOCK_PERIOD) * 0.6]
+set sdram_output_delay_value [expr $::env(SDRAM_CLOCK_PERIOD) * 0.6]
+puts "\[INFO\]: Setting wb output delay to:$wb_output_delay_value"
+puts "\[INFO\]: Setting wb input delay to: $wb_input_delay_value"
+
+set_output_delay $sdram_output_delay_value  -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port sdr_cke*]
+set_output_delay $sdram_output_delay_value  -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port sdr_cs_n*]
+set_output_delay $sdram_output_delay_value  -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port sdr_ras_n*]
+set_output_delay $sdram_output_delay_value  -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port sdr_cas_n*]
+set_output_delay $sdram_output_delay_value  -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port sdr_we_n*]
+set_output_delay $sdram_output_delay_value  -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port sdr_dqm*]
+set_output_delay $sdram_output_delay_value  -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port sdr_ba*]
+set_output_delay $sdram_output_delay_value  -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port sdr_addr*]
+set_output_delay $sdram_output_delay_value  -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port sdr_dout*]
+set_output_delay $sdram_output_delay_value  -clock [get_clocks $::env(SDRAM_CLOCK_PORT)] [get_port sdr_den_n*]
+
+################################################
+# PAD SDRAM Clock domain input output
+# Note: PAD SDRAM clock is same as SDRAM clock
+#       it's a feedback clock through pads
+################################################
+
+create_clock [get_ports $::env(PAD_SDRAM_CLOCK_PORT)]  -name $::env(PAD_SDRAM_CLOCK_PORT)  -period $::env(SDRAM_CLOCK_PERIOD)
+set_input_delay  $sdram_input_delay_value   -clock [get_clocks $::env(PAD_SDRAM_CLOCK_PORT)] [get_port pad_sdr_din*]
+
+
+set_clock_groups -name async_clock -asynchronous -comment "Async Clock group" -group [get_clocks $::env(WB_CLOCK_PORT)] -group [get_clocks $::env(SDRAM_CLOCK_PORT)]
+
+
+# TODO set this as parameter
+set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
+set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load  $cap_load [all_outputs]
+
diff --git a/openlane/sdram/config.tcl b/openlane/sdram/config.tcl
index 6d6fa7c..796a40c 100755
--- a/openlane/sdram/config.tcl
+++ b/openlane/sdram/config.tcl
@@ -5,20 +5,11 @@
 # Name
 set ::env(DESIGN_NAME) sdrc_top
 
-# This is macro
-set ::env(DESIGN_IS_CORE) 0
 
-# Diode insertion
-	#  Spray
-set ::env(DIODE_INSERTION_STRATEGY) 0
-
-	# Smart-"ish"
-#set ::env(DIODE_INSERTION_STRATEGY) 3
-#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
 
 # Timing configuration
 set ::env(CLOCK_PERIOD) "10"
-set ::env(CLOCK_PORT) "wb_clk_i"
+set ::env(CLOCK_PORT) "wb_clk_i sdram_clk sdram_pad_clk"
 
 
 # Sources
@@ -38,84 +29,38 @@
 
 set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/sdram_ctrl/src/defs ]
 
-#set ::env(SYNTH_DEFINES) [list SCR1_DBG_EN ]
-
-
-# Need blackbox for cells
-set ::env(SYNTH_READ_BLACKBOX_LIB) 0
+set ::env(SDC_FILE) "$script_dir/base.sdc"
+set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
 
 
 # Floorplanning
 # -------------
 
-# Fixed area and pin position
-set ::env(FP_SIZING) "absolute"
-#actual die area is 0 0 2920 3520, given 500 micron extra margin
-set ::env(DIE_AREA) [list 0.0 0.0 1000.0 300.0]
 set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
-
-# Halo around the Macros
-set ::env(FP_HORIZONTAL_HALO) 25
-set ::env(FP_VERTICAL_HALO) 20
-
-#set ::env(PDN_CFG) $::env(DESIGN_DIR)/pdn.tcl
+set ::env(FP_SIZING) "absolute"
+set ::env(DIE_AREA) [list 0.0 0.0 900.0 300.0]
 
 
 
-# Placement
-# ---------
 
-set ::env(PL_TARGET_DENSITY) 0.40
+set ::env(FP_PDN_VPITCH) 50
+set ::env(PDN_CFG) $script_dir/pdn.tcl
 
-#set ::env(MACRO_PLACEMENT_CFG) $::env(DESIGN_DIR)/macro_placement.cfg
+set ::env(FP_VERTICAL_HALO) 6
+set ::env(PL_TARGET_DENSITY) 0.52
+set ::env(PL_TARGET_DENSITY_CELLS) 0.38
+set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 1
+set ::env(CELL_PAD) 4
+
+set ::env(GLB_RT_ADJUSTMENT) 0
+set ::env(GLB_RT_L2_ADJUSTMENT) 0.2
+set ::env(GLB_RT_L3_ADJUSTMENT) 0.25
+set ::env(GLB_RT_L4_ADJUSTMENT) 0.2
+set ::env(GLB_RT_L5_ADJUSTMENT) 0.1
+set ::env(GLB_RT_L6_ADJUSTMENT) 0.1
+set ::env(GLB_RT_TILES) 14
+set ::env(GLB_RT_MAXLAYER) 5
+
+set ::env(DIODE_INSERTION_STRATEGY) 4
 
 
-# Routing
-# -------
-
-#| `ROUTING_CORES` | Specifies the number of threads to be used in TritonRoute. <br> (Default: `4`) |
-set ::env(ROUTING_CORES) 4
-
-#| `GLB_RT_ALLOW_CONGESTION` | Allow congestion in the resultign guides. 0 = false, 1 = true <br> (Default: `0`) |
-set ::env(GLB_RT_ALLOW_CONGESTION) 0
-
-# | `GLB_RT_MINLAYER` | The number of lowest layer to be used in routing. <br> (Default: `1`)|
-set ::env(GLB_RT_MINLAYER) 1
-
-# | `GLB_RT_MAXLAYER` | The number of highest layer to be used in routing. <br> (Default: `6`)|
-set ::env(GLB_RT_MAXLAYER) 6
-
-# Obstructions
-    # li1 over the SRAM areas
-	# met5 over the whole design
-#set ::env(GLB_RT_OBS) "li1 0.00 22.68 1748.00 486.24, li1 0.00 851.08 1748.00 486.24, met5 0.0 0.0 1748.0 1360.0"
-
-#| `ROUTING_OPT_ITERS` | Specifies the maximum number of optimization iterations during Detailed Routing in TritonRoute. <br> (Default: `64`) |
-set ::env(ROUTING_OPT_ITERS) "64"
-
-#| `GLOBAL_ROUTER` | Specifies which global router to use. Values: `fastroute` or `cugr`. <br> (Default: `fastroute`) |
-set ::env(GLOBAL_ROUTER) "fastroute"
-
-#| `DETAILED_ROUTER` | Specifies which detailed router to use. Values: `tritonroute`, `tritonroute_or`, or `drcu`. <br> (Default: `tritonroute`) |
-set ::env(DETAILED_ROUTER) "tritonroute"
-
-# DRC
-# ---
-
-
-set ::env(MAGIC_DRC_USE_GDS) 1
-
-
-# Tape Out
-# --------
-
-set ::env(MAGIC_ZEROIZE_ORIGIN) 0
-
-
-# Cell library specific config
-# ----------------------------
-
-set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
-if { [file exists $filename] == 1} {
-	source $filename
-}
diff --git a/openlane/sdram/pdn.tcl b/openlane/sdram/pdn.tcl
new file mode 100644
index 0000000..1fe689b
--- /dev/null
+++ b/openlane/sdram/pdn.tcl
@@ -0,0 +1,49 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# Power nets
+set ::power_nets $::env(VDD_PIN)
+set ::ground_nets $::env(GND_PIN)
+
+set ::macro_blockage_layer_list "li1 met1 met2 met3 met4 met5"
+
+pdngen::specify_grid stdcell {
+    name grid
+    rails {
+	    met1 {width 0.48 pitch $::env(PLACE_SITE_HEIGHT) offset 0}
+    }
+    straps {
+	    met4 {width 1.6 pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)}
+	    met5 {width 1.6 pitch $::env(FP_PDN_HPITCH) offset $::env(FP_PDN_HOFFSET)}
+    }
+    connect {{met1 met4} {met4 met5}}
+}
+
+pdngen::specify_grid macro {
+    power_pins "VPWR"
+    ground_pins "VGND"
+    blockages "li1 met1 met2 met3 met4"
+    straps { 
+    } 
+    connect {{met4_PIN_ver met5}}
+}
+
+set ::halo 5
+
+# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
+set ::rails_start_with "POWER" ;
+
+# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
+set ::stripes_start_with "POWER" ;
diff --git a/openlane/sdram/pin_order.cfg b/openlane/sdram/pin_order.cfg
index 691cdfa..52236e6 100644
--- a/openlane/sdram/pin_order.cfg
+++ b/openlane/sdram/pin_order.cfg
@@ -1,51 +1,52 @@
 #BUS_SORT
 
-#E
-wb_clk_i, 
-wb_rst_i, 
-sdram_resetn, 
-sdram_clk, 
+#W
+wb_clk_i 
+wb_rst_i 
 
 
 
-#S
-sdr_cas_n, 
-sdr_cke, 
-sdr_cs_n, 
-sdr_dqm, 
-sdr_ras_n, 
-sdr_we_n, 
+#N
+sdr_cas_n 
+sdr_cke 
+sdr_cs_n
+sdr_dqm 
+sdr_ras_n 
+sdr_we_n 
 sdr_addr.*
 sdr_ba.*
 pad_sdr_din.*
 sdr_dout.*
-sdr_den_n, 
-sdram_pad_clk, 
+sdr_den_n 
+sdram_pad_clk 
 
 
-#W
-sdr_init_done, 
-cfg_sdr_en, 
-cfg_colbits.*
-cfg_req_depth.*
-cfg_sdr_cas.*
-cfg_sdr_mode_reg.*
-cfg_sdr_rfmax.*
-cfg_sdr_rfsh.*
-cfg_sdr_trcar_d.*
-cfg_sdr_trcd_d.*
-cfg_sdr_trp_d.*
-cfg_sdr_twr_d.*
+#E
+sdram_clk
+sdram_resetn
+sdr_init_done 
 cfg_sdr_width.*
+cfg_colbits.*
+cfg_sdr_tras_d.*
+cfg_sdr_trp_d.*
+cfg_sdr_trcd_d.*
+cfg_sdr_en.*
+cfg_req_depth.*
+cfg_sdr_mode_reg.*
+cfg_sdr_cas.*
+cfg_sdr_trcar_d.*
+cfg_sdr_twr_d.*
+cfg_sdr_rfsh.*
+cfg_sdr_rfmax.*
 
 
-#N
-wb_stb_i, 
-wb_we_i, 
+#S
+wb_stb_i 
+wb_we_i 
 wb_addr_i.*
 wb_sel_i.*
 wb_dat_i.*
 wb_dat_o.*
-wb_ack_o, 
+wb_ack_o 
 wb_cyc_i, 
 wb_cti_i.*
diff --git a/openlane/spi_master/base.sdc b/openlane/spi_master/base.sdc
new file mode 100644
index 0000000..af8edee
--- /dev/null
+++ b/openlane/spi_master/base.sdc
@@ -0,0 +1,50 @@
+set_units -time ns
+set ::env(WB_CLOCK_PERIOD) "10"
+set ::env(WB_CLOCK_PORT) "mclk"
+
+######################################
+# WB Clock domain input output
+######################################
+create_clock [get_ports $::env(WB_CLOCK_PORT)]  -name $::env(WB_CLOCK_PORT)  -period $::env(WB_CLOCK_PERIOD)
+set wb_input_delay_value [expr $::env(WB_CLOCK_PERIOD) * 0.6]
+set wb_output_delay_value [expr $::env(WB_CLOCK_PERIOD) * 0.6]
+puts "\[INFO\]: Setting wb output delay to:$wb_output_delay_value"
+puts "\[INFO\]: Setting wb input delay to: $wb_input_delay_value"
+
+
+set_input_delay 2.0 -clock [get_clocks $::env(WB_CLOCK_PORT)] {rst_n}
+
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbd_stb_i*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbd_adr_i*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbd_we_i*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbd_dat_i*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbd_sel_i*]
+
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port spi_sdi0*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port spi_sdi1*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port spi_sdi2*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port spi_sdi3*]
+
+set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbd_dat_o*]
+set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbd_ack_o*]
+set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbd_err_o*]
+set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port events_o*]
+set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port spi_clk*]
+set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port spi_csn0*]
+set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port spi_csn1*]
+set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port spi_csn2*]
+set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port spi_csn2*]
+set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port spi_csn3*]
+set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port spi_mode*]
+set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port spi_sdo0*]
+set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port spi_sdo1*]
+set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port spi_sdo2*]
+set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port spi_sdo3*]
+set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port spi_en_tx*]
+
+# TODO set this as parameter
+set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
+set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load  $cap_load [all_outputs]
+
diff --git a/openlane/spi_master/config.tcl b/openlane/spi_master/config.tcl
index b69e7cf..584bda3 100755
--- a/openlane/spi_master/config.tcl
+++ b/openlane/spi_master/config.tcl
@@ -3,23 +3,14 @@
 
 set script_dir [file dirname [file normalize [info script]]]
 # Name
+
 set ::env(DESIGN_NAME) spim_top
 
-# This is macro
-set ::env(DESIGN_IS_CORE) 0
-
-# Diode insertion
-	#  Spray
-set ::env(DIODE_INSERTION_STRATEGY) 0
-
-	# Smart-"ish"
-#set ::env(DIODE_INSERTION_STRATEGY) 3
-#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
-
 # Timing configuration
 set ::env(CLOCK_PERIOD) "10"
 set ::env(CLOCK_PORT) "mclk"
 
+set ::env(SYNTH_MAX_FANOUT) 4
 
 # Sources
 # -------
@@ -33,86 +24,38 @@
         $script_dir/../../verilog/rtl/spi_master/src/spim_rx.sv \
         $script_dir/../../verilog/rtl/spi_master/src/spim_tx.sv "
 
-#set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/syntacore/scr1/src/includes ]
-
-#set ::env(SYNTH_DEFINES) [list SCR1_DBG_EN ]
-
-
-# Need blackbox for cells
-set ::env(SYNTH_READ_BLACKBOX_LIB) 0
+set ::env(SDC_FILE) "$script_dir/base.sdc"
+set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
 
 
 # Floorplanning
 # -------------
 
-# Fixed area and pin position
-set ::env(FP_SIZING) "absolute"
-#actual die area is 0 0 2920 3520, given 500 micron extra margin
-set ::env(DIE_AREA) [list 0.0 0.0 300.0 300.0]
 set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
 
-# Halo around the Macros
-set ::env(FP_HORIZONTAL_HALO) 25
-set ::env(FP_VERTICAL_HALO) 20
-
-#set ::env(PDN_CFG) $::env(DESIGN_DIR)/pdn.tcl
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 600 500"
 
 
 
-# Placement
-# ---------
+set ::env(FP_PDN_VPITCH) 50
+set ::env(PDN_CFG) $script_dir/pdn.tcl
 
-set ::env(PL_TARGET_DENSITY) 0.40
+set ::env(FP_VERTICAL_HALO) 6
+set ::env(PL_TARGET_DENSITY) 0.52
+set ::env(PL_TARGET_DENSITY_CELLS) 0.38
+set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 1
+set ::env(CELL_PAD) 4
 
-#set ::env(MACRO_PLACEMENT_CFG) $::env(DESIGN_DIR)/macro_placement.cfg
+set ::env(GLB_RT_ADJUSTMENT) 0
+set ::env(GLB_RT_L2_ADJUSTMENT) 0.2
+set ::env(GLB_RT_L3_ADJUSTMENT) 0.25
+set ::env(GLB_RT_L4_ADJUSTMENT) 0.2
+set ::env(GLB_RT_L5_ADJUSTMENT) 0.1
+set ::env(GLB_RT_L6_ADJUSTMENT) 0.1
+set ::env(GLB_RT_TILES) 14
+set ::env(GLB_RT_MAXLAYER) 5
+
+set ::env(DIODE_INSERTION_STRATEGY) 4
 
 
-# Routing
-# -------
-
-#| `ROUTING_CORES` | Specifies the number of threads to be used in TritonRoute. <br> (Default: `4`) |
-set ::env(ROUTING_CORES) 4
-
-#| `GLB_RT_ALLOW_CONGESTION` | Allow congestion in the resultign guides. 0 = false, 1 = true <br> (Default: `0`) |
-set ::env(GLB_RT_ALLOW_CONGESTION) 0
-
-# | `GLB_RT_MINLAYER` | The number of lowest layer to be used in routing. <br> (Default: `1`)|
-set ::env(GLB_RT_MINLAYER) 1
-
-# | `GLB_RT_MAXLAYER` | The number of highest layer to be used in routing. <br> (Default: `6`)|
-set ::env(GLB_RT_MAXLAYER) 6
-
-# Obstructions
-    # li1 over the SRAM areas
-	# met5 over the whole design
-#set ::env(GLB_RT_OBS) "li1 0.00 22.68 1748.00 486.24, li1 0.00 851.08 1748.00 486.24, met5 0.0 0.0 1748.0 1360.0"
-
-#| `ROUTING_OPT_ITERS` | Specifies the maximum number of optimization iterations during Detailed Routing in TritonRoute. <br> (Default: `64`) |
-set ::env(ROUTING_OPT_ITERS) "64"
-
-#| `GLOBAL_ROUTER` | Specifies which global router to use. Values: `fastroute` or `cugr`. <br> (Default: `fastroute`) |
-set ::env(GLOBAL_ROUTER) "fastroute"
-
-#| `DETAILED_ROUTER` | Specifies which detailed router to use. Values: `tritonroute`, `tritonroute_or`, or `drcu`. <br> (Default: `tritonroute`) |
-set ::env(DETAILED_ROUTER) "tritonroute"
-
-# DRC
-# ---
-
-
-set ::env(MAGIC_DRC_USE_GDS) 1
-
-
-# Tape Out
-# --------
-
-set ::env(MAGIC_ZEROIZE_ORIGIN) 0
-
-
-# Cell library specific config
-# ----------------------------
-
-set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
-if { [file exists $filename] == 1} {
-	source $filename
-}
diff --git a/openlane/spi_master/pdn.tcl b/openlane/spi_master/pdn.tcl
new file mode 100644
index 0000000..1fe689b
--- /dev/null
+++ b/openlane/spi_master/pdn.tcl
@@ -0,0 +1,49 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# Power nets
+set ::power_nets $::env(VDD_PIN)
+set ::ground_nets $::env(GND_PIN)
+
+set ::macro_blockage_layer_list "li1 met1 met2 met3 met4 met5"
+
+pdngen::specify_grid stdcell {
+    name grid
+    rails {
+	    met1 {width 0.48 pitch $::env(PLACE_SITE_HEIGHT) offset 0}
+    }
+    straps {
+	    met4 {width 1.6 pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)}
+	    met5 {width 1.6 pitch $::env(FP_PDN_HPITCH) offset $::env(FP_PDN_HOFFSET)}
+    }
+    connect {{met1 met4} {met4 met5}}
+}
+
+pdngen::specify_grid macro {
+    power_pins "VPWR"
+    ground_pins "VGND"
+    blockages "li1 met1 met2 met3 met4"
+    straps { 
+    } 
+    connect {{met4_PIN_ver met5}}
+}
+
+set ::halo 5
+
+# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
+set ::rails_start_with "POWER" ;
+
+# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
+set ::stripes_start_with "POWER" ;
diff --git a/openlane/spi_master/pin_order.cfg b/openlane/spi_master/pin_order.cfg
index afd59ee..23b1cf5 100644
--- a/openlane/spi_master/pin_order.cfg
+++ b/openlane/spi_master/pin_order.cfg
@@ -24,7 +24,7 @@
 spi_sdo3
 
 
-#N
+#S
 wbd_stb_i
 wbd_we_i
 wbd_adr_i.*
diff --git a/openlane/syntacore/base.sdc b/openlane/syntacore/base.sdc
new file mode 100644
index 0000000..0bb30a6
--- /dev/null
+++ b/openlane/syntacore/base.sdc
@@ -0,0 +1,49 @@
+set_units -time ns
+#Wishbone Clock
+set ::env(WB_CLOCK_PERIOD)    "10"
+set ::env(WB_CLOCK_PORT)      "wb_clk"
+
+#Risc Core Clock
+set ::env(CORE_CLOCK_PERIOD) "50"
+set ::env(CORE_CLOCK_PORT)   "core_clk"
+
+######################################
+# CORE Clock domain input output
+######################################
+create_clock [get_ports $::env(CORE_CLOCK_PORT)]  -name $::env(CORE_CLOCK_PORT)  -period $::env(CORE_CLOCK_PERIOD)
+set core_input_delay_value [expr $::env(CORE_CLOCK_PERIOD) * 0.6]
+set core_output_delay_value [expr $::env(CORE_CLOCK_PERIOD) * 0.6]
+puts "\[INFO\]: Setting core output delay to: $core_output_delay_value"
+puts "\[INFO\]: Setting core input delay to: $core_input_delay_value"
+set core_clk_indx [lsearch [all_inputs] [get_port $::env(CORE_CLOCK_PORT)]]
+set core_rst_indx [lsearch [all_inputs] [get_port cpu_rst_n]]
+set all_inputs_wo_core_clk_rst [lreplace [all_inputs] $core_clk_indx $core_rst_indx]
+set all_outputs_core [all_outputs] 
+
+set_input_delay $core_input_delay_value  -clock [get_clocks $::env(CORE_CLOCK_PORT)] $all_inputs_wo_core_clk_rst
+set_input_delay 5.0 -clock [get_clocks $::env(CORE_CLOCK_PORT)] {cpu_rst_n}
+set_output_delay $core_output_delay_value  -clock [get_clocks $::env(CORE_CLOCK_PORT)] $all_outputs_core
+
+######################################
+# WB Clock domain input output
+######################################
+create_clock [get_ports $::env(WB_CLOCK_PORT)]  -name $::env(WB_CLOCK_PORT)  -period $::env(WB_CLOCK_PERIOD)
+set wb_input_delay_value [expr $::env(WB_CLOCK_PERIOD) * 0.6]
+set wb_output_delay_value [expr $::env(WB_CLOCK_PERIOD) * 0.6]
+puts "\[INFO\]: Setting wb output delay to:$wb_output_delay_value"
+puts "\[INFO\]: Setting wb input delay to: $wb_input_delay_value"
+set wb_clk_indx [lsearch [all_inputs] [get_port $::env(WB_CLOCK_PORT)]]
+set wb_rst_indx [lsearch [all_inputs] [get_port wb_rst_n]]
+set all_inputs_wo_wb_clk_rst [lreplace [all_inputs] $wb_clk_indx $wb_rst_indx]
+set all_outputs_wb [all_outputs]
+
+set_input_delay $wb_input_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] $all_inputs_wo_wb_clk_rst
+set_input_delay 5.0 -clock [get_clocks $::env(WB_CLOCK_PORT)] {wb_rst_n}
+set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] $all_outputs_wb
+
+
+# TODO set this as parameter
+set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
+set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load  $cap_load [all_outputs]
diff --git a/openlane/syntacore/config.tcl b/openlane/syntacore/config.tcl
index 766f736..994b399 100755
--- a/openlane/syntacore/config.tcl
+++ b/openlane/syntacore/config.tcl
@@ -5,21 +5,13 @@
 # Name
 set ::env(DESIGN_NAME) scr1_top_wb
 
-# This is macro
-set ::env(DESIGN_IS_CORE) 0
-
-# Diode insertion
-	#  Spray
-set ::env(DIODE_INSERTION_STRATEGY) 0
-
-	# Smart-"ish"
-#set ::env(DIODE_INSERTION_STRATEGY) 3
-#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
 
 # Timing configuration
 set ::env(CLOCK_PERIOD) "10"
-set ::env(CLOCK_PORT) "clk"
+set ::env(CLOCK_PORT) "wb_clk core_clk"
 
+set ::env(SYNTH_MAX_FANOUT) 4
 
 # Sources
 # -------
@@ -53,88 +45,45 @@
 	$script_dir/../../verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv   \
 	$script_dir/../../verilog/rtl/syntacore/scr1/src/top/scr1_dmem_wb.sv   \
 	$script_dir/../../verilog/rtl/syntacore/scr1/src/top/scr1_imem_wb.sv   \
-	$script_dir/../../verilog/rtl/lib/sync_fifo.sv "
+	$script_dir/../../verilog/rtl/lib/async_fifo.sv "
 
 set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/syntacore/scr1/src/includes ]
 
+set ::env(SDC_FILE) "$script_dir/base.sdc"
+set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
 #set ::env(SYNTH_DEFINES) [list SCR1_DBG_EN ]
 
 
-# Need blackbox for cells
-set ::env(SYNTH_READ_BLACKBOX_LIB) 0
-
-
+# --------
 # Floorplanning
 # -------------
 
-# Fixed area and pin position
-set ::env(FP_SIZING) "absolute"
-#actual die area is 0 0 2920 3520, given 500 micron extra margin
-set ::env(DIE_AREA) [list 0.0 0.0 2000.0 1200.0]
-set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
+set ::env(FP_DEF_TEMPLATE) $script_dir/floorplan.def
+#set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
 
-# Halo around the Macros
-set ::env(FP_HORIZONTAL_HALO) 25
-set ::env(FP_VERTICAL_HALO) 20
-
-#set ::env(PDN_CFG) $::env(DESIGN_DIR)/pdn.tcl
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) [list 0.0 0.0 1500.0 1200.0]
 
 
 
-# Placement
-# ---------
+set ::env(FP_PDN_VPITCH) 50
+set ::env(PDN_CFG) $script_dir/pdn.tcl
 
-set ::env(PL_TARGET_DENSITY) 0.40
+set ::env(FP_VERTICAL_HALO) 6
+set ::env(PL_TARGET_DENSITY) 0.52
+set ::env(PL_TARGET_DENSITY_CELLS) 0.38
+set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 1
+set ::env(CELL_PAD) 4
 
-#set ::env(MACRO_PLACEMENT_CFG) $::env(DESIGN_DIR)/macro_placement.cfg
+set ::env(GLB_RT_ADJUSTMENT) 0
+set ::env(GLB_RT_L2_ADJUSTMENT) 0.2
+set ::env(GLB_RT_L3_ADJUSTMENT) 0.25
+set ::env(GLB_RT_L4_ADJUSTMENT) 0.2
+set ::env(GLB_RT_L5_ADJUSTMENT) 0.1
+set ::env(GLB_RT_L6_ADJUSTMENT) 0.1
+set ::env(GLB_RT_TILES) 14
+set ::env(GLB_RT_MAXLAYER) 5
+
+set ::env(DIODE_INSERTION_STRATEGY) 4
 
 
-# Routing
-# -------
-
-#| `ROUTING_CORES` | Specifies the number of threads to be used in TritonRoute. <br> (Default: `4`) |
-set ::env(ROUTING_CORES) 4
-
-#| `GLB_RT_ALLOW_CONGESTION` | Allow congestion in the resultign guides. 0 = false, 1 = true <br> (Default: `0`) |
-set ::env(GLB_RT_ALLOW_CONGESTION) 0
-
-# | `GLB_RT_MINLAYER` | The number of lowest layer to be used in routing. <br> (Default: `1`)|
-set ::env(GLB_RT_MINLAYER) 1
-
-# | `GLB_RT_MAXLAYER` | The number of highest layer to be used in routing. <br> (Default: `6`)|
-set ::env(GLB_RT_MAXLAYER) 6
-
-# Obstructions
-    # li1 over the SRAM areas
-	# met5 over the whole design
-#set ::env(GLB_RT_OBS) "li1 0.00 22.68 1748.00 486.24, li1 0.00 851.08 1748.00 486.24, met5 0.0 0.0 1748.0 1360.0"
-
-#| `ROUTING_OPT_ITERS` | Specifies the maximum number of optimization iterations during Detailed Routing in TritonRoute. <br> (Default: `64`) |
-set ::env(ROUTING_OPT_ITERS) "64"
-
-#| `GLOBAL_ROUTER` | Specifies which global router to use. Values: `fastroute` or `cugr`. <br> (Default: `fastroute`) |
-set ::env(GLOBAL_ROUTER) "fastroute"
-
-#| `DETAILED_ROUTER` | Specifies which detailed router to use. Values: `tritonroute`, `tritonroute_or`, or `drcu`. <br> (Default: `tritonroute`) |
-set ::env(DETAILED_ROUTER) "tritonroute"
-
-# DRC
-# ---
-
-
-set ::env(MAGIC_DRC_USE_GDS) 1
-
-
-# Tape Out
-# --------
-
-set ::env(MAGIC_ZEROIZE_ORIGIN) 0
-
-
-# Cell library specific config
-# ----------------------------
-
-set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
-if { [file exists $filename] == 1} {
-	source $filename
-}
diff --git a/openlane/syntacore/pdn.tcl b/openlane/syntacore/pdn.tcl
new file mode 100644
index 0000000..1fe689b
--- /dev/null
+++ b/openlane/syntacore/pdn.tcl
@@ -0,0 +1,49 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# Power nets
+set ::power_nets $::env(VDD_PIN)
+set ::ground_nets $::env(GND_PIN)
+
+set ::macro_blockage_layer_list "li1 met1 met2 met3 met4 met5"
+
+pdngen::specify_grid stdcell {
+    name grid
+    rails {
+	    met1 {width 0.48 pitch $::env(PLACE_SITE_HEIGHT) offset 0}
+    }
+    straps {
+	    met4 {width 1.6 pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)}
+	    met5 {width 1.6 pitch $::env(FP_PDN_HPITCH) offset $::env(FP_PDN_HOFFSET)}
+    }
+    connect {{met1 met4} {met4 met5}}
+}
+
+pdngen::specify_grid macro {
+    power_pins "VPWR"
+    ground_pins "VGND"
+    blockages "li1 met1 met2 met3 met4"
+    straps { 
+    } 
+    connect {{met4_PIN_ver met5}}
+}
+
+set ::halo 5
+
+# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
+set ::rails_start_with "POWER" ;
+
+# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
+set ::stripes_start_with "POWER" ;
diff --git a/openlane/syntacore/pin_order.cfg b/openlane/syntacore/pin_order.cfg
index 398de52..a854d55 100644
--- a/openlane/syntacore/pin_order.cfg
+++ b/openlane/syntacore/pin_order.cfg
@@ -1,41 +1,34 @@
 #BUS_SORT
 #E
-clk
+core_clk
+rtc_clk
 cpu_rst_n
 irq_lines.*
-pwrup_rst_n
-rst_n
-rtc_clk
 soft_irq
-sys_rdc_qlfy_o
-sys_rst_n_o
-fuse_idcode.*
 fuse_mhartid.*
 
 #W
-tck
-tdi
-tdo
-tdo_en
-test_mode
-test_rst_n
-tms
-trst_n
+wb_clk
+wb_rst_n
+pwrup_rst_n
+rst_n
+sys_rdc_qlfy_o
+sys_rst_n_o
 
-#S
+#N
 wbd_imem_stb_o
 wbd_imem_we_o 
 wbd_imem_adr_o.* 
-wbd_imem_sel_o 
+wbd_imem_sel_o.* 
 wbd_imem_dat_o.* 
 wbd_imem_dat_i.*
 wbd_imem_ack_i
 wbd_imem_err_i
 
 wbd_dmem_stb_o
-wbd_dmem_adr_o.*
 wbd_dmem_we_o
-wbd_dmem_sel_o
+wbd_dmem_adr_o.*
+wbd_dmem_sel_o.*
 wbd_dmem_dat_o.*
 wbd_dmem_dat_i.*
 wbd_dmem_ack_i
diff --git a/openlane/user_project_wrapper/base.sdc b/openlane/user_project_wrapper/base.sdc
new file mode 100644
index 0000000..97e8ab3
--- /dev/null
+++ b/openlane/user_project_wrapper/base.sdc
@@ -0,0 +1,56 @@
+set_units -time ns
+set ::env(WB_CLOCK_PERIOD) "10"
+set ::env(WB_CLOCK_PORT)   "wb_clk_i"
+
+set ::env(SDRAM_CLOCK_PERIOD) "20"
+set ::env(SDRAM_CLOCK_PORT)   "digital_core.u_glbl_cfg.sdram_clk"
+
+set ::env(PAD_SDRAM_CLOCK_PERIOD) "20"
+set ::env(PAD_SDRAM_CLOCK_PORT)   "digital_core.u_sdram_ctrl.sdram_pad_clk"
+
+set ::env(CPU_CLOCK_PERIOD) "50"
+set ::env(CPU_CLOCK_PORT)   "digital_core.u_glbl_cfg.cpu_clk"
+
+set ::env(RTC_CLOCK_PERIOD) "50"
+set ::env(RTC_CLOCK_PORT)   "digital_core.u_glbl_cfg.rtc_clk"
+######################################
+# WB Clock domain input output
+######################################
+create_clock [get_ports $::env(WB_CLOCK_PORT)]  -name $::env(WB_CLOCK_PORT)  -period $::env(WB_CLOCK_PERIOD)
+set wb_input_delay_value [expr $::env(WB_CLOCK_PERIOD) * 0.6]
+set wb_output_delay_value [expr $::env(WB_CLOCK_PERIOD) * 0.6]
+puts "\[INFO\]: Setting wb output delay to:$wb_output_delay_value"
+puts "\[INFO\]: Setting wb input delay to: $wb_input_delay_value"
+
+
+set_input_delay 2.0 -clock [get_clocks $::env(WB_CLOCK_PORT)] {wb_rst_i}
+
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbs_stb_i*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbs_cyc_i*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbs_we_i*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbs_sel_i*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbs_dat_i*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbs_adr_i*]
+set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wb_cti_i*]
+
+set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbs_dat_o*]
+set_output_delay 3.0                     -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbs_ack_o*]
+
+######################################
+# SDRAM Clock domain input output
+######################################
+create_clock [get_pins (SDRAM_CLOCK_PORT)]  -name $::env(SDRAM_CLOCK_PORT)  -period $::env(SDRAM_CLOCK_PERIOD)
+create_clock [get_pins (PAD_SDRAM_CLOCK_PORT)]  -name $::env(PAD_SDRAM_CLOCK_PORT)  -period $::env(PAD_SDRAM_CLOCK_PERIOD)
+create_clock [get_pins (CPU_CLOCK_PORT)] -name $::env(CPU_CLOCK_PORT)  -period $::env(CPU_CLOCK_PERIOD)
+create_clock [get_pins (RTC_CLOCK_PORT)] -name $::env(RTC_CLOCK_PORT)  -period $::env(RTC_CLOCK_PERIOD)
+
+set_clock_groups -name async_clock -asynchronous -comment "Async Clock group" -group [get_clocks $::env(WB_CLOCK_PORT)] -group [get_clocks $::env(SDRAM_CLOCK_PORT)] -group [get_clocks $::env(CPU_CLOCK_PORT)] -group [get_clocks $::env(RTC_CLOCK_PORT)]
+
+
+
+# TODO set this as parameter
+set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
+set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load  $cap_load [all_outputs]
+
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 330cf57..04ea174 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -20,6 +20,9 @@
 source $script_dir/../../caravel/openlane/user_project_wrapper_empty/fixed_wrapper_cfgs.tcl
 
 set ::env(DESIGN_NAME) user_project_wrapper
+set verilog_root $script_dir/../../verilog/
+set lef_root $script_dir/../../lef/
+set gds_root $script_dir/../../gds/
 #section end
 
 # User Configurations
@@ -27,43 +30,75 @@
 ## Source Verilog Files
 set ::env(VERILOG_FILES) "\
 	$script_dir/../../caravel/verilog/rtl/defines.v \
+        $script_dir/../../verilog/rtl/digital_core/src/digital_core.sv \
 	$script_dir/../../verilog/rtl/user_project_wrapper.v"
 
 ## Clock configurations
-set ::env(CLOCK_PORT) "user_clock2"
-set ::env(CLOCK_NET) "mprj.clk"
+set ::env(CLOCK_PORT) "user_clock2 wb_clk_i"
+#set ::env(CLOCK_NET) "mprj.clk"
 
 set ::env(CLOCK_PERIOD) "10"
 
 ## Internal Macros
 ### Macro Placement
-set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro.cfg
+set ::env(FP_SIZING) "absolute"
+set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg
+
+set ::env(SDC_FILE) "$script_dir/base.sdc"
+set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
+
 
 ### Black-box verilog and views
 set ::env(VERILOG_FILES_BLACKBOX) "\
-	$script_dir/../../caravel/verilog/rtl/defines.v \
-	$script_dir/../../verilog/rtl/user_proj_example.v"
+        $script_dir/../../verilog/rtl/spi_master/src/spim_top.sv \
+        $script_dir/../../verilog/rtl/wb_interconnect/src/wb_interconnect.sv  \
+        $script_dir/../../verilog/rtl/digital_core/src/glbl_cfg.sv     \
+	$script_dir/macro/bb/sdram.v \
+	$script_dir/macro/bb/syntacore.v \
+	"
 
 set ::env(EXTRA_LEFS) "\
-	$script_dir/../../lef/user_proj_example.lef"
+	$lef_root/spi_master.lef \
+	$lef_root/glbl_cfg.lef \
+	$lef_root/wb_interconnect.lef \
+	$lef_root/sdram.lef \
+	$lef_root/syntacore.lef \
+	"
 
 set ::env(EXTRA_GDS_FILES) "\
-	$script_dir/../../gds/user_proj_example.gds"
+	$gds_root/spi_master.gds \
+	$gds_root/glbl_cfg.gds \
+	$gds_root/wb_interconnect.gds \
+	$gds_root/sdram.gds \
+	$gds_root/syntacore.gds \
+	"
+
+set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
+
+set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/syntacore/scr1/src/includes $script_dir/../../verilog/rtl/sdram_ctrl/src/defs ]
 
 set ::env(GLB_RT_MAXLAYER) 5
 
 set ::env(FP_PDN_CHECK_NODES) 0
 
 # The following is because there are no std cells in the example wrapper project.
-set ::env(SYNTH_TOP_LEVEL) 1
-set ::env(PL_RANDOM_GLB_PLACEMENT) 1
+#set ::env(SYNTH_TOP_LEVEL) 1
+set ::env(PL_BASIC_PLACEMENT) 1
 
 set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
 set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
 set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 0
 set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0
 
-set ::env(DIODE_INSERTION_STRATEGY) 0
-set ::env(FILL_INSERTION) 0
-set ::env(TAP_DECAP_INSERTION) 0
-set ::env(CLOCK_TREE_SYNTH) 0
+set ::env(DIODE_INSERTION_STRATEGY) 4
+set ::env(FILL_INSERTION) 1
+set ::env(TAP_DECAP_INSERTION) 1
+#set ::env(CLOCK_TREE_SYNTH) 1
+
+# Important for large macro placement
+set ::env(PL_DIAMOND_SEARCH_HEIGHT) "400"
+set ::env(ROUTING_OPT_ITERS) "20"
+
+set ::env(GLB_RT_OBS) "met5 0.0 0.0 2920.0 3520.0"
+
+
diff --git a/openlane/user_project_wrapper/macro/bb/sdram.v b/openlane/user_project_wrapper/macro/bb/sdram.v
new file mode 100644
index 0000000..2beba06
--- /dev/null
+++ b/openlane/user_project_wrapper/macro/bb/sdram.v
@@ -0,0 +1,84 @@
+module sdrc_top (cfg_sdr_en,
+    sdr_cas_n,
+    sdr_cke,
+    sdr_cs_n,
+    sdr_den_n,
+    sdr_dqm,
+    sdr_init_done,
+    sdr_ras_n,
+    sdr_we_n,
+    sdram_clk,
+    sdram_pad_clk,
+    sdram_resetn,
+    wb_ack_o,
+    wb_clk_i,
+    wb_cyc_i,
+    wb_rst_i,
+    wb_stb_i,
+    wb_we_i,
+    VPWR,
+    VGND,
+    cfg_colbits,
+    cfg_req_depth,
+    cfg_sdr_cas,
+    cfg_sdr_mode_reg,
+    cfg_sdr_rfmax,
+    cfg_sdr_rfsh,
+    cfg_sdr_tras_d,
+    cfg_sdr_trcar_d,
+    cfg_sdr_trcd_d,
+    cfg_sdr_trp_d,
+    cfg_sdr_twr_d,
+    cfg_sdr_width,
+    pad_sdr_din,
+    sdr_addr,
+    sdr_ba,
+    sdr_dout,
+    wb_addr_i,
+    wb_cti_i,
+    wb_dat_i,
+    wb_dat_o,
+    wb_sel_i);
+ input cfg_sdr_en;
+ output sdr_cas_n;
+ output sdr_cke;
+ output sdr_cs_n;
+ output sdr_den_n;
+ output sdr_dqm;
+ output sdr_init_done;
+ output sdr_ras_n;
+ output sdr_we_n;
+ input sdram_clk;
+ input sdram_pad_clk;
+ input sdram_resetn;
+ output wb_ack_o;
+ input wb_clk_i;
+ input wb_cyc_i;
+ input wb_rst_i;
+ input wb_stb_i;
+ input wb_we_i;
+ input VPWR;
+ input VGND;
+ input [1:0] cfg_colbits;
+ input [1:0] cfg_req_depth;
+ input [2:0] cfg_sdr_cas;
+ input [12:0] cfg_sdr_mode_reg;
+ input [2:0] cfg_sdr_rfmax;
+ input [11:0] cfg_sdr_rfsh;
+ input [3:0] cfg_sdr_tras_d;
+ input [3:0] cfg_sdr_trcar_d;
+ input [3:0] cfg_sdr_trcd_d;
+ input [3:0] cfg_sdr_trp_d;
+ input [3:0] cfg_sdr_twr_d;
+ input [1:0] cfg_sdr_width;
+ input [7:0] pad_sdr_din;
+ output [12:0] sdr_addr;
+ output [1:0] sdr_ba;
+ output [7:0] sdr_dout;
+ input [31:0] wb_addr_i;
+ input [2:0] wb_cti_i;
+ input [31:0] wb_dat_i;
+ output [31:0] wb_dat_o;
+ input [3:0] wb_sel_i;
+
+endmodule
diff --git a/openlane/user_project_wrapper/macro/bb/syntacore.v b/openlane/user_project_wrapper/macro/bb/syntacore.v
new file mode 100644
index 0000000..4e1c7db
--- /dev/null
+++ b/openlane/user_project_wrapper/macro/bb/syntacore.v
@@ -0,0 +1,62 @@
+module scr1_top_wb (core_clk,
+    cpu_rst_n,
+    pwrup_rst_n,
+    rst_n,
+    rtc_clk,
+    soft_irq,
+    test_mode,
+    test_rst_n,
+    wb_clk,
+    wb_rst_n,
+    wbd_dmem_ack_i,
+    wbd_dmem_err_i,
+    wbd_dmem_stb_o,
+    wbd_dmem_we_o,
+    wbd_imem_ack_i,
+    wbd_imem_err_i,
+    wbd_imem_stb_o,
+    wbd_imem_we_o,
+    VPWR,
+    VGND,
+    fuse_mhartid,
+    irq_lines,
+    wbd_dmem_adr_o,
+    wbd_dmem_dat_i,
+    wbd_dmem_dat_o,
+    wbd_dmem_sel_o,
+    wbd_imem_adr_o,
+    wbd_imem_dat_i,
+    wbd_imem_dat_o,
+    wbd_imem_sel_o);
+ input core_clk;
+ input cpu_rst_n;
+ input pwrup_rst_n;
+ input rst_n;
+ input rtc_clk;
+ input soft_irq;
+ input test_mode;
+ input test_rst_n;
+ input wb_clk;
+ input wb_rst_n;
+ input wbd_dmem_ack_i;
+ input wbd_dmem_err_i;
+ output wbd_dmem_stb_o;
+ output wbd_dmem_we_o;
+ input wbd_imem_ack_i;
+ input wbd_imem_err_i;
+ output wbd_imem_stb_o;
+ output wbd_imem_we_o;
+ input VPWR;
+ input VGND;
+ input [31:0] fuse_mhartid;
+ input [15:0] irq_lines;
+ output [31:0] wbd_dmem_adr_o;
+ input [31:0] wbd_dmem_dat_i;
+ output [31:0] wbd_dmem_dat_o;
+ output [3:0] wbd_dmem_sel_o;
+ output [31:0] wbd_imem_adr_o;
+ input [31:0] wbd_imem_dat_i;
+ output [31:0] wbd_imem_dat_o;
+ output [3:0] wbd_imem_sel_o;
+
+endmodule
diff --git a/openlane/user_project_wrapper/macro_placement.cfg b/openlane/user_project_wrapper/macro_placement.cfg
new file mode 100644
index 0000000..bc62704
--- /dev/null
+++ b/openlane/user_project_wrapper/macro_placement.cfg
@@ -0,0 +1,5 @@
+u_core.u_riscv_top	       300	       300	       N
+u_core.u_intercon              300             1800            N
+u_core.u_spi_master            300             2500            N
+u_core.u_sdram_ctrl            1000            2500            N
+u_core.u_glbl_cfg              2000            2500            N
diff --git a/openlane/user_project_wrapper/pin_order.cfg b/openlane/user_project_wrapper/pin_order.cfg
index 267d91c..90cde69 100644
--- a/openlane/user_project_wrapper/pin_order.cfg
+++ b/openlane/user_project_wrapper/pin_order.cfg
@@ -1 +1,156 @@
-../../caravel/openlane/user_project_wrapper_empty/pin_order.cfg
\ No newline at end of file
+#BUS_SORT
+#NR
+analog_io\[8\]
+io_in\[15\]
+io_out\[15\]
+io_oeb\[15\]
+analog_io\[9\]
+io_in\[16\]
+io_out\[16\]
+io_oeb\[16\]
+analog_io\[10\]
+io_in\[17\]
+io_out\[17\]
+io_oeb\[17\]
+analog_io\[11\]
+io_in\[18\]
+io_out\[18\]
+io_oeb\[18\]
+analog_io\[12\]
+io_in\[19\]
+io_out\[19\]
+io_oeb\[19\]
+analog_io\[13\]
+io_in\[20\]
+io_out\[20\]
+io_oeb\[20\]
+analog_io\[14\]
+io_in\[21\]
+io_out\[21\]
+io_oeb\[21\]
+analog_io\[15\]
+io_in\[22\]
+io_out\[22\]
+io_oeb\[22\]
+analog_io\[16\]
+io_in\[23\]
+io_out\[23\]
+io_oeb\[23\]
+
+#S
+wb_.*
+wbs_.*
+la_.*
+user_clock2
+user_irq.*
+
+#E
+io_in\[0\]
+io_out\[0\]
+io_oeb\[0\]
+io_in\[1\]
+io_out\[1\]
+io_oeb\[1\]
+io_in\[2\]
+io_out\[2\]
+io_oeb\[2\]
+io_in\[3\]
+io_out\[3\]
+io_oeb\[3\]
+io_in\[4\]
+io_out\[4\]
+io_oeb\[4\]
+io_in\[5\]
+io_out\[5\]
+io_oeb\[5\]
+io_in\[6\]
+io_out\[6\]
+io_oeb\[6\]
+analog_io\[0\]
+io_in\[7\]
+io_out\[7\]
+io_oeb\[7\]
+analog_io\[1\]
+io_in\[8\]
+io_out\[8\]
+io_oeb\[8\]
+analog_io\[2\]
+io_in\[9\]
+io_out\[9\]
+io_oeb\[9\]
+analog_io\[3\]
+io_in\[10\]
+io_out\[10\]
+io_oeb\[10\]
+analog_io\[4\]
+io_in\[11\]
+io_out\[11\]
+io_oeb\[11\]
+analog_io\[5\]
+io_in\[12\]
+io_out\[12\]
+io_oeb\[12\]
+analog_io\[6\]
+io_in\[13\]
+io_out\[13\]
+io_oeb\[13\]
+analog_io\[7\]
+io_in\[14\]
+io_out\[14\]
+io_oeb\[14\]
+
+#WR
+analog_io\[17\]
+io_in\[24\]
+io_out\[24\]
+io_oeb\[24\]
+analog_io\[18\]
+io_in\[25\]
+io_out\[25\]
+io_oeb\[25\]
+analog_io\[19\]
+io_in\[26\]
+io_out\[26\]
+io_oeb\[26\]
+analog_io\[20\]
+io_in\[27\]
+io_out\[27\]
+io_oeb\[27\]
+analog_io\[21\]
+io_in\[28\]
+io_out\[28\]
+io_oeb\[28\]
+analog_io\[22\]
+io_in\[29\]
+io_out\[29\]
+io_oeb\[29\]
+analog_io\[23\]
+io_in\[30\]
+io_out\[30\]
+io_oeb\[30\]
+analog_io\[24\]
+io_in\[31\]
+io_out\[31\]
+io_oeb\[31\]
+analog_io\[25\]
+io_in\[32\]
+io_out\[32\]
+io_oeb\[32\]
+analog_io\[26\]
+io_in\[33\]
+io_out\[33\]
+io_oeb\[33\]
+analog_io\[27\]
+io_in\[34\]
+io_out\[34\]
+io_oeb\[34\]
+analog_io\[28\]
+io_in\[35\]
+io_out\[35\]
+io_oeb\[35\]
+io_in\[36\]
+io_out\[36\]
+io_oeb\[36\]
+io_in\[37\]
+io_out\[37\]
+io_oeb\[37\]
diff --git a/openlane/wb_interconnect/base.sdc b/openlane/wb_interconnect/base.sdc
new file mode 100644
index 0000000..1ef8a54
--- /dev/null
+++ b/openlane/wb_interconnect/base.sdc
@@ -0,0 +1,27 @@
+set_units -time ns
+set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PORT) "clk_i"
+
+create_clock [get_ports $::env(CLOCK_PORT)]  -name $::env(CLOCK_PORT)  -period $::env(CLOCK_PERIOD)
+
+set input_delay_value [expr $::env(CLOCK_PERIOD) * 0.6]
+set output_delay_value [expr $::env(CLOCK_PERIOD) * 0.6]
+puts "\[INFO\]: Setting output delay to: $output_delay_value"
+puts "\[INFO\]: Setting input delay to: $input_delay_value"
+
+
+set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
+set rst_indx [lsearch [all_inputs] [get_port rst_n]]
+set all_inputs_wo_clk_rst [lreplace [all_inputs] $clk_indx $rst_indx]
+
+
+# correct resetn
+set_input_delay $input_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
+set_input_delay 2.0 -clock [get_clocks $::env(CLOCK_PORT)] {rst_n}
+set_output_delay $output_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
+
+# TODO set this as parameter
+set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
+set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load  $cap_load [all_outputs]
diff --git a/openlane/wb_interconnect/config.tcl b/openlane/wb_interconnect/config.tcl
new file mode 100755
index 0000000..3cbb6cb
--- /dev/null
+++ b/openlane/wb_interconnect/config.tcl
@@ -0,0 +1,65 @@
+# Global
+# ------
+
+set script_dir [file dirname [file normalize [info script]]]
+# Name
+set ::env(DESIGN_NAME) wb_interconnect
+
+#set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+
+# Timing configuration
+set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PORT) "clk_i"
+
+set ::env(SYNTH_MAX_FANOUT) 4
+
+# Sources
+# -------
+
+# Local sources + no2usb sources
+set ::env(VERILOG_FILES) "\
+        $script_dir/../../verilog/rtl/lib/wb_stagging.sv                \
+        $script_dir/../../verilog/rtl/wb_interconnect/src/wb_arb.sv     \
+        $script_dir/../../verilog/rtl/wb_interconnect/src/wb_interconnect.sv  \
+	"
+
+set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/syntacore/scr1/src/includes $script_dir/../../verilog/rtl/sdram_ctrl/src/defs ]
+
+set ::env(SDC_FILE) "$script_dir/base.sdc"
+set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
+
+
+
+# Floorplanning
+# -------------
+
+#set ::env(PL_BASIC_PLACEMENT) 1
+#set ::env(FP_DEF_TEMPLATE) $script_dir/floorplan.def
+set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 2400 150"
+
+
+
+set ::env(FP_PDN_VPITCH) 50
+set ::env(PDN_CFG) $script_dir/pdn.tcl
+
+set ::env(FP_VERTICAL_HALO) 6
+set ::env(PL_TARGET_DENSITY) 0.32
+set ::env(PL_TARGET_DENSITY_CELLS) 0.2
+set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 1
+set ::env(CELL_PAD) 4
+
+set ::env(GLB_RT_ADJUSTMENT) 0
+set ::env(GLB_RT_L2_ADJUSTMENT) 0.2
+set ::env(GLB_RT_L3_ADJUSTMENT) 0.25
+set ::env(GLB_RT_L4_ADJUSTMENT) 0.2
+set ::env(GLB_RT_L5_ADJUSTMENT) 0.1
+set ::env(GLB_RT_L6_ADJUSTMENT) 0.1
+set ::env(GLB_RT_TILES) 14
+set ::env(GLB_RT_MAXLAYER) 5
+
+set ::env(DIODE_INSERTION_STRATEGY) 4
+
+
diff --git a/openlane/wb_interconnect/pdn.tcl b/openlane/wb_interconnect/pdn.tcl
new file mode 100644
index 0000000..1fe689b
--- /dev/null
+++ b/openlane/wb_interconnect/pdn.tcl
@@ -0,0 +1,49 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# Power nets
+set ::power_nets $::env(VDD_PIN)
+set ::ground_nets $::env(GND_PIN)
+
+set ::macro_blockage_layer_list "li1 met1 met2 met3 met4 met5"
+
+pdngen::specify_grid stdcell {
+    name grid
+    rails {
+	    met1 {width 0.48 pitch $::env(PLACE_SITE_HEIGHT) offset 0}
+    }
+    straps {
+	    met4 {width 1.6 pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)}
+	    met5 {width 1.6 pitch $::env(FP_PDN_HPITCH) offset $::env(FP_PDN_HOFFSET)}
+    }
+    connect {{met1 met4} {met4 met5}}
+}
+
+pdngen::specify_grid macro {
+    power_pins "VPWR"
+    ground_pins "VGND"
+    blockages "li1 met1 met2 met3 met4"
+    straps { 
+    } 
+    connect {{met4_PIN_ver met5}}
+}
+
+set ::halo 5
+
+# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
+set ::rails_start_with "POWER" ;
+
+# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
+set ::stripes_start_with "POWER" ;
diff --git a/openlane/wb_interconnect/pin_order.cfg b/openlane/wb_interconnect/pin_order.cfg
new file mode 100644
index 0000000..ffc604a
--- /dev/null
+++ b/openlane/wb_interconnect/pin_order.cfg
@@ -0,0 +1,69 @@
+#BUS_SORT
+
+#E
+clk_i
+rst_n
+
+
+#S
+m0_wbd_stb_i
+m0_wbd_we_i
+m0_wbd_adr_i.*
+m0_wbd_sel_i.*
+m0_wbd_dat_i.*
+m0_wbd_dat_o.*
+m0_wbd_ack_o
+m0_wbd_err_o
+m0_wbd_cyc_i
+
+m1_wbd_stb_i
+m1_wbd_we_i
+m1_wbd_adr_i.*
+m1_wbd_sel_i.*
+m1_wbd_dat_i.*
+m1_wbd_dat_o.*
+m1_wbd_ack_o
+m1_wbd_err_o
+m1_wbd_cyc_i
+
+m2_wbd_stb_i
+m2_wbd_we_i
+m2_wbd_adr_i.*
+m2_wbd_sel_i.*
+m2_wbd_dat_i.*
+m2_wbd_dat_o.*
+m2_wbd_ack_o
+m2_wbd_err_o
+m2_wbd_cyc_i
+
+#N
+s0_wbd_stb_o
+s0_wbd_we_o
+s0_wbd_adr_o.*
+s0_wbd_sel_o.*
+s0_wbd_dat_o.*
+s0_wbd_dat_i.*
+s0_wbd_ack_i
+s0_wbd_err_i
+s0_wbd_cyc_o
+
+s1_wbd_stb_o
+s1_wbd_we_o
+s1_wbd_adr_o.*
+s1_wbd_sel_o.*
+s1_wbd_dat_o.*
+s1_wbd_dat_i.*
+s1_wbd_ack_i
+s1_wbd_err_i
+s1_wbd_cyc_o
+
+s2_wbd_stb_o
+s2_wbd_we_o
+s2_wbd_adr_o.*
+s2_wbd_sel_o.*
+s2_wbd_dat_o.*
+s2_wbd_dat_i.*
+s2_wbd_ack_i
+s2_wbd_err_i
+s2_wbd_cyc_o
+
diff --git a/openlane/yifive/config.tcl b/openlane/yifive/config.tcl
index 4ea25c6..31de106 100644
--- a/openlane/yifive/config.tcl
+++ b/openlane/yifive/config.tcl
@@ -15,27 +15,88 @@
 
 set script_dir [file dirname [file normalize [info script]]]
 
-set ::env(DESIGN_NAME) user_proj_example
+set ::env(DESIGN_NAME) digital_core
+
+set verilog_root $script_dir/../../verilog/
+set lef_root $script_dir/../../lef/
+set gds_root $script_dir/../../gds/
+
 
 set ::env(VERILOG_FILES) "\
-	$script_dir/../../caravel/verilog/rtl/defines.v \
-	$script_dir/../../verilog/rtl/user_proj_example.v"
+        $script_dir/../../verilog/rtl/digital_core/src/digital_core.sv \
+	"
+set ::env(SYNTH_READ_BLACKBOX_LIB) "1"
+set ::env(CLOCK_PORT) "wb_clk_i"
+set ::env(CLOCK_PERIOD) "50"
+set ::env(SYNTH_STRATEGY) "AREA 0"
+set ::env(SYNTH_MAX_FANOUT) 4
 
-set ::env(CLOCK_PORT) ""
-set ::env(CLOCK_NET) "counter.clk"
-set ::env(CLOCK_PERIOD) "10"
-
-set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 900 600"
-set ::env(DESIGN_IS_CORE) 0
-
-set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
-set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}]
-
-set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
+set ::env(FP_PDN_VPITCH) 50
+set ::env(PDN_CFG) $script_dir/pdn.tcl
 
 set ::env(PL_BASIC_PLACEMENT) 1
-set ::env(PL_TARGET_DENSITY) 0.05
 
-# If you're going to use multiple power domains, then keep this disabled.
-set ::env(RUN_CVC) 0
+set ::env(FP_VERTICAL_HALO) 6
+set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
+
+
+set ::env(DESIGN_IS_CORE) "0"
+
+
+
+set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
+
+set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/syntacore/scr1/src/includes $script_dir/../../verilog/rtl/sdram_ctrl/src/defs ]
+
+set ::env(EXTRA_LEFS) "\
+	$lef_root/spi_master.lef \
+	$lef_root/glbl_cfg.lef \
+	$lef_root/wb_interconnect.lef \
+	$lef_root/sdram.lef \
+	$lef_root/syntacore.lef \
+	"
+
+set ::env(EXTRA_GDS_FILES) "\
+	$gds_root/spi_master.gds \
+	$gds_root/glbl_cfg.gds \
+	$gds_root/wb_interconnect.gds \
+	$gds_root/sdram.gds \
+	$gds_root/syntacore.gds \
+        "
+
+set ::env(VERILOG_FILES_BLACKBOX) "\
+        $script_dir/../../verilog/rtl/spi_master/src/spim_top.sv \
+        $script_dir/../../verilog/rtl/wb_interconnect/src/wb_interconnect.sv  \
+        $script_dir/../../verilog/rtl/digital_core/src/glbl_cfg.sv     \
+	$script_dir/macro/bb/sdram.v \
+	$script_dir/macro/bb/syntacore.v \
+	"
+
+
+set ::env(FP_SIZING) relative
+set ::env(DIE_AREA) "0 0 3000 3000"
+
+
+
+set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg
+set ::env(PL_BASIC_PLACEMENT) 1
+set ::env(PL_TARGET_DENSITY) 0.20
+set ::env(PL_TARGET_DENSITY_CELLS) 0.20
+set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 0
+set ::env(CELL_PAD) 4
+
+set ::env(GLB_RT_ADJUSTMENT) 0
+set ::env(GLB_RT_L2_ADJUSTMENT) 0.2
+set ::env(GLB_RT_L3_ADJUSTMENT) 0.25
+set ::env(GLB_RT_L4_ADJUSTMENT) 0.2
+set ::env(GLB_RT_L5_ADJUSTMENT) 0.1
+set ::env(GLB_RT_L6_ADJUSTMENT) 0.1
+set ::env(GLB_RT_TILES) 14
+set ::env(GLB_RT_MAXLAYER) 4
+set ::env(PL_DIAMOND_SEARCH_HEIGHT) "400"
+
+set ::env(DIODE_INSERTION_STRATEGY) 4
+
+
+
+
diff --git a/openlane/yifive/macro/bb/sdram.v b/openlane/yifive/macro/bb/sdram.v
new file mode 100644
index 0000000..2beba06
--- /dev/null
+++ b/openlane/yifive/macro/bb/sdram.v
@@ -0,0 +1,84 @@
+module sdrc_top (cfg_sdr_en,
+    sdr_cas_n,
+    sdr_cke,
+    sdr_cs_n,
+    sdr_den_n,
+    sdr_dqm,
+    sdr_init_done,
+    sdr_ras_n,
+    sdr_we_n,
+    sdram_clk,
+    sdram_pad_clk,
+    sdram_resetn,
+    wb_ack_o,
+    wb_clk_i,
+    wb_cyc_i,
+    wb_rst_i,
+    wb_stb_i,
+    wb_we_i,
+    VPWR,
+    VGND,
+    cfg_colbits,
+    cfg_req_depth,
+    cfg_sdr_cas,
+    cfg_sdr_mode_reg,
+    cfg_sdr_rfmax,
+    cfg_sdr_rfsh,
+    cfg_sdr_tras_d,
+    cfg_sdr_trcar_d,
+    cfg_sdr_trcd_d,
+    cfg_sdr_trp_d,
+    cfg_sdr_twr_d,
+    cfg_sdr_width,
+    pad_sdr_din,
+    sdr_addr,
+    sdr_ba,
+    sdr_dout,
+    wb_addr_i,
+    wb_cti_i,
+    wb_dat_i,
+    wb_dat_o,
+    wb_sel_i);
+ input cfg_sdr_en;
+ output sdr_cas_n;
+ output sdr_cke;
+ output sdr_cs_n;
+ output sdr_den_n;
+ output sdr_dqm;
+ output sdr_init_done;
+ output sdr_ras_n;
+ output sdr_we_n;
+ input sdram_clk;
+ input sdram_pad_clk;
+ input sdram_resetn;
+ output wb_ack_o;
+ input wb_clk_i;
+ input wb_cyc_i;
+ input wb_rst_i;
+ input wb_stb_i;
+ input wb_we_i;
+ input VPWR;
+ input VGND;
+ input [1:0] cfg_colbits;
+ input [1:0] cfg_req_depth;
+ input [2:0] cfg_sdr_cas;
+ input [12:0] cfg_sdr_mode_reg;
+ input [2:0] cfg_sdr_rfmax;
+ input [11:0] cfg_sdr_rfsh;
+ input [3:0] cfg_sdr_tras_d;
+ input [3:0] cfg_sdr_trcar_d;
+ input [3:0] cfg_sdr_trcd_d;
+ input [3:0] cfg_sdr_trp_d;
+ input [3:0] cfg_sdr_twr_d;
+ input [1:0] cfg_sdr_width;
+ input [7:0] pad_sdr_din;
+ output [12:0] sdr_addr;
+ output [1:0] sdr_ba;
+ output [7:0] sdr_dout;
+ input [31:0] wb_addr_i;
+ input [2:0] wb_cti_i;
+ input [31:0] wb_dat_i;
+ output [31:0] wb_dat_o;
+ input [3:0] wb_sel_i;
+
+endmodule
diff --git a/openlane/yifive/macro/bb/syntacore.v b/openlane/yifive/macro/bb/syntacore.v
new file mode 100644
index 0000000..1eb131f
--- /dev/null
+++ b/openlane/yifive/macro/bb/syntacore.v
@@ -0,0 +1,58 @@
+module scr1_top_wb (clk,
+    cpu_rst_n,
+    pwrup_rst_n,
+    rst_n,
+    rtc_clk,
+    soft_irq,
+    test_mode,
+    test_rst_n,
+    wbd_dmem_ack_i,
+    wbd_dmem_err_i,
+    wbd_dmem_stb_o,
+    wbd_dmem_we_o,
+    wbd_imem_ack_i,
+    wbd_imem_err_i,
+    wbd_imem_stb_o,
+    wbd_imem_we_o,
+    VPWR,
+    VGND,
+    fuse_mhartid,
+    irq_lines,
+    wbd_dmem_adr_o,
+    wbd_dmem_dat_i,
+    wbd_dmem_dat_o,
+    wbd_dmem_sel_o,
+    wbd_imem_adr_o,
+    wbd_imem_dat_i,
+    wbd_imem_dat_o,
+    wbd_imem_sel_o);
+ input clk;
+ input cpu_rst_n;
+ input pwrup_rst_n;
+ input rst_n;
+ input rtc_clk;
+ input soft_irq;
+ input test_mode;
+ input test_rst_n;
+ input wbd_dmem_ack_i;
+ input wbd_dmem_err_i;
+ output wbd_dmem_stb_o;
+ output wbd_dmem_we_o;
+ input wbd_imem_ack_i;
+ input wbd_imem_err_i;
+ output wbd_imem_stb_o;
+ output wbd_imem_we_o;
+ input VPWR;
+ input VGND;
+ input [31:0] fuse_mhartid;
+ input [15:0] irq_lines;
+ output [31:0] wbd_dmem_adr_o;
+ input [31:0] wbd_dmem_dat_i;
+ output [31:0] wbd_dmem_dat_o;
+ output [3:0] wbd_dmem_sel_o;
+ output [31:0] wbd_imem_adr_o;
+ input [31:0] wbd_imem_dat_i;
+ output [31:0] wbd_imem_dat_o;
+ output [3:0] wbd_imem_sel_o;
+
+endmodule
diff --git a/openlane/yifive/macro_placement.cfg b/openlane/yifive/macro_placement.cfg
new file mode 100644
index 0000000..7b2d9a8
--- /dev/null
+++ b/openlane/yifive/macro_placement.cfg
@@ -0,0 +1,5 @@
+u_riscv_top		300		1200		N
+u_intercon              300             900             N
+u_sdram_ctrl            1100            300             N
+u_glbl_cfg              2300            300             N
+u_spi_master            200             200             N
diff --git a/openlane/yifive/pdn.tcl b/openlane/yifive/pdn.tcl
new file mode 100644
index 0000000..19314bf
--- /dev/null
+++ b/openlane/yifive/pdn.tcl
@@ -0,0 +1,49 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# Power nets
+set ::power_nets $::env(VDD_PIN)
+set ::ground_nets $::env(GND_PIN)
+
+set ::macro_blockage_layer_list "li1 met1 met2 met3 met4 met5"
+
+pdngen::specify_grid stdcell {
+    name grid
+    rails {
+	    met1 {width 0.48 pitch $::env(PLACE_SITE_HEIGHT) offset 0}
+    }
+    straps {
+	    met4 {width 1.6 pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)}
+	    met5 {width 1.6 pitch $::env(FP_PDN_HPITCH) offset $::env(FP_PDN_HOFFSET)}
+    }
+    connect {{met1 met4} {met4 met5}}
+}
+
+pdngen::specify_grid macro {
+    power_pins "VPWR"
+    ground_pins "VGND"
+    blockages "li1 met1 met2 met3 met4"
+    straps { 
+    } 
+    connect {{met4_PIN_ver met5}}
+}
+
+set ::halo 4
+
+# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
+set ::rails_start_with "POWER" ;
+
+# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
+set ::stripes_start_with "POWER" ;
diff --git a/openlane/yifive/pin_order.cfg b/openlane/yifive/pin_order.cfg
index 8128f78..925c4df 100644
--- a/openlane/yifive/pin_order.cfg
+++ b/openlane/yifive/pin_order.cfg
@@ -1,9 +1,128 @@
 #BUS_SORT
+#NR
+io_in\[15\]
+io_out\[15\]
+io_oeb\[15\]
+io_in\[16\]
+io_out\[16\]
+io_oeb\[16\]
+io_in\[17\]
+io_out\[17\]
+io_oeb\[17\]
+io_in\[18\]
+io_out\[18\]
+io_oeb\[18\]
+io_in\[19\]
+io_out\[19\]
+io_oeb\[19\]
+io_in\[20\]
+io_out\[20\]
+io_oeb\[20\]
+io_in\[21\]
+io_out\[21\]
+io_oeb\[21\]
+io_in\[22\]
+io_out\[22\]
+io_oeb\[22\]
+io_in\[23\]
+io_out\[23\]
+io_oeb\[23\]
 
 #S
-wb_.*
-wbs_.*
-la_.*
 
-#N
-io_.*
+wb_.*
+wbd_.*
+la_.*
+rtc_clk
+user_irq.*
+
+#E
+io_in\[0\]
+io_out\[0\]
+io_oeb\[0\]
+io_in\[1\]
+io_out\[1\]
+io_oeb\[1\]
+io_in\[2\]
+io_out\[2\]
+io_oeb\[2\]
+io_in\[3\]
+io_out\[3\]
+io_oeb\[3\]
+io_in\[4\]
+io_out\[4\]
+io_oeb\[4\]
+io_in\[5\]
+io_out\[5\]
+io_oeb\[5\]
+io_in\[6\]
+io_out\[6\]
+io_oeb\[6\]
+io_in\[7\]
+io_out\[7\]
+io_oeb\[7\]
+io_in\[8\]
+io_out\[8\]
+io_oeb\[8\]
+io_in\[9\]
+io_out\[9\]
+io_oeb\[9\]
+io_in\[10\]
+io_out\[10\]
+io_oeb\[10\]
+io_in\[11\]
+io_out\[11\]
+io_oeb\[11\]
+io_in\[12\]
+io_out\[12\]
+io_oeb\[12\]
+io_in\[13\]
+io_out\[13\]
+io_oeb\[13\]
+io_in\[14\]
+io_out\[14\]
+io_oeb\[14\]
+
+#WR
+io_in\[24\]
+io_out\[24\]
+io_oeb\[24\]
+io_in\[25\]
+io_out\[25\]
+io_oeb\[25\]
+io_in\[26\]
+io_out\[26\]
+io_oeb\[26\]
+io_in\[27\]
+io_out\[27\]
+io_oeb\[27\]
+io_in\[28\]
+io_out\[28\]
+io_oeb\[28\]
+io_in\[29\]
+io_out\[29\]
+io_oeb\[29\]
+io_in\[30\]
+io_out\[30\]
+io_oeb\[30\]
+io_in\[31\]
+io_out\[31\]
+io_oeb\[31\]
+io_in\[32\]
+io_out\[32\]
+io_oeb\[32\]
+io_in\[33\]
+io_out\[33\]
+io_oeb\[33\]
+io_in\[34\]
+io_out\[34\]
+io_oeb\[34\]
+io_in\[35\]
+io_out\[35\]
+io_oeb\[35\]
+io_in\[36\]
+io_out\[36\]
+io_oeb\[36\]
+io_in\[37\]
+io_out\[37\]
+io_oeb\[37\]
diff --git a/read.me b/read.me
deleted file mode 100644
index 50e0e30..0000000
--- a/read.me
+++ /dev/null
@@ -1,6 +0,0 @@
-
-# To run the sim for wishbone register access
-make verify-wb_port
-
-#To run the sim for Risc Hello 
-make verify-risc_hello
diff --git a/signoff/glbl_cfg/OPENLANE_VERSION b/signoff/glbl_cfg/OPENLANE_VERSION
new file mode 100644
index 0000000..a2633b1
--- /dev/null
+++ b/signoff/glbl_cfg/OPENLANE_VERSION
@@ -0,0 +1 @@
+openlane rc7
diff --git a/signoff/glbl_cfg/PDK_SOURCES b/signoff/glbl_cfg/PDK_SOURCES
new file mode 100644
index 0000000..8b58bd5
--- /dev/null
+++ b/signoff/glbl_cfg/PDK_SOURCES
@@ -0,0 +1,6 @@
+-ne openlane 
+a68c95289612a361870acedb7f6478fcfae32e49
+-ne skywater-pdk 
+f6f76f3dc99526c6fc2cfede19b5b1227d4ebde7
+-ne open_pdks 
+522a373441a865fee9d6e3783015b4445f11afe6
diff --git a/signoff/glbl_cfg/final_summary_report.csv b/signoff/glbl_cfg/final_summary_report.csv
new file mode 100644
index 0000000..c2ec988
--- /dev/null
+++ b/signoff/glbl_cfg/final_summary_report.csv
@@ -0,0 +1,2 @@
+,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
+0,/project/openlane/glbl_cfg,glbl_cfg,glbl_cfg,Flow_completed,0h5m29s,0h4m0s,58333.33333333334,0.09,29166.66666666667,48,595.32,2625,0,0,0,0,0,0,0,9,0,0,0,112279,21278,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,81244573,0.0,28.2,24.76,3.22,-1,-1,2478,2670,463,655,0,0,0,2625,1,0,3,1,468,0,0,560,577,533,10,212,1078,10,1300,100.0,10.0,10,AREA 0,5,50,1,80,10.8,0.9,0,sky130_fd_sc_hd,0,3
diff --git a/signoff/sdram/final_summary_report.csv b/signoff/sdram/final_summary_report.csv
index b86c95b..3fff53d 100644
--- a/signoff/sdram/final_summary_report.csv
+++ b/signoff/sdram/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/sdram,sdrc_top,sdram,Flow_completed,0h8m25s,0h4m36s,43346.66666666667,0.3,21673.333333333336,30,612.11,6502,0,0,0,0,0,0,0,50,0,0,0,373862,49373,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,320796393,0.0,41.88,12.09,12.26,0.0,0.0,6477,6647,1150,1320,0,0,0,6502,131,107,82,107,352,213,29,2197,1190,1123,28,204,3638,0,3842,100.0,10.0,10,AREA 0,5,50,1,153.6,153.18,0.4,0,sky130_fd_sc_hd,4,0
+0,/project/openlane/sdram,sdrc_top,sdram,Flow_completed,0h7m32s,0h4m3s,43333.333333333336,0.3,21666.666666666668,30,603.28,6500,0,0,0,0,0,0,0,43,0,0,0,362096,48694,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,313618208,0.0,40.99,11.75,11.06,0.0,-1,6475,6645,1150,1320,0,0,0,6500,130,107,82,102,354,211,31,2197,1190,1123,28,204,3638,0,3842,100.0,10.0,10,AREA 0,5,50,1,153.6,153.18,0.4,0,sky130_fd_sc_hd,4,0
diff --git a/signoff/spi_master/OPENLANE_VERSION b/signoff/spi_master/OPENLANE_VERSION
new file mode 100644
index 0000000..a2633b1
--- /dev/null
+++ b/signoff/spi_master/OPENLANE_VERSION
@@ -0,0 +1 @@
+openlane rc7
diff --git a/signoff/spi_master/PDK_SOURCES b/signoff/spi_master/PDK_SOURCES
new file mode 100644
index 0000000..8b58bd5
--- /dev/null
+++ b/signoff/spi_master/PDK_SOURCES
@@ -0,0 +1,6 @@
+-ne openlane 
+a68c95289612a361870acedb7f6478fcfae32e49
+-ne skywater-pdk 
+f6f76f3dc99526c6fc2cfede19b5b1227d4ebde7
+-ne open_pdks 
+522a373441a865fee9d6e3783015b4445f11afe6
diff --git a/signoff/spi_master/final_summary_report.csv b/signoff/spi_master/final_summary_report.csv
new file mode 100644
index 0000000..7325d8c
--- /dev/null
+++ b/signoff/spi_master/final_summary_report.csv
@@ -0,0 +1,2 @@
+,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
+0,/project/openlane/spi_master,spim_top,spi_master,Flow_completed,0h7m4s,0h4m20s,19293.333333333336,0.3,9646.666666666668,15,567.92,2894,0,0,0,0,0,0,1,5,1,0,0,150790,24828,-1.25,-1.25,-1.79,-1.79,-2.3,-107.03,-107.03,-394.49,-394.49,-544.26,121832965,0.0,12.02,8.74,0.89,0.0,-1,2872,2970,449,547,0,0,0,2894,85,0,95,81,1125,90,20,923,529,465,27,358,3708,13,4079,81.30081300813008,12.3,10,AREA 0,5,50,1,153.6,153.18,0.4,0,sky130_fd_sc_hd,0,3
diff --git a/signoff/syntacore/final_summary_report.csv b/signoff/syntacore/final_summary_report.csv
index eb76ee8..c99599e 100644
--- a/signoff/syntacore/final_summary_report.csv
+++ b/signoff/syntacore/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/syntacore,scr1_top_wb,syntacore,Flow_completed,4h25m58s,0h24m27s,14261.866666666665,3.75,7130.9333333333325,9,1835.44,26741,0,0,0,0,0,0,0,386,0,0,0,2348462,220538,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,2088019437,0.0,20.65,8.72,3.4,0.0,0.0,26627,26865,2336,2574,0,0,0,26741,509,0,694,1902,3881,2196,1040,6600,2386,2349,98,1086,48226,0,49312,20.0,50.0,50,AREA 0,5,50,1,153.6,153.18,0.2,0,sky130_fd_sc_hd,4,0
+0,/project/openlane/syntacore,scr1_top_wb,syntacore,Flow_completed,1h35m28s,0h27m5s,29668.888888888887,1.8,14834.444444444443,20,1125.28,26702,0,0,0,0,0,0,0,69,0,0,0,1591280,222490,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,1348931410,0.0,19.87,15.65,3.42,0.14,-1,26588,26826,2335,2573,0,0,0,26702,508,0,693,1900,3881,2188,1037,6599,2386,2349,100,866,22835,255,23956,20.0,50.0,50,AREA 0,5,50,1,153.6,153.18,0.4,0,sky130_fd_sc_hd,4,3
diff --git a/signoff/user_project_wrapper/OPENLANE_VERSION b/signoff/user_project_wrapper/OPENLANE_VERSION
new file mode 100644
index 0000000..a2633b1
--- /dev/null
+++ b/signoff/user_project_wrapper/OPENLANE_VERSION
@@ -0,0 +1 @@
+openlane rc7
diff --git a/signoff/user_project_wrapper/PDK_SOURCES b/signoff/user_project_wrapper/PDK_SOURCES
new file mode 100644
index 0000000..8b58bd5
--- /dev/null
+++ b/signoff/user_project_wrapper/PDK_SOURCES
@@ -0,0 +1,6 @@
+-ne openlane 
+a68c95289612a361870acedb7f6478fcfae32e49
+-ne skywater-pdk 
+f6f76f3dc99526c6fc2cfede19b5b1227d4ebde7
+-ne open_pdks 
+522a373441a865fee9d6e3783015b4445f11afe6
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
new file mode 100644
index 0000000..5246de2
--- /dev/null
+++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -0,0 +1,2 @@
+,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,Flow_completed,0h34m28s,0h2m12s,37.943648816936495,10.2784,18.971824408468247,0,585.11,195,0,0,0,0,0,0,74835,13,226,-1,2,898598,4357,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,895585866,0.0,1.19,1.92,1.26,2.19,-1,684,1302,676,1294,0,0,0,195,0,0,0,0,0,0,0,0,2,2,1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,180,180,0.55,0,sky130_fd_sc_hd,4,0
diff --git a/signoff/wb_interconnect/OPENLANE_VERSION b/signoff/wb_interconnect/OPENLANE_VERSION
new file mode 100644
index 0000000..a2633b1
--- /dev/null
+++ b/signoff/wb_interconnect/OPENLANE_VERSION
@@ -0,0 +1 @@
+openlane rc7
diff --git a/signoff/wb_interconnect/PDK_SOURCES b/signoff/wb_interconnect/PDK_SOURCES
new file mode 100644
index 0000000..8b58bd5
--- /dev/null
+++ b/signoff/wb_interconnect/PDK_SOURCES
@@ -0,0 +1,6 @@
+-ne openlane 
+a68c95289612a361870acedb7f6478fcfae32e49
+-ne skywater-pdk 
+f6f76f3dc99526c6fc2cfede19b5b1227d4ebde7
+-ne open_pdks 
+522a373441a865fee9d6e3783015b4445f11afe6
diff --git a/signoff/wb_interconnect/final_summary_report.csv b/signoff/wb_interconnect/final_summary_report.csv
new file mode 100644
index 0000000..7b324d7
--- /dev/null
+++ b/signoff/wb_interconnect/final_summary_report.csv
@@ -0,0 +1,2 @@
+,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
+0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,Flow_completed,0h5m21s,0h3m7s,7321.739130434781,0.23,3660.8695652173906,4,510.27,842,0,0,0,0,0,0,0,14,0,0,0,399186,10637,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,371301320,0.0,48.62,5.88,23.46,-1,-1,583,1159,59,635,0,0,0,842,146,0,3,75,33,0,0,107,318,318,14,64,2750,195,3009,100.0,10.0,10,AREA 0,5,50,1,80,10.8,0.9,0,sky130_fd_sc_hd,0,3
diff --git a/verilog/dv/risc_boot/risc_boot.c b/verilog/dv/risc_boot/risc_boot.c
index d042822..f0d8010 100644
--- a/verilog/dv/risc_boot/risc_boot.c
+++ b/verilog/dv/risc_boot/risc_boot.c
@@ -170,7 +170,6 @@
 
     // Add some delay for user core to boot
     for(i = 0; i < 40; i ++);
-    for(i = 0; i < 40; i ++);
 
     if(reg_mprj_globl_reg6  != 0x11223344) bFail = 1;
     if(reg_mprj_globl_reg7  != 0x22334455) bFail = 1;
diff --git a/verilog/dv/risc_boot/risc_boot.hex b/verilog/dv/risc_boot/risc_boot.hex
new file mode 100755
index 0000000..3a5d43e
--- /dev/null
+++ b/verilog/dv/risc_boot/risc_boot.hex
@@ -0,0 +1,125 @@
+@00000000
+93 00 00 00 93 01 00 00 13 02 00 00 93 02 00 00 
+13 03 00 00 93 03 00 00 13 04 00 00 93 04 00 00 
+13 05 00 00 93 05 00 00 13 06 00 00 93 06 00 00 
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+13 09 00 00 93 09 00 00 13 0A 00 00 93 0A 00 00 
+13 0B 00 00 93 0B 00 00 13 0C 00 00 93 0C 00 00 
+13 0D 00 00 93 0D 00 00 13 0E 00 00 93 0E 00 00 
+13 0F 00 00 93 0F 00 00 17 05 00 00 13 05 05 74 
+93 05 00 00 13 06 00 00 63 D8 C5 00 14 41 94 C1 
+11 05 91 05 E3 CC C5 FE 13 05 00 00 93 05 80 00 
+63 57 B5 00 23 20 05 00 11 05 E3 4D B5 FE 11 22 
+01 A0 01 00 B7 02 00 28 13 03 00 12 23 90 62 00 
+A3 81 02 00 05 C6 21 4F 93 73 F6 0F 93 DE 73 00 
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+00 10 AA 87 A3 07 F4 FE 03 47 F4 FE A9 47 63 14 
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+B7 07 00 26 98 43 85 47 E3 0C F7 FE B7 07 00 25 
+13 87 87 02 FD 57 1C C3 37 07 00 25 61 07 1C C3 
+B7 07 00 26 B1 07 37 07 60 AB 98 C3 B7 07 00 26 
+93 87 87 0B 09 67 13 07 07 C0 98 C3 B7 07 00 26 
+93 87 47 0B 09 67 13 07 07 C0 98 C3 B7 07 00 26 
+93 87 07 0B 09 67 13 07 07 C0 98 C3 B7 07 00 26 
+93 87 C7 0A 09 67 13 07 07 C0 98 C3 B7 07 00 26 
+93 87 87 0A 09 67 13 07 07 C0 98 C3 B7 07 00 26 
+93 87 47 0A 09 67 13 07 07 C0 98 C3 B7 07 00 26 
+93 87 07 0A 09 67 13 07 07 C0 98 C3 B7 07 00 26 
+93 87 C7 09 09 67 13 07 07 C0 98 C3 B7 07 00 26 
+93 87 87 09 09 67 13 07 07 C0 98 C3 B7 07 00 26 
+93 87 47 09 09 67 13 07 07 C0 98 C3 B7 07 00 26 
+93 87 07 09 09 67 13 07 07 C0 98 C3 B7 07 00 26 
+93 87 C7 08 09 67 13 07 07 C0 98 C3 B7 07 00 26 
+93 87 87 08 09 67 13 07 07 C0 98 C3 B7 07 00 26 
+93 87 47 08 09 67 13 07 07 C0 98 C3 B7 07 00 26 
+93 87 07 08 09 67 13 07 07 C0 98 C3 B7 07 00 26 
+93 87 C7 07 09 67 13 07 07 C0 98 C3 B7 07 00 26 
+93 87 87 07 09 67 13 07 07 C0 98 C3 B7 07 00 26 
+93 87 47 07 09 67 13 07 07 C0 98 C3 B7 07 00 26 
+93 87 07 07 09 67 13 07 07 C0 98 C3 B7 07 00 26 
+93 87 C7 06 09 67 13 07 07 C0 98 C3 B7 07 00 26 
+93 87 87 06 09 67 13 07 07 C0 98 C3 B7 07 00 26 
+93 87 47 06 09 67 13 07 07 C0 98 C3 B7 07 00 26 
+93 87 07 06 09 67 13 07 07 C0 98 C3 B7 07 00 26 
+93 87 C7 05 09 67 13 07 07 C0 98 C3 B7 07 00 26 
+93 87 87 05 09 67 13 07 07 C0 98 C3 B7 07 00 26 
+93 87 47 05 09 67 13 07 07 C0 98 C3 B7 07 00 26 
+93 87 07 05 09 67 13 07 07 C0 98 C3 B7 07 00 26 
+93 87 C7 04 09 67 13 07 07 C0 98 C3 B7 07 00 26 
+93 87 87 04 09 67 13 07 07 C0 98 C3 B7 07 00 26 
+93 87 47 04 09 67 13 07 07 C0 98 C3 B7 07 00 26 
+93 87 07 04 09 67 13 07 07 C0 98 C3 B7 07 00 26 
+93 87 C7 03 09 67 13 07 07 C0 98 C3 B7 07 00 26 
+93 87 87 03 09 67 13 07 07 C0 98 C3 B7 07 00 26 
+93 87 47 03 09 67 13 07 07 C0 98 C3 B7 07 00 26 
+93 87 07 03 09 67 13 07 07 C0 98 C3 B7 07 00 26 
+93 87 C7 02 09 67 13 07 07 C0 98 C3 B7 07 00 26 
+93 87 87 02 09 67 13 07 07 C0 98 C3 B7 07 00 26 
+93 87 47 02 09 67 13 07 07 C0 98 C3 B7 07 00 26 
+05 47 98 C3 01 00 B7 07 00 26 98 43 85 47 E3 0C 
+F7 FE B7 07 00 30 D1 07 37 07 00 01 13 07 E7 19 
+98 C3 B7 07 00 30 C1 07 37 27 17 2F 13 07 27 24 
+98 C3 B7 07 00 30 1D 47 98 C3 23 20 00 00 39 A0 
+83 27 00 00 13 87 17 00 23 20 E0 00 03 27 00 00 
+93 07 70 02 E3 D6 E7 FE 23 20 00 00 39 A0 83 27 
+00 00 13 87 17 00 23 20 E0 00 03 27 00 00 93 07 
+70 02 E3 D6 E7 FE B7 07 00 30 E1 07 98 43 B7 37 
+22 11 93 87 47 34 63 05 F7 00 85 47 23 26 F4 FE 
+B7 07 00 30 F1 07 98 43 B7 47 33 22 93 87 57 45 
+63 05 F7 00 85 47 23 26 F4 FE B7 07 00 30 93 87 
+07 02 98 43 B7 57 44 33 93 87 67 56 63 05 F7 00 
+85 47 23 26 F4 FE B7 07 00 30 93 87 47 02 98 43 
+B7 67 55 44 93 87 77 67 63 05 F7 00 85 47 23 26 
+F4 FE B7 07 00 30 93 87 87 02 98 43 B7 77 66 55 
+93 87 87 78 63 05 F7 00 85 47 23 26 F4 FE B7 07 
+00 30 93 87 C7 02 98 43 B7 97 77 66 93 87 97 89 
+63 05 F7 00 85 47 23 26 F4 FE 83 27 C4 FE 81 EB 
+B7 07 00 26 B1 07 37 07 61 AB 98 C3 39 A0 B7 07 
+00 26 B1 07 37 07 60 AB 98 C3 B7 07 00 26 93 87 
+07 0A 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 
+C7 09 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 
+87 09 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 
+47 09 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 
+07 09 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 
+C7 08 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 
+87 08 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 
+47 08 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 
+07 08 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 
+C7 07 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 
+87 07 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 
+47 07 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 
+07 07 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 
+C7 06 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 
+87 06 09 67 13 07 97 80 98 C3 B7 07 00 26 93 87 
+47 06 09 67 13 07 97 80 98 C3 B7 07 00 26 05 47 
+98 C3 01 00 B7 07 00 26 98 43 85 47 E3 0C F7 FE 
+01 00 72 44 05 61 82 80 
diff --git a/verilog/dv/risc_boot/risc_boot_tb.v b/verilog/dv/risc_boot/risc_boot_tb.v
index 80c7d98..fe5a499 100644
--- a/verilog/dv/risc_boot/risc_boot_tb.v
+++ b/verilog/dv/risc_boot/risc_boot_tb.v
@@ -91,7 +91,7 @@
            $dumpfile("simx.vcd");
            $dumpvars(1,risc_boot_tb);
            //$dumpvars(2,risc_boot_tb.uut);
-           $dumpvars(1,risc_boot_tb.uut.mprj.u_core);
+           $dumpvars(4,risc_boot_tb.uut.mprj.u_core);
            //$dumpvars(0,risc_boot_tb.u_user_spiflash);
 	   $display("Waveform Dump started");
         end
@@ -100,7 +100,7 @@
 	initial begin
 
 		// Repeat cycles of 1000 clock edges as needed to complete testbench
-		repeat (600) begin
+		repeat (200) begin
 			repeat (1000) @(posedge clock);
 			// $display("+1000 cycles");
 		end
diff --git a/verilog/dv/risc_boot/run_iverilog b/verilog/dv/risc_boot/run_iverilog
index 0cafcde..65f8bd5 100755
--- a/verilog/dv/risc_boot/run_iverilog
+++ b/verilog/dv/risc_boot/run_iverilog
@@ -1,6 +1,6 @@
 
 #add -DWFDUMP to enable waveform dump
-iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $PDK_PATH \
+iverilog -DWFDUMP -g2005-sv -DFUNCTIONAL -DSIM -I $PDK_PATH \
 -I $CARAVEL_ROOT/verilog/dv/caravel -I $CARAVEL_ROOT/verilog/rtl \
 -I ../model    -I ../../../verilog/rtl \
 -I ../../../verilog/rtl/syntacore/scr1/src/includes    -I ../../../verilog/rtl/sdram_ctrl/src/defs \
diff --git a/verilog/dv/risc_boot/user_risc_boot.hex b/verilog/dv/risc_boot/user_risc_boot.hex
index 1fdd96c..5ab43fa 100755
--- a/verilog/dv/risc_boot/user_risc_boot.hex
+++ b/verilog/dv/risc_boot/user_risc_boot.hex
@@ -38,20 +38,20 @@
 93 08 00 00 13 09 00 00 93 09 00 00 13 0A 00 00
 93 0A 00 00 13 0B 00 00 93 0B 00 00 13 0C 00 00
 93 0C 00 00 13 0D 00 00 93 0D 00 00 13 0E 00 00
-93 0E 00 00 13 0F 00 00 93 0F 00 00 97 01 48 00
-93 81 41 62 13 05 00 40 97 05 48 00 93 85 85 D7
-17 06 48 00 13 06 06 E3 63 0D B5 00 29 A0 14 41
-94 C1 11 05 91 05 E3 9C C5 FE 17 06 48 00 13 06
-66 E1 97 05 48 00 93 85 E5 E0 21 A0 23 20 06 00
-11 06 E3 9D C5 FE 17 01 49 00 13 01 A1 D3 17 05
-48 00 13 05 25 DF 17 06 48 00 13 06 A6 DE B3 05
-A6 40 17 07 49 00 13 07 E7 91 33 02 B7 40 92 85
-17 06 48 00 13 06 06 DD 29 A0 14 41 94 C1 11 05
+93 0E 00 00 13 0F 00 00 93 0F 00 00 97 01 00 20
+93 81 41 62 13 05 00 40 97 05 00 20 93 85 85 D7
+17 06 00 20 13 06 06 E3 63 0D B5 00 29 A0 14 41
+94 C1 11 05 91 05 E3 9C C5 FE 17 06 00 20 13 06
+66 E1 97 05 00 20 93 85 E5 E0 21 A0 23 20 06 00
+11 06 E3 9D C5 FE 17 01 01 20 13 01 A1 D3 17 05
+00 20 13 05 25 DF 17 06 00 20 13 06 A6 DE B3 05
+A6 40 17 07 01 20 13 07 E7 91 33 02 B7 40 92 85
+17 06 00 20 13 06 06 DD 29 A0 14 41 94 C1 11 05
 91 05 E3 1C C5 FE 21 A0 23 A0 05 00 91 05 E3 9D
 E5 FE B7 02 49 00 05 43 23 A0 62 00 B7 02 49 00
 91 02 13 03 30 06 23 A0 62 00 B7 02 49 00 C1 02
 7D 53 23 A0 62 00 23 A2 62 00 01 45 81 45 97 02
-48 00 E7 80 22 CC 97 02 48 00 93 82 A2 D1 6D 71
+00 20 E7 80 22 CC 97 02 00 20 93 82 A2 D1 6D 71
 06 C2 0A C4 0E C6 12 C8 16 CA 1A CC 1E CE 22 D0
 26 D2 2A D4 2E D6 32 D8 36 DA 3A DC 3E DE C2 C0
 C6 C2 CA C4 CE C6 D2 C8 D6 CA DA CC DE CE E2 D0
@@ -70,7 +70,7 @@
 66 55 D4 D3 93 08 88 78 37 9E 77 66 23 A4 17 03
 93 0E 9E 89 23 A6 D7 03 01 A0 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-97 02 B8 FF 93 82 42 09 82 82 13 00 00 00 13 00
+97 02 00 E0 93 82 42 09 82 82 13 00 00 00 13 00
 00 00 13 00 00 00 13 00 00 00 13 00 00 00 01 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/verilog/dv/user_risc_boot/uprj_netlists.v b/verilog/dv/user_risc_boot/uprj_netlists.v
index 45af4a9..fe938c1 100644
--- a/verilog/dv/user_risc_boot/uprj_netlists.v
+++ b/verilog/dv/user_risc_boot/uprj_netlists.v
@@ -38,6 +38,7 @@
      `include "digital_core/src/glbl_cfg.sv"
      `include "digital_core/src/digital_core.sv"
 
+     `include "lib/wb_stagging.sv"
      `include "wb_interconnect/src/wb_arb.sv"
      `include "wb_interconnect/src/wb_interconnect.sv"
 
diff --git a/verilog/dv/user_risc_boot/user_risc_boot.hex b/verilog/dv/user_risc_boot/user_risc_boot.hex
index 1fdd96c..5ab43fa 100755
--- a/verilog/dv/user_risc_boot/user_risc_boot.hex
+++ b/verilog/dv/user_risc_boot/user_risc_boot.hex
@@ -38,20 +38,20 @@
 93 08 00 00 13 09 00 00 93 09 00 00 13 0A 00 00
 93 0A 00 00 13 0B 00 00 93 0B 00 00 13 0C 00 00
 93 0C 00 00 13 0D 00 00 93 0D 00 00 13 0E 00 00
-93 0E 00 00 13 0F 00 00 93 0F 00 00 97 01 48 00
-93 81 41 62 13 05 00 40 97 05 48 00 93 85 85 D7
-17 06 48 00 13 06 06 E3 63 0D B5 00 29 A0 14 41
-94 C1 11 05 91 05 E3 9C C5 FE 17 06 48 00 13 06
-66 E1 97 05 48 00 93 85 E5 E0 21 A0 23 20 06 00
-11 06 E3 9D C5 FE 17 01 49 00 13 01 A1 D3 17 05
-48 00 13 05 25 DF 17 06 48 00 13 06 A6 DE B3 05
-A6 40 17 07 49 00 13 07 E7 91 33 02 B7 40 92 85
-17 06 48 00 13 06 06 DD 29 A0 14 41 94 C1 11 05
+93 0E 00 00 13 0F 00 00 93 0F 00 00 97 01 00 20
+93 81 41 62 13 05 00 40 97 05 00 20 93 85 85 D7
+17 06 00 20 13 06 06 E3 63 0D B5 00 29 A0 14 41
+94 C1 11 05 91 05 E3 9C C5 FE 17 06 00 20 13 06
+66 E1 97 05 00 20 93 85 E5 E0 21 A0 23 20 06 00
+11 06 E3 9D C5 FE 17 01 01 20 13 01 A1 D3 17 05
+00 20 13 05 25 DF 17 06 00 20 13 06 A6 DE B3 05
+A6 40 17 07 01 20 13 07 E7 91 33 02 B7 40 92 85
+17 06 00 20 13 06 06 DD 29 A0 14 41 94 C1 11 05
 91 05 E3 1C C5 FE 21 A0 23 A0 05 00 91 05 E3 9D
 E5 FE B7 02 49 00 05 43 23 A0 62 00 B7 02 49 00
 91 02 13 03 30 06 23 A0 62 00 B7 02 49 00 C1 02
 7D 53 23 A0 62 00 23 A2 62 00 01 45 81 45 97 02
-48 00 E7 80 22 CC 97 02 48 00 93 82 A2 D1 6D 71
+00 20 E7 80 22 CC 97 02 00 20 93 82 A2 D1 6D 71
 06 C2 0A C4 0E C6 12 C8 16 CA 1A CC 1E CE 22 D0
 26 D2 2A D4 2E D6 32 D8 36 DA 3A DC 3E DE C2 C0
 C6 C2 CA C4 CE C6 D2 C8 D6 CA DA CC DE CE E2 D0
@@ -70,7 +70,7 @@
 66 55 D4 D3 93 08 88 78 37 9E 77 66 23 A4 17 03
 93 0E 9E 89 23 A6 D7 03 01 A0 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-97 02 B8 FF 93 82 42 09 82 82 13 00 00 00 13 00
+97 02 00 E0 93 82 42 09 82 82 13 00 00 00 13 00
 00 00 13 00 00 00 13 00 00 00 13 00 00 00 01 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/verilog/dv/user_risc_boot/user_risc_boot_tb.v b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
index efab5eb..8009a57 100644
--- a/verilog/dv/user_risc_boot/user_risc_boot_tb.v
+++ b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
@@ -207,9 +207,9 @@
     .vssd1(),	// User area 1 digital ground
     .vssd2(),	// User area 2 digital ground
 `endif
-    .clk             (clock),  // System clock
+    .wb_clk_i        (clock),  // System clock
     .rtc_clk         (1'b1),  // Real-time clock
-    .rst_n           (RSTB),  // Regular Reset signal
+    .wb_rst_i        (RSTB),  // Regular Reset signal
 
     .wbd_ext_cyc_i   (wbd_ext_cyc_i),  // strobe/request
     .wbd_ext_stb_i   (wbd_ext_stb_i),  // strobe/request
@@ -234,7 +234,7 @@
     .io_out         (io_out) ,
     .io_oeb         (io_oeb) ,
 
-    .irq            () 
+    .user_irq       () 
 
 );
 
diff --git a/verilog/rtl/digital_core/src/digital_core.sv b/verilog/rtl/digital_core/src/digital_core.sv
index 44448ff..41fbf83 100644
--- a/verilog/rtl/digital_core/src/digital_core.sv
+++ b/verilog/rtl/digital_core/src/digital_core.sv
@@ -22,6 +22,24 @@
 ////    0.1 - 16th Feb 2021, Dinesh A                             ////
 ////          Initial integration with Risc-V core +              ////
 ////          Wishbone Cross Bar + SPI  Master                    ////
+////    0.2 - 17th June 2021, Dinesh A                            ////
+////        1. In risc core, wishbone and core domain is          ////
+////           created                                            ////
+////        2. cpu and rtc clock are generated in glbl reg block  ////
+////        3. in wishbone interconnect:- Stagging flop are added ////
+////           at interface to break wishbone timing path         ////
+////        4. buswidth warning are fixed inside spi_master       ////
+////        modified rtl files are                                ////
+////           verilog/rtl/digital_core/src/digital_core.sv       ////
+///            verilog/rtl/digital_core/src/glbl_cfg.sv           ////
+///            verilog/rtl/lib/wb_stagging.sv                     ////
+///            verilog/rtl/syntacore/scr1/src/top/scr1_dmem_wb.sv ////
+///            verilog/rtl/syntacore/scr1/src/top/scr1_imem_wb.sv ////
+///            verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv  ////
+///            verilog/rtl/user_project_wrapper.v                 ////
+///            verilog/rtl/wb_interconnect/src/wb_interconnect.sv ////
+///            verilog/rtl/spi_master/src/spim_clkgen.sv          ////
+///            verilog/rtl/spi_master/src/spim_ctrl.sv            ////
 ////                                                              ////
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
@@ -72,9 +90,9 @@
     inout vssd1,	// User area 1 digital ground
     inout vssd2,	// User area 2 digital ground
 `endif
-    input   logic                       clk             ,  // System clock
-    input   logic                       rtc_clk         ,  // Real-time clock
-    input   logic                       rst_n           ,  // Regular Reset signal
+    input   logic                       wb_clk_i        ,  // System clock
+    input   logic                       user_clock2     ,  // user Clock
+    input   logic                       wb_rst_i        ,  // Regular Reset signal
 
     input   logic                       wbd_ext_cyc_i   ,  // strobe/request
     input   logic                       wbd_ext_stb_i   ,  // strobe/request
@@ -98,7 +116,7 @@
     output logic  [37:0]                io_out          ,
     output logic  [37:0]                io_oeb          ,
 
-    output logic  [2:0]                 irq             
+    output logic  [2:0]                 user_irq             
 
 );
 
@@ -161,7 +179,7 @@
 //    Global Register Wishbone Interface
 //---------------------------------------------------------------------
 logic                           wbd_glbl_stb_o; // strobe/request
-logic   [WB_WIDTH-1:0]          wbd_glbl_adr_o; // address
+logic   [7:0]                   wbd_glbl_adr_o; // address
 logic                           wbd_glbl_we_o;  // write
 logic   [WB_WIDTH-1:0]          wbd_glbl_dat_o; // data output
 logic   [3:0]                   wbd_glbl_sel_o; // byte enable
@@ -284,14 +302,16 @@
 assign  io_oeb[37] =  1'b1; // Unused
 
 
+wire wb_rst_n = !wb_rst_i;
+
 
 //------------------------------------------------------------------------------
 // RISC V Core instance
 //------------------------------------------------------------------------------
 scr1_top_wb u_riscv_top (
     // Reset
-    .pwrup_rst_n            (rst_n                     ),
-    .rst_n                  (rst_n                     ),
+    .pwrup_rst_n            (wb_rst_n                  ),
+    .rst_n                  (wb_rst_n                  ),
     .cpu_rst_n              (cpu_rst_n                 ),
 `ifdef SCR1_DBG_EN
     .sys_rst_n_o            (sys_rst_n_o               ),
@@ -299,7 +319,7 @@
 `endif // SCR1_DBG_EN
 
     // Clock
-    .clk                    (clk                       ),
+    .core_clk               (cpu_clk                   ),
     .rtc_clk                (rtc_clk                   ),
 
     // Fuses
@@ -330,6 +350,9 @@
     .tdo_en                 (tdo_en                    ),
 `endif // SCR1_DBG_EN
 
+    
+    .wb_rst_n               (wb_rst_n                  ),
+    .wb_clk                 (wb_clk_i                  ),
     // Instruction memory interface
     .wbd_imem_stb_o         (wbd_riscv_imem_stb_i      ),
     .wbd_imem_adr_o         (wbd_riscv_imem_adr_i      ),
@@ -365,7 +388,7 @@
 `endif
 ) u_spi_master
 (
-    .mclk                   (clk                       ),
+    .mclk                   (wb_clk_i                  ),
     .rst_n                  (spi_rst_n                 ),
 
     .wbd_stb_i              (wbd_spim_stb_o            ),
@@ -397,18 +420,21 @@
 );
 
 
-sdrc_top  #(.APP_AW(WB_WIDTH), 
+sdrc_top  
+    `ifndef SYNTHESIS
+    #(.APP_AW(WB_WIDTH), 
 	    .APP_DW(WB_WIDTH), 
 	    .APP_BW(4),
 	    .SDR_DW(8), 
 	    .SDR_BW(1))
+      `endif
      u_sdram_ctrl (
-    .cfg_sdr_width          (cfg_sdr_width             ),
-    .cfg_colbits            (cfg_colbits               ),
+    .cfg_sdr_width          (cfg_sdr_width              ),
+    .cfg_colbits            (cfg_colbits                ),
                     
     // WB bus
-    .wb_rst_i               (!rst_n                    ),
-    .wb_clk_i               (clk                       ),
+    .wb_rst_i               (wb_rst_i                   ),
+    .wb_clk_i               (wb_clk_i                   ),
     
     .wb_stb_i               (wbd_sdram_stb_o            ),
     .wb_addr_i              (wbd_sdram_adr_o            ),
@@ -453,39 +479,9 @@
    );
 
 
-//------------------------------
-// RISC Data Memory Map
-// 0x0000_0000 to 0x0FFF_FFFF  - SPI FLASH MEMORY
-// 0x1000_0000 to 0x1000_00FF  - SPI REGISTER
-// 0x2000_0000 to 0x2FFF_FFFF  - SDRAM
-// 0x3000_0000 to 0x3000_00FF  - GLOBAL REGISTER
-//-----------------------------
-// 
-wire [3:0] wbd_riscv_imem_tar_id     = (wbd_riscv_imem_adr_i[31:16] == 16'h0000 ) ? 4'b0000 :
-                                       (wbd_riscv_imem_adr_i[31:16] == 16'h0041 ) ? 4'b0000 :
-                                       (wbd_riscv_imem_adr_i[31:16] == 16'h0048 ) ? 4'b0001 :// Todo: Temp fix for SDRAM
-                                       (wbd_riscv_imem_adr_i[31:16] == 16'h3000 ) ? 4'b0010 : 4'b0000;
-
-wire [3:0] wbd_riscv_dmem_tar_id     = (wbd_riscv_dmem_adr_i[31:16] == 16'h0000 ) ? 4'b0000 :
-                                       (wbd_riscv_dmem_adr_i[31:16] == 16'h0041 ) ? 4'b0000 :
-                                       (wbd_riscv_dmem_adr_i[31:16] == 16'h0048 ) ? 4'b0001 : // todo: Temp fix for SDRAM
-                                       (wbd_riscv_dmem_adr_i[31:16] == 16'h3000 ) ? 4'b0010 : 4'b0000;
-
-
-//-------------------------------------------------------------------
-// EXTERNAL MEMORY MAP
-// 0x3000_0000 to 0x3000_00FF -  GLOBAL REGISTER
-// 0x4000_0000 to 0x4FFF_FFFF -  SPI FLASH MEMORY
-// 0x5000_0000 to 0x5000_00FF -  SPI REGISTER
-// 0x6000_0000 to 0x6FFF_FFFF -  SDRAM
-//
-wire [3:0] wbd_ext_tar_id            = (wbd_ext_adr_i[31:28] == 4'b0100 ) ? 4'b0000 :
-                                       (wbd_ext_adr_i[31:28] == 4'b0101 ) ? 4'b0000 :
-                                       (wbd_ext_adr_i[31:28] == 4'b0110 ) ? 4'b0001 :
-                                       (wbd_ext_adr_i[31:28] == 4'b0011 ) ? 4'b0010 : 4'b0000;
 wb_interconnect  u_intercon (
-         .clk_i         (clk), 
-         .rst_n         (rst_n),
+         .clk_i         (wb_clk_i              ), 
+         .rst_n         (wb_rst_n              ),
          
          // Master 0 Interface
          .m0_wbd_dat_i  (wbd_riscv_imem_dat_i  ),
@@ -494,7 +490,6 @@
          .m0_wbd_we_i   (wbd_riscv_imem_we_i   ),
          .m0_wbd_cyc_i  (wbd_riscv_imem_stb_i  ),
          .m0_wbd_stb_i  (wbd_riscv_imem_stb_i  ),
-         .m0_wbd_tid_i  (wbd_riscv_imem_tar_id ), // target id
          .m0_wbd_dat_o  (wbd_riscv_imem_dat_o  ),
          .m0_wbd_ack_o  (wbd_riscv_imem_ack_o  ),
          .m0_wbd_err_o  (wbd_riscv_imem_err_o  ),
@@ -506,7 +501,6 @@
          .m1_wbd_we_i   (wbd_riscv_dmem_we_i   ),
          .m1_wbd_cyc_i  (wbd_riscv_dmem_stb_i  ),
          .m1_wbd_stb_i  (wbd_riscv_dmem_stb_i  ),
-         .m1_wbd_tid_i  (wbd_riscv_dmem_tar_id ), // target id
          .m1_wbd_dat_o  (wbd_riscv_dmem_dat_o  ),
          .m1_wbd_ack_o  (wbd_riscv_dmem_ack_o  ),
          .m1_wbd_err_o  (wbd_riscv_dmem_err_o  ),
@@ -518,7 +512,6 @@
          .m2_wbd_we_i   (wbd_ext_we_i   ),
          .m2_wbd_cyc_i  (wbd_ext_cyc_i  ),
          .m2_wbd_stb_i  (wbd_ext_stb_i  ),
-         .m2_wbd_tid_i  (wbd_ext_tar_id ), // target id
          .m2_wbd_dat_o  (wbd_ext_dat_o  ),
          .m2_wbd_ack_o  (wbd_ext_ack_o  ),
          .m2_wbd_err_o  (wbd_ext_err_o  ),
@@ -560,14 +553,15 @@
 
 glbl_cfg   u_glbl_cfg (
 
-       .mclk                   (clk                       ),
-       .reset_n                (rst_n                     ),
+       .mclk                   (wb_clk_i                  ),
+       .reset_n                (wb_rst_n                  ),
+       .user_clock2            (user_clock2               ),
        .device_idcode          (                          ),
 
         // Reg Bus Interface Signal
        .reg_cs                 (wbd_glbl_stb_o            ),
        .reg_wr                 (wbd_glbl_we_o             ),
-       .reg_addr               (wbd_glbl_adr_o[5:2]       ),
+       .reg_addr               (wbd_glbl_adr_o            ),
        .reg_wdata              (wbd_glbl_dat_o            ),
        .reg_be                 (wbd_glbl_sel_o            ),
 
@@ -578,6 +572,8 @@
        // SDRAM Clock
 
        .sdram_clk              (sdram_clk                 ),
+       .cpu_clk                (cpu_clk                   ),
+       .rtc_clk                (rtc_clk                   ),
 
        // reset
        .cpu_rst_n              (cpu_rst_n                 ),
@@ -588,6 +584,7 @@
        .fuse_mhartid           (fuse_mhartid              ),
        .irq_lines              (irq_lines                 ), 
        .soft_irq               (soft_irq                  ),
+       .user_irq               (user_irq                  ),
 
        // SDRAM Config
        .cfg_sdr_width          (cfg_sdr_width             ),
diff --git a/verilog/rtl/digital_core/src/glbl_cfg.sv b/verilog/rtl/digital_core/src/glbl_cfg.sv
index c44e20c..1754aec 100644
--- a/verilog/rtl/digital_core/src/glbl_cfg.sv
+++ b/verilog/rtl/digital_core/src/glbl_cfg.sv
@@ -48,13 +48,14 @@
 module glbl_cfg (
 
         input logic             mclk,
+        input logic             user_clock2,
         input logic             reset_n,
         output logic [31:0]     device_idcode,
 
         // Reg Bus Interface Signal
         input logic             reg_cs,
         input logic             reg_wr,
-        input logic [3:0]       reg_addr,
+        input logic [7:0]       reg_addr,
         input logic [31:0]      reg_wdata,
         input logic [3:0]       reg_be,
 
@@ -65,6 +66,8 @@
        // SDRAM Clock
 
        output  logic           sdram_clk,
+       output  logic           cpu_clk,
+       output  logic           rtc_clk,
 
        // reset
        output  logic           cpu_rst_n,
@@ -75,6 +78,7 @@
        output logic [31:0]     fuse_mhartid,
        output logic [15:0]     irq_lines,
        output logic            soft_irq,
+       output logic [2:0]      user_irq,
 
        // SDRAM Config
        input logic             sdr_init_done       , // Indicate SDRAM Initialisation Done
@@ -109,7 +113,6 @@
 
 logic           reg_cs_l    ;
 logic           reg_cs_2l    ;
-logic           cfg_sdram_clk_div;
 
 
 logic [31:0]    reg_0;  // Software_Reg_0
@@ -149,7 +152,7 @@
     reg_cs_l      <= '0;
     reg_cs_2l     <= '0;
   end else begin
-    sw_addr       <= reg_addr [3:0];
+    sw_addr       <= reg_addr [5:2];
     sw_rd_en      <= reg_cs & !reg_wr;
     sw_wr_en      <= reg_cs & reg_wr;
     sw_reg_wdata  <= reg_wdata;
@@ -251,12 +254,24 @@
 //   reg-0
 //   -----------------------------------------------------------------
 
-assign cpu_rst_n     = reg_0[0];
-assign spi_rst_n     = reg_0[1];
-assign sdram_rst_n   = reg_0[2];
-assign cfg_sdram_clk_div = reg_0[3];
+assign cpu_rst_n               = reg_0[0];
+assign spi_rst_n               = reg_0[1];
+assign sdram_rst_n             = reg_0[2];
 
+// SDRAM Clock source & div selection
+wire       cfg_sdram_clk_src_sel   = reg_0[4];
+wire       cfg_sdram_clk_div       = reg_0[5];
+wire [1:0] cfg_sdram_clk_ratio     = reg_0[7:6];
 
+// Core Clock source & div selection
+wire       cfg_cpu_clk_src_sel   = reg_0[8];
+wire       cfg_cpu_clk_div       = reg_0[9];
+wire [1:0] cfg_cpu_clk_ratio     = reg_0[11:10];
+
+// RTC Clock source & div selection
+wire       cfg_rtc_clk_src_sel   = reg_0[12];
+wire       cfg_rtc_clk_div       = reg_0[13];
+wire [1:0] cfg_rtc_clk_ratio     = reg_0[15:14];
 
 generic_register #(8,0  ) u_reg0_be0 (
 	      .we            ({8{sw_wr_en_0 & 
@@ -404,6 +419,7 @@
 //-----------------------------------------------------------------
 assign  irq_lines     = reg_3[15:0]; 
 assign  soft_irq      = reg_3[16]; 
+assign  user_irq      = reg_3[19:17]; 
 
 generic_register #(8,0  ) u_reg3_be0 (
 	      .we            ({8{sw_wr_en_3 & 
@@ -426,18 +442,18 @@
 	      //List of Outs
 	      .data_out      (reg_3[15:8]        )
           );
-generic_register #(1,0  ) u_reg3_be2 (
-	      .we            ({1{sw_wr_en_3 & 
+generic_register #(4,0  ) u_reg3_be2 (
+	      .we            ({4{sw_wr_en_3 & 
                                  wr_be[2]   }}  ),		 
-	      .data_in       (sw_reg_wdata[16]    ),
+	      .data_in       (sw_reg_wdata[19:16]    ),
 	      .reset_n       (reset_n           ),
 	      .clk           (mclk              ),
 	      
 	      //List of Outs
-	      .data_out      (reg_3[16]        )
+	      .data_out      (reg_3[19:16]        )
           );
 
-assign reg_3[31:17] = '0;
+assign reg_3[31:20] = '0;
 
 
 //-----------------------------------------------------------------------
@@ -1028,29 +1044,72 @@
 	      .clk           (mclk              ),
 	      
 	      //List of Outs
-	      .data_out      (reg_15[31:24]        )
+	      .data_out      (reg_15[31:24]     )
           );
 
 
 
 
 //----------------------------------
-// Generate SDRAM Div-2 Clock
+// Generate SDRAM Clock Generation
 //----------------------------------
-wire   sdram_clk_div2;
+wire   sdram_clk_div;
+wire   sdram_ref_clk;
 
-assign sdram_clk = (cfg_sdram_clk_div) ? sdram_clk_div2 : mclk;
+assign sdram_ref_clk = (cfg_sdram_clk_src_sel) ? user_clock2 : mclk;
+
+
+
+assign sdram_clk = (cfg_sdram_clk_div) ? sdram_clk_div : sdram_ref_clk;
 
 
 clk_ctl #(1) u_sdramclk (
    // Outputs
-       .clk_o         (sdram_clk_div2),
+       .clk_o         (sdram_clk_div      ),
    // Inputs
-       .mclk          (mclk),
-       .reset_n       (reset_n), 
-       .clk_div_ratio (2'b00)
+       .mclk          (sdram_ref_clk      ),
+       .reset_n       (reset_n            ), 
+       .clk_div_ratio (cfg_sdram_clk_ratio)
    );
 
 
+//----------------------------------
+// Generate CORE Clock Generation
+//----------------------------------
+wire   cpu_clk_div;
+wire   cpu_ref_clk;
+
+assign cpu_ref_clk = (cfg_cpu_clk_src_sel) ? user_clock2 : mclk;
+assign cpu_clk     = (cfg_cpu_clk_div)     ? cpu_clk_div : cpu_ref_clk;
+
+
+clk_ctl #(1) u_cpuclk (
+   // Outputs
+       .clk_o         (cpu_clk_div      ),
+   // Inputs
+       .mclk          (cpu_ref_clk      ),
+       .reset_n       (reset_n          ), 
+       .clk_div_ratio (cfg_cpu_clk_ratio)
+   );
+
+//----------------------------------
+// Generate RTC Clock Generation
+//----------------------------------
+wire   rtc_clk_div;
+wire   rtc_ref_clk;
+
+assign rtc_ref_clk = (cfg_rtc_clk_src_sel) ? user_clock2 : mclk;
+assign rtc_clk     = (cfg_rtc_clk_div)     ? rtc_clk_div : rtc_ref_clk;
+
+
+clk_ctl #(1) u_rtcclk (
+   // Outputs
+       .clk_o         (rtc_clk_div      ),
+   // Inputs
+       .mclk          (rtc_ref_clk      ),
+       .reset_n       (reset_n          ), 
+       .clk_div_ratio (cfg_rtc_clk_ratio)
+   );
+
 
 endmodule
diff --git a/verilog/rtl/lib/async_fifo_th.sv b/verilog/rtl/lib/async_fifo_th.sv
new file mode 100755
index 0000000..5ff3df6
--- /dev/null
+++ b/verilog/rtl/lib/async_fifo_th.sv
@@ -0,0 +1,386 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  OMS 8051 cores common library Module                        ////
+////                                                              ////
+////  This file is part of the OMS 8051 cores project             ////
+////  http://www.opencores.org/cores/oms8051mini/                 ////
+////                                                              ////
+////  Description                                                 ////
+////    Async Fifo with threshold tracking/status                 ////
+////                                                              ////
+////  To Do:                                                      ////
+////    nothing                                                   ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Dinesh Annayya, dinesha@opencores.org                 ////
+////                                                              ////
+////  Revision : Nov 26, 2016                                      //// 
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+//-------------------------------------------
+// async_fifo:: async FIFO
+//    Following two ports are newly added
+//        1. At write clock domain:
+//           wr_total_free_space -->  Indicate total free transfer available 
+//        2. At read clock domain:
+//           rd_total_aval       -->  Indicate total no of transfer available
+//-----------------------------------------------
+
+module async_fifo_th (
+	           wr_clk,
+                   wr_reset_n,
+                   wr_en,
+                   wr_data,
+                   full,                 // sync'ed to wr_clk
+                   afull,                 // sync'ed to wr_clk
+                   wr_total_free_space,
+                   rd_clk,
+                   rd_reset_n,
+                   rd_en,
+                   empty,                // sync'ed to rd_clk
+                   aempty,                // sync'ed to rd_clk
+                   rd_total_aval,
+                   rd_data);
+
+   parameter W = 4'd8;
+   parameter DP = 3'd4;
+   parameter WR_FAST = 1'b1;
+   parameter RD_FAST = 1'b1;
+   parameter FULL_DP = DP;
+   parameter EMPTY_DP = 1'b0;
+
+   parameter AW = (DP == 2)   ? 1 : 
+		  (DP == 4)   ? 2 :
+                  (DP == 8)   ? 3 :
+                  (DP == 16)  ? 4 :
+                  (DP == 32)  ? 5 :
+                  (DP == 64)  ? 6 :
+                  (DP == 128) ? 7 :
+                  (DP == 256) ? 8 : 0;
+
+   output [W-1 : 0]  rd_data;
+   input [W-1 : 0]   wr_data;
+   input             wr_clk, wr_reset_n, wr_en, rd_clk, rd_reset_n,
+                     rd_en;
+   output            full, empty;
+   output            afull, aempty; // about full and about to empty
+   output   [AW:0]   wr_total_free_space; // Total Number of free space aval 
+                                               // w.r.t write clk
+                                               // note: Without accounting byte enables
+   output   [AW:0]   rd_total_aval;       // Total Number of words avaialble 
+                                               // w.r.t rd clock, 
+                                              // note: Without accounting byte enables
+   // synopsys translate_off
+
+   initial begin
+      if (AW == 0) begin
+         $display ("%m : ERROR!!! Fifo depth %d not in range 2 to 256", DP);
+      end // if (AW == 0)
+   end // initial begin
+
+   // synopsys translate_on
+   reg [W-1 : 0]    mem[DP-1 : 0];
+
+   /*********************** write side ************************/
+   reg [AW:0] sync_rd_ptr_0, sync_rd_ptr_1; 
+   wire [AW:0] sync_rd_ptr;
+   reg [AW:0] wr_ptr, grey_wr_ptr;
+   reg [AW:0] grey_rd_ptr;
+   reg full_q;
+   wire full_c;
+   wire afull_c;
+   wire [AW:0] wr_ptr_inc = wr_ptr + 1'b1;
+   wire [AW:0] wr_cnt = get_cnt(wr_ptr, sync_rd_ptr);
+
+   assign full_c  = (wr_cnt == FULL_DP) ? 1'b1 : 1'b0;
+   assign afull_c = (wr_cnt == FULL_DP-1) ? 1'b1 : 1'b0;
+
+   //--------------------------
+   // Shows total number of words 
+   // of free space available w.r.t write clock
+   //--------------------------- 
+   assign wr_total_free_space = FULL_DP - wr_cnt;
+
+   always @(posedge wr_clk or negedge wr_reset_n) begin
+	if (!wr_reset_n) begin
+		wr_ptr <= 0;
+		grey_wr_ptr <= 0;
+		full_q <= 0;	
+	end
+	else if (wr_en) begin
+		wr_ptr <= wr_ptr_inc;
+		grey_wr_ptr <= bin2grey(wr_ptr_inc);
+		if (wr_cnt == (FULL_DP-1)) begin
+			full_q <= 1'b1;
+		end
+	end
+	else begin
+	    	if (full_q && (wr_cnt<FULL_DP)) begin
+			full_q <= 1'b0;
+	     	end
+	end
+    end
+
+    assign full  = (WR_FAST == 1) ? full_c : full_q;
+    assign afull = afull_c;
+
+    always @(posedge wr_clk) begin
+	if (wr_en) begin
+		mem[wr_ptr[AW-1:0]] <= wr_data;
+	end
+    end
+
+    wire [AW:0] grey_rd_ptr_dly ;
+    assign #1 grey_rd_ptr_dly = grey_rd_ptr;
+
+    // read pointer synchronizer
+    always @(posedge wr_clk or negedge wr_reset_n) begin
+	if (!wr_reset_n) begin
+		sync_rd_ptr_0 <= 0;
+		sync_rd_ptr_1 <= 0;
+	end
+	else begin
+		sync_rd_ptr_0 <= grey_rd_ptr_dly;		
+		sync_rd_ptr_1 <= sync_rd_ptr_0;
+	end
+    end
+
+    assign sync_rd_ptr = grey2bin(sync_rd_ptr_1);
+
+   /************************ read side *****************************/
+   reg [AW:0] sync_wr_ptr_0, sync_wr_ptr_1; 
+   wire [AW:0] sync_wr_ptr;
+   reg [AW:0] rd_ptr;
+   reg empty_q;
+   wire empty_c;
+   wire aempty_c;
+   wire [AW:0] rd_ptr_inc = rd_ptr + 1'b1;
+   wire [AW:0] sync_wr_ptr_dec = sync_wr_ptr - 1'b1;
+   wire [AW:0] rd_cnt = get_cnt(sync_wr_ptr, rd_ptr);
+ 
+   assign empty_c  = (rd_cnt == 0) ? 1'b1 : 1'b0;
+   assign aempty_c = (rd_cnt == 1) ? 1'b1 : 1'b0;
+   //--------------------------
+   // Shows total number of words 
+   // space available w.r.t write clock
+   //--------------------------- 
+   assign rd_total_aval = rd_cnt;
+
+   always @(posedge rd_clk or negedge rd_reset_n) begin
+	if (!rd_reset_n) begin
+		rd_ptr <= 0;
+		grey_rd_ptr <= 0;
+		empty_q <= 1'b1;
+	end
+	else begin
+		if (rd_en) begin
+			rd_ptr <= rd_ptr_inc;
+			grey_rd_ptr <= bin2grey(rd_ptr_inc);
+			if (rd_cnt==(EMPTY_DP+1)) begin
+				empty_q <= 1'b1;
+			end
+		end
+		else begin
+			if (empty_q && (rd_cnt!=EMPTY_DP)) begin
+				empty_q <= 1'b0;
+			end
+		end
+	end
+    end
+
+    assign empty  = (RD_FAST == 1) ? empty_c : empty_q;
+    assign aempty = aempty_c;
+
+    assign rd_data = mem[rd_ptr[AW-1:0]];
+
+    wire [AW:0] grey_wr_ptr_dly ;
+    assign #1 grey_wr_ptr_dly =  grey_wr_ptr;
+
+    // write pointer synchronizer
+    always @(posedge rd_clk or negedge rd_reset_n) begin
+	if (!rd_reset_n) begin
+		sync_wr_ptr_0 <= 0;
+		sync_wr_ptr_1 <= 0;
+	end
+	else begin
+		sync_wr_ptr_0 <= grey_wr_ptr_dly;		
+		sync_wr_ptr_1 <= sync_wr_ptr_0;
+	end
+    end
+    assign sync_wr_ptr = grey2bin(sync_wr_ptr_1);
+
+	
+/************************ functions ******************************/
+function [AW:0] bin2grey;
+input [AW:0] bin;
+reg [8:0] bin_8;
+reg [8:0] grey_8;
+begin
+	bin_8 = bin;
+	grey_8[1:0] = do_grey(bin_8[2:0]);
+	grey_8[3:2] = do_grey(bin_8[4:2]);
+	grey_8[5:4] = do_grey(bin_8[6:4]);
+	grey_8[7:6] = do_grey(bin_8[8:6]);
+	grey_8[8] = bin_8[8];
+	bin2grey = grey_8;
+end
+endfunction
+
+function [AW:0] grey2bin;
+input [AW:0] grey;
+reg [8:0] grey_8;
+reg [8:0] bin_8;
+begin
+	grey_8 = grey;
+	bin_8[8] = grey_8[8];
+	bin_8[7:6] = do_bin({bin_8[8], grey_8[7:6]});
+	bin_8[5:4] = do_bin({bin_8[6], grey_8[5:4]});
+	bin_8[3:2] = do_bin({bin_8[4], grey_8[3:2]});
+	bin_8[1:0] = do_bin({bin_8[2], grey_8[1:0]});
+	grey2bin = bin_8;
+end
+endfunction
+
+
+function [1:0] do_grey;
+input [2:0] bin;
+begin
+	if (bin[2]) begin  // do reverse grey
+		case (bin[1:0]) 
+			2'b00: do_grey = 2'b10;
+			2'b01: do_grey = 2'b11;
+			2'b10: do_grey = 2'b01;
+			2'b11: do_grey = 2'b00;
+		endcase
+	end
+	else begin
+		case (bin[1:0]) 
+			2'b00: do_grey = 2'b00;
+			2'b01: do_grey = 2'b01;
+			2'b10: do_grey = 2'b11;
+			2'b11: do_grey = 2'b10;
+		endcase
+	end
+end
+endfunction
+
+function [1:0] do_bin;
+input [2:0] grey;
+begin
+	if (grey[2]) begin	// actually bin[2]
+		case (grey[1:0])
+			2'b10: do_bin = 2'b00;
+			2'b11: do_bin = 2'b01;
+			2'b01: do_bin = 2'b10;
+			2'b00: do_bin = 2'b11;
+		endcase
+	end
+	else begin
+		case (grey[1:0])
+			2'b00: do_bin = 2'b00;
+			2'b01: do_bin = 2'b01;
+			2'b11: do_bin = 2'b10;
+			2'b10: do_bin = 2'b11;
+		endcase
+	end
+end
+endfunction
+			
+function [AW:0] get_cnt;
+input [AW:0] wr_ptr, rd_ptr;
+begin
+	if (wr_ptr >= rd_ptr) begin
+		get_cnt = (wr_ptr - rd_ptr);	
+	end
+	else begin
+		get_cnt = DP*2 - (rd_ptr - wr_ptr);
+	end
+end
+endfunction
+
+// synopsys translate_off
+always @(posedge wr_clk) begin
+   if (wr_en && full) begin
+      $display($time, "%m Error! afifo overflow!");
+      $stop;
+   end
+end
+
+always @(posedge rd_clk) begin
+   if (rd_en && empty) begin
+      $display($time, "%m error! afifo underflow!");
+      $stop;
+   end
+end
+
+// gray code monitor
+reg [AW:0] last_gwr_ptr;
+always @(posedge wr_clk or negedge wr_reset_n) begin
+   if (!wr_reset_n) begin
+      last_gwr_ptr <= #1 0;
+   end
+   else if (last_gwr_ptr !== grey_wr_ptr) begin
+      check_ptr_chg(last_gwr_ptr, grey_wr_ptr);
+      last_gwr_ptr <= #1 grey_wr_ptr;
+   end 	
+end
+
+reg [AW:0] last_grd_ptr;
+always @(posedge rd_clk or negedge rd_reset_n) begin
+   if (!rd_reset_n) begin
+     last_grd_ptr <= #1 0;
+   end
+   else if (last_grd_ptr !== grey_rd_ptr) begin
+      check_ptr_chg(last_grd_ptr, grey_rd_ptr);
+      last_grd_ptr <= #1 grey_rd_ptr;
+   end 	
+end
+
+task check_ptr_chg;
+input [AW:0] last_ptr;
+input [AW:0] cur_ptr;
+integer i;
+integer ptr_diff;
+begin
+   ptr_diff = 0;
+   for (i=0; i<= AW; i=i+ 1'b1) begin
+      if (last_ptr[i] != cur_ptr[i]) begin
+         ptr_diff = ptr_diff + 1'b1;
+      end
+   end
+   if (ptr_diff !== 1) begin
+      $display($time, "%m, ERROR! async fifo ptr has changed more than noe bit, last=%h, cur=%h",
+				last_ptr, cur_ptr);
+      $stop;
+   end
+end
+endtask 	
+   // synopsys translate_on
+
+endmodule
diff --git a/verilog/rtl/lib/double_sync_high.v b/verilog/rtl/lib/double_sync_high.v
new file mode 100755
index 0000000..8e39520
--- /dev/null
+++ b/verilog/rtl/lib/double_sync_high.v
@@ -0,0 +1,88 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  OMS 8051 cores common library Module                        ////
+////                                                              ////
+////  This file is part of the OMS 8051 cores project             ////
+////  http://www.opencores.org/cores/oms8051mini/                 ////
+////                                                              ////
+////  Description                                                 ////
+////  OMS 8051 definitions.                                       ////
+////                                                              ////
+////  To Do:                                                      ////
+////    nothing                                                   ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Dinesh Annayya, dinesha@opencores.org                 ////
+////                                                              ////
+////  Revision : Nov 26, 2016                                     //// 
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//----------------------------------------------------------------------------
+// Simple Double sync logic with Reset value = 0
+// This double signal should be used for signal transiting from low to high
+//----------------------------------------------------------------------------
+
+module double_sync_high   (
+              in_data    ,
+              out_clk    ,
+              out_rst_n  ,
+              out_data   
+          );
+
+parameter WIDTH = 1;
+
+input [WIDTH-1:0]    in_data    ; // Input from Different clock domain
+input                out_clk    ; // Output clock
+input                out_rst_n  ; // Active low Reset
+output[WIDTH-1:0]    out_data   ; // Output Data
+
+
+reg [WIDTH-1:0]     in_data_s  ; // One   Cycle sync 
+reg [WIDTH-1:0]     in_data_2s ; // two   Cycle sync 
+reg [WIDTH-1:0]     in_data_3s ; // three Cycle sync 
+
+assign out_data =  in_data_3s;
+
+always @(negedge out_rst_n or posedge out_clk)
+begin
+   if(out_rst_n == 1'b0)
+   begin
+      in_data_s  <= {WIDTH{1'b0}};
+      in_data_2s <= {WIDTH{1'b0}};
+      in_data_3s <= {WIDTH{1'b0}};
+   end
+   else
+   begin
+      in_data_s  <= in_data;
+      in_data_2s <= in_data_s;
+      in_data_3s <= in_data_2s;
+   end
+end
+
+
+endmodule
diff --git a/verilog/rtl/lib/double_sync_low.v b/verilog/rtl/lib/double_sync_low.v
new file mode 100755
index 0000000..2709b91
--- /dev/null
+++ b/verilog/rtl/lib/double_sync_low.v
@@ -0,0 +1,88 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  OMS 8051 cores common library Module                        ////
+////                                                              ////
+////  This file is part of the OMS 8051 cores project             ////
+////  http://www.opencores.org/cores/oms8051mini/                 ////
+////                                                              ////
+////  Description                                                 ////
+////  OMS 8051 definitions.                                       ////
+////                                                              ////
+////  To Do:                                                      ////
+////    nothing                                                   ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Dinesh Annayya, dinesha@opencores.org                 ////
+////                                                              ////
+////  Revision : Nov 26, 2016                                     //// 
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//----------------------------------------------------------------------------
+// Simple Double sync logic with Reset value = 1
+// This double signal should be used for signal transiting from low to high
+//----------------------------------------------------------------------------
+
+module double_sync_low   (
+              in_data    ,
+              out_clk    ,
+              out_rst_n  ,
+              out_data   
+          );
+
+parameter WIDTH = 1;
+
+input [WIDTH-1:0]    in_data    ; // Input from Different clock domain
+input                out_clk    ; // Output clock
+input                out_rst_n  ; // Active low Reset
+output[WIDTH-1:0]    out_data   ; // Output Data
+
+
+reg [WIDTH-1:0]     in_data_s  ; // One   Cycle sync 
+reg [WIDTH-1:0]     in_data_2s ; // two   Cycle sync 
+reg [WIDTH-1:0]     in_data_3s ; // three Cycle sync 
+
+assign out_data =  in_data_3s;
+
+always @(negedge out_rst_n or posedge out_clk)
+begin
+   if(out_rst_n == 1'b0)
+   begin
+      in_data_s  <= {WIDTH{1'b1}};
+      in_data_2s <= {WIDTH{1'b1}};
+      in_data_3s <= {WIDTH{1'b1}};
+   end
+   else
+   begin
+      in_data_s  <= in_data;
+      in_data_2s <= in_data_s;
+      in_data_3s <= in_data_2s;
+   end
+end
+
+
+endmodule
diff --git a/verilog/rtl/lib/wb_crossbar.v b/verilog/rtl/lib/wb_crossbar.v
deleted file mode 100644
index 76b9981..0000000
--- a/verilog/rtl/lib/wb_crossbar.v
+++ /dev/null
@@ -1,398 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-////                                                              ////
-////  yifive common library Module                                ////
-////                                                              ////
-////  This file is part of the yifive cores project               ////
-////  http://www.opencores.org/cores/yifive/                      ////
-////                                                              ////
-////  Description                                                 ////
-////     This module  does the Wishone crossbar network           ////
-////                                                              ////
-////  To Do:                                                      ////
-////    nothing                                                   ////
-////                                                              ////
-////  Author(s):                                                  ////
-////      - Dinesh Annayya, dinesha@opencores.org                 ////
-////                                                              ////
-//////////////////////////////////////////////////////////////////////
-////  Revision :                                                  ////
-////     v0:    Nov 26, 2016, Dinesh A                            ////
-////            This files copied from my open core               ////
-////             turbo8051 project                                ////
-//////////////////////////////////////////////////////////////////////
-////                                                              ////
-//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
-////                                                              ////
-//// This source file may be used and distributed without         ////
-//// restriction provided that this copyright statement is not    ////
-//// removed from the file and that any derivative work contains  ////
-//// the original copyright notice and the associated disclaimer. ////
-////                                                              ////
-//// This source file is free software; you can redistribute it   ////
-//// and/or modify it under the terms of the GNU Lesser General   ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any   ////
-//// later version.                                               ////
-////                                                              ////
-//// This source is distributed in the hope that it will be       ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
-//// PURPOSE.  See the GNU Lesser General Public License for more ////
-//// details.                                                     ////
-////                                                              ////
-//// You should have received a copy of the GNU Lesser General    ////
-//// Public License along with this source; if not, download it   ////
-//// from http://www.opencores.org/lgpl.shtml                     ////
-////                                                              ////
-//////////////////////////////////////////////////////////////////////
-
-/**********************************************
-      Wish-bone cross bar M-Master By S-Slave
-**********************************************/
-
-module wb_crossbar (
-
-              rst_n               , 
-              clk                 ,
-
-
-    // Master Interface Signal
-              wbd_taddr_master    ,
-              wbd_din_master      ,
-              wbd_dout_master     ,
-              wbd_adr_master      , 
-              wbd_be_master       , 
-              wbd_we_master       , 
-              wbd_ack_master      ,
-              wbd_stb_master      , 
-              wbd_cyc_master      , 
-              wbd_err_master      ,
-              wbd_rty_master      ,
- 
-    // Slave Interface Signal
-              wbd_din_slave       , 
-              wbd_dout_slave      ,
-              wbd_adr_slave       , 
-              wbd_be_slave        , 
-              wbd_we_slave        , 
-              wbd_ack_slave       ,
-              wbd_stb_slave       , 
-              wbd_cyc_slave       , 
-              wbd_err_slave       ,
-              wbd_rty_slave
-         );
-
-parameter WB_SLAVE   = 4 ;
-parameter WB_MASTER  = 4 ;
-
-parameter D_WD    = 16; // Data Width
-parameter BE_WD   = 2;  // Byte Enable
-parameter ADR_WD  = 28; // Address Width
-parameter TAR_WD  = 4;  // Target Width
-
-input                  clk; // CLK_I The clock input [CLK_I] coordinates all activities 
-                            // for the internal logic within the WISHBONE interconnect. 
-                            // All WISHBONE output signals are registered at the 
-                            // rising edge of [CLK_I]. 
-                            // All WISHBONE input signals must be stable before the 
-                            // rising edge of [CLK_I]. 
-input                  rst_n; // RST_I The reset input [RST_I] forces the WISHBONE interface 
-                            // to restart. Furthermore, all internal self-starting state 
-                            // machines will be forced into an initial state. 
-
-input [(WB_MASTER *TAR_WD)-1:0] wbd_taddr_master; // target address from master 
-input [WB_MASTER-1:0]  wbd_stb_master;  
-                    // STB_O The strobe output [STB_O] indicates a valid data 
-                    // transfer cycle. It is used to qualify various other signals 
-                    // on the interface such as [SEL_O(7..0)]. The SLAVE must 
-                    // assert either the [ACK_I], [ERR_I] or [RTY_I] signals in 
-                    // response to every assertion of the [STB_O] signal. 
-output [WB_SLAVE-1:0]  wbd_stb_slave;  
-                    // STB_O The strobe output [STB_O] indicates a valid data 
-                    // transfer cycle. It is used to qualify various other signals 
-                    // on the interface such as [SEL_O(7..0)]. The SLAVE must 
-                    // assert either the [ACK_I], [ERR_I] or [RTY_I] signals in 
-                    // response to every assertion of the [STB_O] signal. 
-
-input [WB_MASTER-1:0]   wbd_we_master;    
-                    // WE_O The write enable output [WE_O] indicates whether the 
-                    // current local bus cycle is a READ or WRITE cycle. The 
-                    // signal is negated during READ cycles, and is asserted 
-                    // during WRITE cycles. 
-output [WB_SLAVE-1:0]   wbd_we_slave;    
-                    // WE_O The write enable output [WE_O] indicates whether the 
-                    // current local bus cycle is a READ or WRITE cycle. The 
-                    // signal is negated during READ cycles, and is asserted 
-                    // during WRITE cycles. 
-
-output [WB_MASTER-1:0]  wbd_ack_master; 
-                    // The acknowledge input [ACK_I], when asserted, 
-                    // indicates the termination of a normal bus cycle. 
-                    // Also see the [ERR_I] and [RTY_I] signal descriptions. 
-input [WB_SLAVE-1:0]  wbd_ack_slave; 
-                    // The acknowledge input [ACK_I], when asserted, 
-                    // indicates the termination of a normal bus cycle. 
-                    // Also see the [ERR_I] and [RTY_I] signal descriptions. 
-
-input [(WB_MASTER *ADR_WD)-1:0] wbd_adr_master; 
-                    // The address output array [ADR_O(63..0)] is used 
-                    // to pass a binary address, with the most significant 
-                    // address bit at the higher numbered end of the signal array. 
-                    // The lower array boundary is specific to the data port size. 
-                    // The higher array boundary is core-specific. 
-                    // In some cases (such as FIFO interfaces) 
-                    // the array may not be present on the interface. 
-
-output [(WB_SLAVE *ADR_WD)-1:0] wbd_adr_slave; 
-                    // The address output array [ADR_O(63..0)] is used 
-                    // to pass a binary address, with the most significant 
-                    // address bit at the higher numbered end of the signal array. 
-                    // The lower array boundary is specific to the data port size. 
-                    // The higher array boundary is core-specific. 
-                    // In some cases (such as FIFO interfaces) 
-                    // the array may not be present on the interface. 
-
-input [(WB_MASTER * BE_WD)-1:0] wbd_be_master; // Byte Enable 
-                    // SEL_O(7..0) The select output array [SEL_O(7..0)] indicates 
-                    // where valid data is expected on the [DAT_I(63..0)] signal 
-                    // array during READ cycles, and where it is placed on the 
-                    // [DAT_O(63..0)] signal array during WRITE cycles. 
-                    // Also see the [DAT_I(63..0)], [DAT_O(63..0)] and [STB_O] 
-                    // signal descriptions.
-output [(WB_SLAVE * BE_WD)-1:0] wbd_be_slave; // Byte Enable  
-                    // SEL_O(7..0) The select output array [SEL_O(7..0)] indicates 
-                    // where valid data is expected on the [DAT_I(63..0)] signal 
-                    // array during READ cycles, and where it is placed on the 
-                    // [DAT_O(63..0)] signal array during WRITE cycles. 
-                    // Also see the [DAT_I(63..0)], [DAT_O(63..0)] and [STB_O] 
-                    // signal descriptions.
-
-input [WB_MASTER -1:0] wbd_cyc_master; 
-                    // CYC_O The cycle output [CYC_O], when asserted, 
-                    // indicates that a valid bus cycle is in progress. 
-                    // The signal is asserted for the duration of all bus cycles. 
-                    // For example, during a BLOCK transfer cycle there can be 
-                    // multiple data transfers. The [CYC_O] signal is asserted 
-                    // during the first data transfer, and remains asserted 
-                    // until the last data transfer. The [CYC_O] signal is useful 
-                    // for interfaces with multi-port interfaces 
-                    // (such as dual port memories). In these cases, 
-                    // the [CYC_O] signal requests use of a common bus from an 
-                    // arbiter. Once the arbiter grants the bus to the MASTER, 
-                    // it is held until [CYC_O] is negated. 
-output [WB_SLAVE -1:0] wbd_cyc_slave; 
-                    // CYC_O The cycle output [CYC_O], when asserted, 
-                    // indicates that a valid bus cycle is in progress. 
-                    // The signal is asserted for the duration of all bus cycles. 
-                    // For example, during a BLOCK transfer cycle there can be 
-                    // multiple data transfers. The [CYC_O] signal is asserted 
-                    // during the first data transfer, and remains asserted 
-                    // until the last data transfer. The [CYC_O] signal is useful 
-                    // for interfaces with multi-port interfaces 
-                    // (such as dual port memories). In these cases, 
-                    // the [CYC_O] signal requests use of a common bus from an 
-                    // arbiter. Once the arbiter grants the bus to the MASTER, 
-                    // it is held until [CYC_O] is negated. 
-
-input [(WB_MASTER * D_WD)-1:0] wbd_din_master;  
-                    // DAT_I(63..0) The data input array [DAT_I(63..0)] is 
-                    // used to pass binary data. The array boundaries are 
-                    // determined by the port size. Also see the [DAT_O(63..0)] 
-                    // and [SEL_O(7..0)] signal descriptions. 
-
-output [(WB_SLAVE * D_WD)-1:0] wbd_din_slave;  
-                    // DAT_I(63..0) The data input array [DAT_I(63..0)] is 
-                    // used to pass binary data. The array boundaries are 
-                    // determined by the port size. Also see the [DAT_O(63..0)] 
-                    // and [SEL_O(7..0)] signal descriptions. 
-
-output [(WB_MASTER * D_WD)-1:0] wbd_dout_master; 
-                    // DAT_O(63..0) The data output array [DAT_O(63..0)] is 
-                    // used to pass binary data. The array boundaries are 
-                    // determined by the port size. Also see the [DAT_I(63..0)] 
-                         // and [SEL_O(7..0)] signal descriptions. 
-input [(WB_SLAVE * D_WD)-1:0] wbd_dout_slave; 
-                    // DAT_O(63..0) The data output array [DAT_O(63..0)] is 
-                    // used to pass binary data. The array boundaries are 
-                    // determined by the port size. Also see the [DAT_I(63..0)] 
-                    // and [SEL_O(7..0)] signal descriptions. 
-
-output [WB_MASTER -1:0]  wbd_err_master; 
-                    // ERR_I The error input [ERR_I] indicates an abnormal 
-                    // cycle termination. The source of the error, and the 
-                    // response generated by the MASTER is defined by the IP core 
-                    // supplier in the WISHBONE DATASHEET. Also see the [ACK_I] 
-                    // and [RTY_I] signal descriptions. 
-input [WB_SLAVE -1:0]  wbd_err_slave; 
-                    // ERR_I The error input [ERR_I] indicates an abnormal 
-                    // cycle termination. The source of the error, and the 
-                    // response generated by the MASTER is defined by the IP core 
-                    // supplier in the WISHBONE DATASHEET. Also see the [ACK_I] 
-                    // and [RTY_I] signal descriptions. 
-
-output [WB_MASTER -1:0]   wbd_rty_master; 
-                    // RTY_I The retry input [RTY_I] indicates that the indicates 
-                    // that the interface is not ready to accept or send data, and 
-                    // that the cycle should be retried. When and how the cycle is 
-                    // retried is defined by the IP core supplier in the WISHBONE 
-                    // DATASHEET. Also see the [ERR_I] and [RTY_I] signal 
-                    // descriptions. 
-input [WB_SLAVE -1:0]   wbd_rty_slave; 
-                    // RTY_I The retry input [RTY_I] indicates that the indicates 
-                    // that the interface is not ready to accept or send data, and 
-                    // that the cycle should be retried. When and how the cycle is 
-                    // retried is defined by the IP core supplier in the WISHBONE 
-                    // DATASHEET. Also see the [ERR_I] and [RTY_I] signal 
-                    // descriptions. 
-
-
-reg  [WB_MASTER-1:0]  wbd_ack_master; 
-reg  [WB_MASTER-1:0]  wbd_err_master; 
-reg  [WB_MASTER-1:0]  wbd_rty_master; 
-
-
-reg  [WB_MASTER-1:0]  master_busy; // master busy flag
-reg  [WB_SLAVE-1:0]   slave_busy;  // slave busy flag
-reg  [TAR_WD -1:0]     master_mx_id[WB_MASTER-1:0];
-reg  [TAR_WD -1:0]     slave_mx_id [WB_SLAVE-1:0];
-
-wire  [TAR_WD-1:0]     wbd_taddr_master_t[WB_MASTER-1:0]; // target address from master 
-wire  [D_WD-1:0]       wbd_din_master_t[WB_MASTER-1:0]; // target address from master 
-reg   [D_WD-1:0]       wbd_dout_master_t[WB_MASTER-1:0]; // target address from master 
-wire  [ADR_WD-1:0]     wbd_adr_master_t[WB_MASTER-1:0]; // target address from master 
-wire  [BE_WD-1:0]      wbd_be_master_t[WB_MASTER-1:0]; // target address from master 
-
-
-reg  [WB_SLAVE-1:0]  wbd_stb_slave; 
-reg  [WB_SLAVE-1:0]  wbd_we_slave; 
-reg  [WB_SLAVE-1:0]  wbd_cyc_slave; 
-wire [D_WD-1:0]      wbd_dout_slave_t[WB_SLAVE-1:0]; // target data towards master 
-
-
-reg   [D_WD-1:0]     wbd_din_slave_t[WB_SLAVE-1:0]; // target address from master 
-reg   [ADR_WD-1:0]    wbd_adr_slave_t[WB_SLAVE-1:0]; // target address from master 
-reg   [BE_WD-1:0]     wbd_be_slave_t[WB_SLAVE-1:0]; // target address from master 
-
-integer i,k,l,n;
-
-  
-/**********************************************************
-   Re-Arraging the array in seperate two dimensional information
-***********************************************************/
-
-genvar j,m; 
-generate        
-
-  // Connect the Master Mux
-  for(j=0; j < WB_MASTER ; j = j + 1) begin : master_expand
-     assign wbd_taddr_master_t[j] = wbd_taddr_master[((j+1)*TAR_WD)-1:j * TAR_WD];
-     assign wbd_din_master_t[j]  = wbd_din_master[((j+1)*D_WD)-1:j * D_WD];
-     assign wbd_adr_master_t[j]  = wbd_adr_master[((j+1)*ADR_WD)-1:j * ADR_WD];
-     assign wbd_be_master_t[j]   = wbd_be_master[((j+1)*BE_WD)-1:j * BE_WD];
-
-     assign wbd_dout_master[((j+1)*D_WD)-1:j * D_WD] = wbd_dout_master_t[j];
-  end
-
-  // Connect the Slave Mux
-  for(m=0; m < WB_SLAVE ; m = m + 1) begin : slave_expand
-     assign wbd_din_slave[((m+1)*D_WD)-1:m * D_WD]        = wbd_din_slave_t[m];
-     assign wbd_adr_slave[((m+1)*ADR_WD)-1:m * ADR_WD]   = wbd_adr_slave_t[m];
-     assign wbd_be_slave[((m+1)*BE_WD)-1:m * BE_WD]      = wbd_be_slave_t[m];
-
-     assign wbd_dout_slave_t[m]   = wbd_dout_slave[((m+1)*D_WD)-1:m * D_WD];
-
-  end
-endgenerate
-
-always @*   begin
-   for(k = 0; k < WB_MASTER; k = k + 1) begin
-      if(master_busy[k] == 1) begin
-         wbd_dout_master_t[k] = wbd_dout_slave_t[master_mx_id[k]];
-         wbd_ack_master[k]    = wbd_ack_slave[master_mx_id[k]];
-         wbd_err_master[k]    = wbd_err_slave[master_mx_id[k]];
-         wbd_rty_master[k]    = wbd_rty_slave[master_mx_id[k]];
-      end else begin
-         wbd_dout_master_t[k] = 0;
-         wbd_ack_master[k]    = 0;
-         wbd_err_master[k]    = 0;
-         wbd_rty_master[k]    = 0;
-      end
-   end
-   for(l = 0; l < WB_SLAVE; l = l + 1) begin
-      if(slave_busy[l] == 1) begin
-         wbd_din_slave_t[l]  = wbd_din_master_t[slave_mx_id[l]];
-         wbd_adr_slave_t[l]  = wbd_adr_master_t[slave_mx_id[l]];
-         wbd_be_slave_t[l]   = wbd_be_master_t[slave_mx_id[l]];
-         wbd_stb_slave[l]    = wbd_stb_master[slave_mx_id[l]];
-         wbd_we_slave[l]     = wbd_we_master[slave_mx_id[l]];
-         wbd_cyc_slave[l]    = wbd_cyc_master[slave_mx_id[l]];
-      end else begin
-         wbd_din_slave_t[l]  = 0;
-         wbd_adr_slave_t[l]  = 0;
-         wbd_be_slave_t[l]   = 0;
-         wbd_stb_slave[l]    = 0;
-         wbd_we_slave[l]     = 0;
-         wbd_cyc_slave[l]    = 0;
-      end
-   end
-end
-
-/*******************************************************
-   Parsing through the master and deciding on mux connectio
-   Step-1: analysis the master from 0 to total master
-   Step-2: If the previously master is not busy, 
-           Then check for any new request from the master and
-           check corresponding slave is free or not. If there is 
-           master request and requesting slave is free. 
-           Then set the master max id to slave id &
-           requesting slave to master number & set the master
-           and slave busy flag
-   Step-3: If the previous state of master is busy and bus-cycle
-           is de-asserted, then reset the master and corresponding
-           slave busy flag
-
-*********************************************************/ 
-
-always @(negedge rst_n or posedge clk) begin
-   if(rst_n == 0) begin
-      master_busy   <= 0;
-      slave_busy    <= 0;
-   end else begin
-      for(i = 0; i < WB_MASTER; i = i + 1) begin
-         if(master_busy[i] == 0) begin
-            if(wbd_stb_master[i] & slave_busy[wbd_taddr_master_t[i]] == 0) begin
-	       $display("Locking Master Id: %d for tar_master: %d, Total Master: %x ", i, wbd_taddr_master_t[i], wbd_taddr_master);
-               slave_busy[wbd_taddr_master_t[i]]   = 1;
-               master_busy[i]              = 1;
-            end
-         end else if(wbd_cyc_master[i] == 0) begin
-            master_busy[i]            <= 0;
-            slave_busy[wbd_taddr_master_t[i]] <= 0;
-         end
-      end
-   end
-end
-
-// Seperated non resetable two dimensional reg
-always @(posedge clk) begin
-      for(n = 0; n < WB_MASTER; n = n + 1) begin
-         if(master_busy[n] == 0) begin
-            if(wbd_stb_master[n] & slave_busy[wbd_taddr_master_t[n]] == 0) begin
-               master_mx_id[n] <= wbd_taddr_master_t[n];
-               slave_mx_id [wbd_taddr_master_t[n]] <= n;
-               // synopsys translate_off
-                $display("%m:%t: Locking Master : %d with Slave : %d",$time,i,wbd_taddr_master_t[n]);
-               // synopsys translate_on
-            end
-         end else if(wbd_cyc_master[n] == 0) begin
-	    if(master_busy[n] == 1) begin
-            // synopsys translate_off
-              $display("%m:%t: Releasing Master : %d with Slave : %d",$time,i,wbd_taddr_master_t[n]);
-            // synopsys translate_on
-            end
-         end
-      end
-end
-
-
-endmodule
diff --git a/verilog/rtl/lib/wb_stagging.sv b/verilog/rtl/lib/wb_stagging.sv
new file mode 100644
index 0000000..5fce5f1
--- /dev/null
+++ b/verilog/rtl/lib/wb_stagging.sv
@@ -0,0 +1,155 @@
+//----------------------------------------------------------------------
+// This logic create a holding register for Wishbone interface.
+// This is usefull to break timing issue at interconnect
+//
+// Limitation: Due to stagging FF, Continous Burst of Wishbone will have one
+// cycle break between each transaction
+//----------------------------------------------------------------------
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  Wishbone Stagging FF                                        ////
+////                                                              ////
+////  This file is part of the YIFive cores project               ////
+////  http://www.opencores.org/cores/yifive/                      ////
+////                                                              ////
+////  Description                                                 ////
+////    This logic create a holding FF for Wishbone interface.    ////
+////    This is usefull to break timing issue at interconnect     ////
+////                                                              ////
+////  Limitation: Due to stagging FF, Continous Burst of          ////
+////  Wishbone will have one cycle break between each transaction ////
+////                                                              ////
+////  To Do:                                                      ////
+////    nothing                                                   ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Dinesh Annayya, dinesha@opencores.org                 ////
+////                                                              ////
+////  Revision :                                                  ////
+////    0.1 - 12th June 2021, Dinesh A                            ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+
+module wb_stagging (
+         input logic		clk_i, 
+         input logic            rst_n,
+         // WishBone Input master I/P
+         input   logic	[31:0]	m_wbd_dat_i,
+         input   logic  [31:0]	m_wbd_adr_i,
+         input   logic  [3:0]	m_wbd_sel_i,
+         input   logic  	m_wbd_we_i,
+         input   logic  	m_wbd_cyc_i,
+         input   logic  	m_wbd_stb_i,
+         input   logic  [3:0]	m_wbd_tid_i,
+         output  logic	[31:0]	m_wbd_dat_o,
+         output  logic		m_wbd_ack_o,
+         output  logic		m_wbd_err_o,
+
+         // Slave Interface
+         input	logic [31:0]	s_wbd_dat_i,
+         input	logic 	        s_wbd_ack_i,
+         input	logic 	        s_wbd_err_i,
+         output	logic [31:0]	s_wbd_dat_o,
+         output	logic [31:0]	s_wbd_adr_o,
+         output	logic [3:0]	s_wbd_sel_o,
+         output	logic 	        s_wbd_we_o,
+         output	logic 	        s_wbd_cyc_o,
+         output	logic 	        s_wbd_stb_o,
+         output	logic [3:0]	s_wbd_tid_o
+
+);
+
+logic        holding_busy   ; // Indicate Stagging for Free or not
+logic [31:0] m_wbd_dat_i_ff ; // Flopped vesion of m_wbd_dat_i
+logic [31:0] m_wbd_adr_i_ff ; // Flopped vesion of m_wbd_adr_i
+logic [3:0]  m_wbd_sel_i_ff ; // Flopped vesion of m_wbd_sel_i
+logic        m_wbd_we_i_ff  ; // Flopped vesion of m_wbd_we_i
+logic        m_wbd_cyc_i_ff ; // Flopped vesion of m_wbd_cyc_i
+logic        m_wbd_stb_i_ff ; // Flopped vesion of m_wbd_stb_i
+logic [3:0]  m_wbd_tid_i_ff ; // Flopped vesion of m_wbd_tid_i
+logic [31:0] s_wbd_dat_i_ff ; // Flopped vesion of s_wbd_dat_i
+logic        s_wbd_ack_i_ff ; // Flopped vesion of s_wbd_ack_i
+logic        s_wbd_err_i_ff ; // Flopped vesion of s_wbd_err_i
+
+
+assign s_wbd_dat_o = m_wbd_dat_i_ff;
+assign s_wbd_adr_o = m_wbd_adr_i_ff;
+assign s_wbd_sel_o = m_wbd_sel_i_ff;
+assign s_wbd_we_o  = m_wbd_we_i_ff;
+assign s_wbd_cyc_o = m_wbd_cyc_i_ff;
+assign s_wbd_stb_o = m_wbd_stb_i_ff;
+assign s_wbd_tid_o = m_wbd_tid_i_ff;
+
+assign m_wbd_dat_o = s_wbd_dat_i_ff;
+assign m_wbd_ack_o = s_wbd_ack_i_ff;
+assign m_wbd_err_o = s_wbd_err_i_ff;
+
+always @(negedge rst_n or posedge clk_i)
+begin
+   if(rst_n == 1'b0) begin
+       holding_busy   <= 1'b0;
+       m_wbd_dat_i_ff <= 'h0;
+       m_wbd_adr_i_ff <= 'h0;
+       m_wbd_sel_i_ff <= 'h0;
+       m_wbd_we_i_ff  <= 'h0;
+       m_wbd_cyc_i_ff <= 'h0;
+       m_wbd_stb_i_ff <= 'h0;
+       m_wbd_tid_i_ff <= 'h0;
+       s_wbd_dat_i_ff <= 'h0;
+       s_wbd_ack_i_ff <= 'h0;
+       s_wbd_err_i_ff <= 'h0;
+   end else begin
+       s_wbd_dat_i_ff <= s_wbd_dat_i;
+       s_wbd_ack_i_ff <= s_wbd_ack_i;
+       s_wbd_err_i_ff <= s_wbd_err_i;
+       if(m_wbd_stb_i && holding_busy == 0 && m_wbd_ack_o == 0) begin
+          holding_busy   <= 1'b1;
+          m_wbd_dat_i_ff <= m_wbd_dat_i;
+          m_wbd_adr_i_ff <= m_wbd_adr_i;
+          m_wbd_sel_i_ff <= m_wbd_sel_i;
+          m_wbd_we_i_ff  <= m_wbd_we_i;
+          m_wbd_cyc_i_ff <= m_wbd_cyc_i;
+          m_wbd_stb_i_ff <= m_wbd_stb_i;
+          m_wbd_tid_i_ff <= m_wbd_tid_i;
+       end else if (holding_busy && s_wbd_ack_i) begin
+          holding_busy   <= 1'b0;
+          m_wbd_dat_i_ff <= 'h0;
+          m_wbd_adr_i_ff <= 'h0;
+          m_wbd_sel_i_ff <= 'h0;
+          m_wbd_we_i_ff  <= 'h0;
+          m_wbd_cyc_i_ff <= 'h0;
+          m_wbd_stb_i_ff <= 'h0;
+          m_wbd_tid_i_ff <= 'h0;
+       end
+   end
+end
+
+
+endmodule
+
diff --git a/verilog/rtl/spi_master/src/spim_clkgen.sv b/verilog/rtl/spi_master/src/spim_clkgen.sv
index 2c6b236..8c9fa83 100644
--- a/verilog/rtl/spi_master/src/spim_clkgen.sv
+++ b/verilog/rtl/spi_master/src/spim_clkgen.sv
@@ -58,25 +58,22 @@
     input  logic                        clk,
     input  logic                        rstn,
     input  logic                        en,
-    input  logic          [7:0]         cfg_sck_period,
+    input  logic          [5:0]         cfg_sck_period,
     output logic                        spi_clk,
     output logic                        spi_fall,
     output logic                        spi_rise
 );
 
-	logic [7:0] sck_half_period;
-	logic [7:0] clk_cnt;
+	logic [5:0] sck_half_period;
+	logic [5:0] clk_cnt;
 
-    assign sck_half_period = {1'b0, cfg_sck_period[7:1]};
+    assign sck_half_period = {1'b0, cfg_sck_period[5:1]};
    
     // The first transition on the sck_toggle happens one SCK period
     // after en is asserted
     always @(posedge clk or negedge rstn) begin
     	if(!rstn) begin
-    	   clk_cnt    <= 'h1;
     	   spi_clk    <= 1'b1;
-	   spi_fall   <= 1'b0;
-	   spi_rise   <= 1'b0;
     	end // if (!reset_n)
     	else 
     	begin
diff --git a/verilog/rtl/spi_master/src/spim_ctrl.sv b/verilog/rtl/spi_master/src/spim_ctrl.sv
index 8ce6524..5ae41ad 100644
--- a/verilog/rtl/spi_master/src/spim_ctrl.sv
+++ b/verilog/rtl/spi_master/src/spim_ctrl.sv
@@ -49,7 +49,7 @@
     input  logic                          rstn,
     output logic                          eot,
 
-    input  logic                    [7:0] spi_clk_div,
+    input  logic                    [5:0] spi_clk_div,
     output logic                    [8:0] spi_status,
 
 
diff --git a/verilog/rtl/spi_master/src/spim_regs.sv b/verilog/rtl/spi_master/src/spim_regs.sv
index 0128568..cfb8ead 100644
--- a/verilog/rtl/spi_master/src/spim_regs.sv
+++ b/verilog/rtl/spi_master/src/spim_regs.sv
@@ -227,6 +227,7 @@
    end
 end
 
+  wire [3:0] reg_addr = spim_wb_addr[5:2];
   integer byte_index;
   always_ff @(negedge rst_n or posedge mclk) begin
     if ( rst_n == 1'b0 ) begin
@@ -328,7 +329,7 @@
        endcase
     end else if (spim_reg_req & spim_wb_we )
     begin
-      case(spim_wb_addr[7:4])
+      case(reg_addr)
         REG_CTRL:
         begin
           if ( spim_wb_be[0] == 1 )
@@ -398,8 +399,6 @@
 
 
 
-  wire [3:0] reg_addr = spim_wb_addr[7:4];
-
   // implement slave model register read mux
   always_comb
     begin
diff --git a/verilog/rtl/spi_master/synth/Makefile b/verilog/rtl/spi_master/synth/Makefile
new file mode 100644
index 0000000..1c814b2
--- /dev/null
+++ b/verilog/rtl/spi_master/synth/Makefile
@@ -0,0 +1,32 @@
+#------------------------------------------------------------------------------
+# Makefile for Synthesis
+#------------------------------------------------------------------------------
+
+# Paths
+export ROOT_DIR := $(shell pwd)
+export REPORT_DIR  := $(ROOT_DIR)/reports
+export NETLIST_DIR  := $(ROOT_DIR)/netlist
+export TMP_DIR  := $(ROOT_DIR)/tmp
+
+
+# Targets
+.PHONY: clean create synth
+
+default: clean create synth
+
+synth: clean create 
+	yosys -g -c synth.tcl -l synth.log
+
+create:
+	mkdir -p ./tmp/synthesis; 
+	mkdir -p ./reports; 
+	mkdir -p ./netlist;
+	$(OPENLANE_ROOT)/scripts/libtrim.pl $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib $(PDK_ROOT)/sky130A/libs.tech/openlane/sky130_fd_sc_hd/no_synth.cells > ./tmp/trimmed.lib
+
+
+
+clean:
+	$(RM) -R synth.log
+	$(RM) -R $(REPORT_DIR)
+	$(RM) -R $(NETLIST_DIR)
+	$(RM) -R $(TMP_DIR)
diff --git a/verilog/rtl/spi_master/synth/synth.tcl b/verilog/rtl/spi_master/synth/synth.tcl
new file mode 100755
index 0000000..1c327cf
--- /dev/null
+++ b/verilog/rtl/spi_master/synth/synth.tcl
@@ -0,0 +1,388 @@
+# Copyright 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+# inputs expected as env vars
+#set opt $::env(SYNTH_OPT)
+########### config.tcl ##################
+# User config
+
+# User config
+set ::env(DESIGN_DIR) ../
+
+set ::env(PROJ_DIR) ../../../../
+
+# User config
+set ::env(DESIGN_NAME) spim_ctrl
+
+# Change if needed
+set ::env(VERILOG_FILES) [glob  \
+	../src/spim_clkgen.sv   \
+        ../src/spim_ctrl.sv    \
+	../src/spim_fifo.sv    \
+	../src/spim_regs.sv    \
+	../src/spim_rx.sv    \
+	../src/spim_top.sv    \
+	../src/spim_tx.sv ]
+
+
+set ::env(SYNTH_DEFINES) [list YOSYS ]
+
+
+set ::env(LIB_SYNTH)  ./tmp/trimmed.lib
+
+
+# Fill this
+set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PORT) "mclk"
+set ::env(CLOCK_TREE_SYNTH) 0
+
+set ::env(RUN_SIMPLE_CTS) 0
+set ::env(SYNTH_BUFFERING) 0
+set ::env(SYNTH_SIZING) 0
+
+set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_8"
+set ::env(SYNTH_CAP_LOAD) "17.65"
+set ::env(SYNTH_MAX_TRAN) "[expr {0.1*10.0}]"
+
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(FP_CORE_UTIL) 50
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+set ::env(CELL_PAD) 4
+
+set ::env(SYNTH_NO_FLAT) "0"
+
+
+set ::env(SYNTH_STRATEGY) "AREA 0"
+set ::env(SYNTH_TIELO_PORT) "sky130_fd_sc_hd__conb_1 LO"
+set ::env(SYNTH_TIEHI_PORT) "sky130_fd_sc_hd__conb_1 HI"
+set ::env(SYNTH_MIN_BUF_PORT) "sky130_fd_sc_hd__buf_2 A X"
+
+
+set ::env(CLOCK_NET) $::env(CLOCK_PORT)
+
+
+
+set ::env(yosys_tmp_file_tag) "./tmp/"
+set ::env(TMP_DIR) "./tmp/"
+set ::env(yosys_netlist_dir) "./netlist"
+set ::env(yosys_report_file_tag) "./reports/yosys"
+set ::env(yosys_result_file_tag) "./reports/yosys.synthesis"
+
+set ::env(SAVE_NETLIST) $::env(yosys_netlist_dir)/$::env(DESIGN_NAME).gv
+
+
+
+########### End of config.tcl
+set buffering $::env(SYNTH_BUFFERING)
+set sizing $::env(SYNTH_SIZING)
+
+yosys -import
+
+set vtop $::env(DESIGN_NAME)
+#set sdc_file $::env(SDC_FILE)
+set sclib $::env(LIB_SYNTH)
+
+if { [info exists ::env(SYNTH_DEFINES) ] } {
+	foreach define $::env(SYNTH_DEFINES) {
+		log "Defining $define"
+		verilog_defines -D$define
+	}
+}
+
+set vIdirsArgs ""
+if {[info exist ::env(VERILOG_INCLUDE_DIRS)]} {
+	foreach dir $::env(VERILOG_INCLUDE_DIRS) {
+		log "Adding include file -I$dir "
+		lappend vIdirsArgs "-I$dir"
+	}
+	set vIdirsArgs [join $vIdirsArgs]
+}
+
+
+
+if { [info exists ::env(EXTRA_LIBS) ] } {
+	foreach lib $::env(EXTRA_LIBS) {
+		read_liberty {*}$vIdirsArgs -lib -ignore_miss_dir -setattr blackbox $lib
+	}
+}
+
+
+
+# ns expected (in sdc as well)
+set clock_period [expr {$::env(CLOCK_PERIOD)*1000}]
+
+set driver  $::env(SYNTH_DRIVING_CELL)
+set cload   $::env(SYNTH_CAP_LOAD)
+# input pin cap of IN_3VX8
+set max_FO $::env(SYNTH_MAX_FANOUT)
+if {![info exist ::env(SYNTH_MAX_TRAN)]} {
+	set ::env(SYNTH_MAX_TRAN) [expr {0.1*$clock_period}]
+} else {
+	set ::env(SYNTH_MAX_TRAN) [expr {$::env(SYNTH_MAX_TRAN) * 1000}]
+}
+set max_Tran $::env(SYNTH_MAX_TRAN)
+
+
+# Mapping parameters
+set A_factor  0.00
+set B_factor  0.88
+set F_factor  0.00
+
+# Don't change these unless you know what you are doing
+set stat_ext    ".stat.rpt"
+set chk_ext    ".chk.rpt"
+set gl_ext      ".gl.v"
+set constr_ext  ".$clock_period.constr"
+set timing_ext  ".timing.txt"
+set abc_ext     ".abc"
+
+
+# get old sdc, add library specific stuff for abc scripts
+set sdc_file $::env(yosys_tmp_file_tag).sdc
+set outfile [open ${sdc_file} w]
+#puts $outfile $sdc_data
+puts $outfile "set_driving_cell ${driver}"
+puts $outfile "set_load ${cload}"
+close $outfile
+
+
+# ABC Scrips
+set abc_rs_K    "resub,-K,"
+set abc_rs      "resub"
+set abc_rsz     "resub,-z"
+set abc_rw_K    "rewrite,-K,"
+set abc_rw      "rewrite"
+set abc_rwz     "rewrite,-z"
+set abc_rf      "refactor"
+set abc_rfz     "refactor,-z"
+set abc_b       "balance"
+
+set abc_resyn2        "${abc_b}; ${abc_rw}; ${abc_rf}; ${abc_b}; ${abc_rw}; ${abc_rwz}; ${abc_b}; ${abc_rfz}; ${abc_rwz}; ${abc_b}"
+set abc_share         "strash; multi,-m; ${abc_resyn2}"
+set abc_resyn2a       "${abc_b};${abc_rw};${abc_b};${abc_rw};${abc_rwz};${abc_b};${abc_rwz};${abc_b}"
+set abc_resyn3        "balance;resub;resub,-K,6;balance;resub,-z;resub,-z,-K,6;balance;resub,-z,-K,5;balance"
+set abc_resyn2rs      "${abc_b};${abc_rs_K},6;${abc_rw};${abc_rs_K},6,-N,2;${abc_rf};${abc_rs_K},8;${abc_rw};${abc_rs_K},10;${abc_rwz};${abc_rs_K},10,-N,2;${abc_b},${abc_rs_K},12;${abc_rfz};${abc_rs_K},12,-N,2;${abc_rwz};${abc_b}"
+
+set abc_choice        "fraig_store; ${abc_resyn2}; fraig_store; ${abc_resyn2}; fraig_store; fraig_restore"
+set abc_choice2      "fraig_store; balance; fraig_store; ${abc_resyn2}; fraig_store; ${abc_resyn2}; fraig_store; ${abc_resyn2}; fraig_store; fraig_restore"
+
+set abc_map_old_cnt			"map,-p,-a,-B,0.2,-A,0.9,-M,0"
+set abc_map_old_dly         "map,-p,-B,0.2,-A,0.9,-M,0"
+set abc_retime_area         "retime,-D,{D},-M,5"
+set abc_retime_dly          "retime,-D,{D},-M,6"
+set abc_map_new_area        "amap,-m,-Q,0.1,-F,20,-A,20,-C,5000"
+
+set abc_area_recovery_1       "${abc_choice}; map;"
+set abc_area_recovery_2       "${abc_choice2}; map;"
+
+set map_old_cnt			    "map,-p,-a,-B,0.2,-A,0.9,-M,0"
+set map_old_dly			    "map,-p,-B,0.2,-A,0.9,-M,0"
+set abc_retime_area   	"retime,-D,{D},-M,5"
+set abc_retime_dly    	"retime,-D,{D},-M,6"
+set abc_map_new_area  	"amap,-m,-Q,0.1,-F,20,-A,20,-C,5000"
+
+if {$buffering==1} {
+	set abc_fine_tune		"buffer,-N,${max_FO},-S,${max_Tran};upsize,{D};dnsize,{D}"
+} elseif {$sizing} {
+	set abc_fine_tune       "upsize,{D};dnsize,{D}"
+} else {
+	set abc_fine_tune       ""
+}
+
+
+set delay_scripts [list \
+	"+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_dly}; scleanup;${abc_map_old_dly};retime,-D,{D};${abc_fine_tune};stime,-p;print_stats -m" \
+	\
+	"+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_dly}; scleanup;${abc_choice2};${abc_map_old_dly};${abc_area_recovery_2}; retime,-D,{D};${abc_fine_tune};stime,-p;print_stats -m" \
+	\
+	"+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_dly}; scleanup;${abc_choice};${abc_map_old_dly};${abc_area_recovery_1}; retime,-D,{D};${abc_fine_tune};stime,-p;print_stats -m" \
+	\
+	"+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_area};scleanup;${abc_choice2};${abc_map_new_area};${abc_choice2};${abc_map_old_dly};retime,-D,{D};${abc_fine_tune};stime,-p;print_stats -m" \
+	]
+
+set area_scripts [list \
+	"+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_area};scleanup;${abc_choice2};${abc_map_new_area};retime,-D,{D};${abc_fine_tune};stime,-p;print_stats -m" \
+	\
+	"+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_resyn2};${abc_retime_area};scleanup;${abc_choice2};${abc_map_new_area};${abc_choice2};${abc_map_new_area};retime,-D,{D};${abc_fine_tune};stime,-p;print_stats -m" \
+	\
+	"+read_constr,${sdc_file};fx;mfs;strash;refactor;${abc_choice2};${abc_retime_area};scleanup;${abc_choice2};${abc_map_new_area};${abc_choice2};${abc_map_new_area};retime,-D,{D};${abc_fine_tune};stime,-p;print_stats -m" \
+	]
+
+set all_scripts [list {*}$delay_scripts {*}$area_scripts]
+
+set strategy_parts [split $::env(SYNTH_STRATEGY)]
+
+proc synth_strategy_format_err { } {
+	upvar area_scripts area_scripts
+	upvar delay_scripts delay_scripts
+	log -stderr "\[ERROR] Misformatted SYNTH_STRATEGY (\"$::env(SYNTH_STRATEGY)\")."
+	log -stderr "\[ERROR] Correct format is \"DELAY|AREA 0-[expr [llength $delay_scripts]-1]|0-[expr [llength $area_scripts]-1]\"."
+	exit 1
+}
+
+if { [llength $strategy_parts] != 2 } {
+	synth_strategy_format_err
+}
+
+set strategy_type [lindex $strategy_parts 0]
+set strategy_type_idx [lindex $strategy_parts 1]
+
+if { $strategy_type != "AREA" && $strategy_type != "DELAY" } {
+	log -stderr "\[ERROR] AREA|DELAY tokens not found. ($strategy_type)"
+	synth_strategy_format_err
+}
+
+if { $strategy_type == "DELAY" && $strategy_type_idx >= [llength $delay_scripts] } {
+	log -stderr "\[ERROR] strategy index ($strategy_type_idx) is too high."
+	synth_strategy_format_err
+}
+
+if { $strategy_type == "AREA" && $strategy_type_idx >= [llength $area_scripts] } {
+	log -stderr "\[ERROR] strategy index ($strategy_type_idx) is too high."
+	synth_strategy_format_err
+}
+
+if { $strategy_type == "DELAY" } {
+	set strategy $strategy_type_idx
+} else {
+	set strategy [expr {[llength $delay_scripts]+$strategy_type_idx}]
+}
+
+
+for { set i 0 } { $i < [llength $::env(VERILOG_FILES)] } { incr i } {
+	read_verilog -sv {*}$vIdirsArgs [lindex $::env(VERILOG_FILES) $i]
+}
+
+if { [info exists ::env(VERILOG_FILES_BLACKBOX)] } {
+	foreach verilog_file $::env(VERILOG_FILES_BLACKBOX) {
+		read_verilog -sv {*}$vIdirsArgs -lib $verilog_file
+	}
+}
+select -module $vtop
+show -format dot -prefix $::env(TMP_DIR)/synthesis/hierarchy
+select -clear
+
+hierarchy -check -top $vtop
+
+# Infer tri-state buffers.
+set tbuf_map false
+if { [info exists ::env(TRISTATE_BUFFER_MAP)] } {
+        if { [file exists $::env(TRISTATE_BUFFER_MAP)] } {
+                set tbuf_map true
+                tribuf
+        } else {
+          log "WARNING: TRISTATE_BUFFER_MAP is defined but could not be found: $::env(TRISTATE_BUFFER_MAP)"
+        }
+}
+
+if { $::env(SYNTH_NO_FLAT) } {
+	synth -top $vtop
+} else {
+	synth -top $vtop -flatten
+}
+
+share -aggressive
+opt
+opt_clean -purge
+
+tee -o "$::env(yosys_report_file_tag)_pre.stat" stat
+
+# Map tri-state buffers.
+if { $tbuf_map } {
+        log {mapping tbuf}
+        techmap -map $::env(TRISTATE_BUFFER_MAP)
+        simplemap
+}
+
+# handle technology mapping of 4-MUX, and tell Yosys to infer 4-muxes
+if { [info exists ::env(SYNTH_MUX4_MAP)] && [file exists $::env(SYNTH_MUX4_MAP)] } {
+  muxcover -mux4 
+  techmap -map $::env(SYNTH_MUX4_MAP)
+  simplemap
+}
+
+# handle technology mapping of 2-MUX
+if { [info exists ::env(SYNTH_MUX_MAP)] && [file exists $::env(SYNTH_MUX_MAP)] } {
+  techmap -map $::env(SYNTH_MUX_MAP)
+  simplemap
+}
+
+# handle technology mapping of latches
+if { [info exists ::env(SYNTH_LATCH_MAP)] && [file exists $::env(SYNTH_LATCH_MAP)] } {
+	techmap -map $::env(SYNTH_LATCH_MAP)
+	simplemap
+}
+
+dfflibmap -liberty $sclib
+tee -o "$::env(yosys_report_file_tag)_dff.stat" stat
+
+if { [info exists ::env(SYNTH_EXPLORE)] && $::env(SYNTH_EXPLORE) } {
+	design -save myDesign
+
+	for { set index 0 }  { $index < [llength $all_scripts] }  { incr index } {
+		log "\[INFO\]: ABC: WireLoad : S_$index"
+		design -load myDesign
+
+		abc -D $clock_period \
+			-constr "$sdc_file" \
+			-liberty $sclib  \
+			-script [lindex $all_scripts $index]
+
+		setundef -zero
+
+		hilomap -hicell {*}$::env(SYNTH_TIEHI_PORT) -locell {*}$::env(SYNTH_TIELO_PORT)
+
+		# get rid of the assignments that make verilog2def fail
+		splitnets
+		opt_clean -purge
+		insbuf -buf {*}$::env(SYNTH_MIN_BUF_PORT)
+
+		tee -o "$::env(yosys_report_file_tag)_$index$chk_ext" check
+		write_verilog -noattr -noexpr -nohex -nodec -defparam "$::env(yosys_result_file_tag)_$index.v"
+		design -reset
+	}
+} else {
+
+	log "\[INFO\]: ABC: WireLoad : S_$strategy"
+
+	abc -D $clock_period \
+		-constr "$sdc_file" \
+		-liberty $sclib  \
+		-script [lindex $all_scripts $strategy] \
+		-showtmp;
+
+	setundef -zero
+
+	hilomap -hicell {*}$::env(SYNTH_TIEHI_PORT) -locell {*}$::env(SYNTH_TIELO_PORT)
+
+	# get rid of the assignments that make verilog2def fail
+	splitnets
+	opt_clean -purge
+	insbuf -buf {*}$::env(SYNTH_MIN_BUF_PORT)
+
+	tee -o "$::env(yosys_report_file_tag)_$strategy$chk_ext" check
+	write_verilog -noattr -noexpr -nohex -nodec -defparam "$::env(SAVE_NETLIST)"
+}
+
+if { $::env(SYNTH_NO_FLAT) } {
+	design -reset
+	file copy -force $::env(SAVE_NETLIST) $::env(yosys_tmp_file_tag)_unflat.v
+	read_verilog -sv $::env(SAVE_NETLIST)
+	synth -top $vtop -flatten
+	splitnets
+	opt_clean -purge
+	insbuf -buf {*}$::env(SYNTH_MIN_BUF_PORT)
+	write_verilog -noattr -noexpr -nohex -nodec -defparam "$::env(SAVE_NETLIST)"
+	tee -o "$::env(yosys_report_file_tag)_$strategy$chk_ext" check
+}
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/common/link_tcm.ld b/verilog/rtl/syntacore/scr1/sim/tests/common/link_tcm.ld
index 7b37506..0612031 100644
--- a/verilog/rtl/syntacore/scr1/sim/tests/common/link_tcm.ld
+++ b/verilog/rtl/syntacore/scr1/sim/tests/common/link_tcm.ld
@@ -9,7 +9,7 @@
 
 MEMORY {
   RAM (rwx) : ORIGIN = 0x0, LENGTH = 64K
-  TCM (rwx) : ORIGIN = 0x00480000, LENGTH = 64K
+  TCM (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
 }
 
 STACK_SIZE = 1024;
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_wb.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_wb.sv
index 85a0c5c..b9e893a 100644
--- a/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_wb.sv
+++ b/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_wb.sv
@@ -21,6 +21,9 @@
 ////              On power up, wishbone output are unkown as it   ////
 ////              driven from fifo output. To avoid unknown       ////
 ////              propgation, we are driving 'h0 when fifo empty  ////
+////     v2:    June 18, 2021, Dinesh A                           ////
+////            core and wishbone is made async and async fifo    ////
+////            added to take care of domain cross-over           ////
 ////                                                              ////
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
@@ -60,8 +63,8 @@
 
 module scr1_dmem_wb (
     // Control Signals
-    input   logic                           rst_n,
-    input   logic                           clk,
+    input   logic                           core_rst_n, // core reset
+    input   logic                           core_clk,   // Core clock
 
     // Core Interface
     output  logic                           dmem_req_ack,
@@ -74,6 +77,8 @@
     output  logic [1:0]                     dmem_resp,
 
     // WB Interface
+    input   logic                           wb_rst_n,   // wishbone reset
+    input   logic                           wb_clk,     // wishbone clock
     output  logic                           wbd_stb_o, // strobe/request
     output  logic   [SCR1_WB_WIDTH-1:0]     wbd_adr_o, // address
     output  logic                           wbd_we_o,  // write
@@ -88,31 +93,19 @@
 //-------------------------------------------------------------------------------
 // Local Parameters
 //-------------------------------------------------------------------------------
-`ifndef SCR1_DMEM_WB_OUT_BP
-localparam  SCR1_FIFO_WIDTH = 2;
-localparam  SCR1_FIFO_CNT_WIDTH = 2;
-`endif // SCR1_DMEM_WB_OUT_BP
 
 //-------------------------------------------------------------------------------
 // Local type declaration
 //-------------------------------------------------------------------------------
-typedef enum logic {
-    SCR1_FSM_ADDR = 1'b0,
-    SCR1_FSM_DATA = 1'b1,
-    SCR1_FSM_ERR  = 1'bx
-} type_scr1_fsm_e;
 
 typedef struct packed {
+    logic [3:0]                     hbel;
     logic                           hwrite;
     logic   [2:0]                   hwidth;
     logic   [SCR1_WB_WIDTH-1:0]     haddr;
     logic   [SCR1_WB_WIDTH-1:0]     hwdata;
 } type_scr1_req_fifo_s;
 
-typedef struct packed {
-    logic   [2:0]                   hwidth;
-    logic   [1:0]                   haddr;
-} type_scr1_data_fifo_s;
 
 typedef struct packed {
     logic                           hresp;
@@ -238,85 +231,18 @@
 //-------------------------------------------------------------------------------
 logic                                       req_fifo_rd;
 logic                                       req_fifo_wr;
-logic                                       req_fifo_up;
-`ifdef SCR1_DMEM_WB_OUT_BP
-type_scr1_req_fifo_s                        req_fifo_new;
-type_scr1_req_fifo_s                        req_fifo_r;
-type_scr1_req_fifo_s [0:0]                  req_fifo;
-`else // SCR1_DMEM_WB_OUT_BP
-type_scr1_req_fifo_s [0:SCR1_FIFO_WIDTH-1]  req_fifo;
-type_scr1_req_fifo_s [0:SCR1_FIFO_WIDTH-1]  req_fifo_new;
-logic       [SCR1_FIFO_CNT_WIDTH-1:0]       req_fifo_cnt;
-logic       [SCR1_FIFO_CNT_WIDTH-1:0]       req_fifo_cnt_new;
-`endif // SCR1_DMEM_WB_OUT_BP
 logic                                       req_fifo_empty;
 logic                                       req_fifo_full;
 
-type_scr1_data_fifo_s                       data_fifo;
-type_scr1_resp_fifo_s                       resp_fifo;
-logic                                       resp_fifo_hready;
+
+logic                                       resp_fifo_rd;
+logic                                       resp_fifo_empty;
+logic                                       resp_fifo_full;
+
 
 //-------------------------------------------------------------------------------
-// Interface to Core
+// REQ_FIFO (CORE to WB)
 //-------------------------------------------------------------------------------
-assign dmem_req_ack = ~req_fifo_full;
-assign req_fifo_wr  = ~req_fifo_full & dmem_req;
-
-assign dmem_rdata = (resp_fifo_hready) ? scr1_conv_wb2mem_rdata(resp_fifo.hwidth, resp_fifo.haddr, resp_fifo.hrdata) : 'h0;
-
-assign dmem_resp = (resp_fifo_hready)
-                    ? (resp_fifo.hresp == 1'b1)
-                        ? SCR1_MEM_RESP_RDY_OK
-                        : SCR1_MEM_RESP_RDY_ER
-                    : SCR1_MEM_RESP_NOTRDY ;
-
-//-------------------------------------------------------------------------------
-// REQ_FIFO
-//-------------------------------------------------------------------------------
-`ifdef SCR1_DMEM_WB_OUT_BP
-always_ff @(negedge rst_n, posedge clk) begin
-    if (~rst_n) begin
-        req_fifo_full <= 1'b0;
-    end else begin
-        if (~req_fifo_full) begin
-            req_fifo_full <= dmem_req & ~req_fifo_rd;
-        end else begin
-            req_fifo_full <= ~req_fifo_rd;
-        end
-    end
-end
-assign req_fifo_empty = ~(req_fifo_full | dmem_req);
-
-assign req_fifo_up = ~req_fifo_rd & req_fifo_wr;
-always_ff @(posedge clk) begin
-    if (req_fifo_up) begin
-        req_fifo_r <= req_fifo_new;
-    end
-end
-
-assign req_fifo_new.hwrite = dmem_req ? (dmem_cmd == SCR1_MEM_CMD_WR)       : 1'b0;
-assign req_fifo_new.hwidth = dmem_req ? scr1_conv_mem2wb_width(dmem_width) : '0;
-assign req_fifo_new.haddr  = dmem_req ? dmem_addr                           : '0;
-assign req_fifo_new.hwdata = (dmem_req & (dmem_cmd == SCR1_MEM_CMD_WR))
-                                ? scr1_conv_mem2wb_wdata(dmem_addr[1:0], dmem_width, dmem_wdata)
-                                : '0;
-assign req_fifo[0] = (req_fifo_full) ? req_fifo_r: req_fifo_new;
-
-//-------------------------------------------------------------------------------
-// Register Data from response path - Used by Read path logic
-//-------------------------------------------------------------------------------
-always_ff @(posedge clk) begin
-    if (wbd_ack_i) begin
-         if (~req_fifo_empty) begin
-             data_fifo.hwidth <= req_fifo[0].hwidth;
-             data_fifo.haddr  <= req_fifo[0].haddr[1:0];
-         end
-    end
-end
-
-`else // SCR1_DMEM_WB_OUT_BP
-
-
 wire	                 hwrite_in = (dmem_cmd == SCR1_MEM_CMD_WR);
 wire [2:0]               hwidth_in = scr1_conv_mem2wb_width(dmem_width);
 wire [SCR1_WB_WIDTH-1:0] haddr_in  = dmem_addr;
@@ -339,47 +265,46 @@
 end
 
 
-wire [SCR1_WB_WIDTH+SCR1_WB_WIDTH+3+4:0] req_fifo_din = {hbel_in,hwrite_in,hwidth_in,haddr_in,hwdata_in};
-wire [SCR1_WB_WIDTH+SCR1_WB_WIDTH+3+4:0] req_fifo_dout;
+//-------------------------------------------------------------------------------
+// REQ_FIFO (WB to CORE)
+//-------------------------------------------------------------------------------
+type_scr1_req_fifo_s    req_fifo_din;
+type_scr1_req_fifo_s    req_fifo_dout;
 
- sync_fifo #(
+
+assign dmem_req_ack        = ~req_fifo_full;
+assign req_fifo_wr         = ~req_fifo_full & dmem_req;
+
+//pack data in
+assign req_fifo_din.hbel   =  hbel_in;
+assign req_fifo_din.hwrite =  hwrite_in;
+assign req_fifo_din.hwidth =  hwidth_in;
+assign req_fifo_din.haddr  =  haddr_in;
+assign req_fifo_din.hwdata =  hwdata_in;
+
+
+ async_fifo #(
       .W(SCR1_WB_WIDTH+SCR1_WB_WIDTH+3+1+4), // Data Width
-      .D(2)    // FIFO DEPTH
+      .DP(4),            // FIFO DEPTH
+      .WR_FAST(1),       // We need FF'ed Full
+      .RD_FAST(1)        // We need FF'ed Empty
      )   u_req_fifo(
+     // Writc Clock
+	.wr_clk      (core_clk       ),
+        .wr_reset_n  (core_rst_n     ),
+        .wr_en       (req_fifo_wr    ),
+        .wr_data     (req_fifo_din   ),
+        .full        (req_fifo_full  ),
+        .afull       (               ),                 
 
-       .rd_data      (req_fifo_dout  ),
-
-       .reset_n   (rst_n          ),
-       .clk       (clk            ),
-       .wr_en     (req_fifo_wr    ), // Write
-       .rd_en     (req_fifo_rd    ), // Read
-       .wr_data   (req_fifo_din   ),
-       .full      (req_fifo_full  ),
-       .empty     (req_fifo_empty )
-);
-
-//-------------------------------------------------------------------------------
-// Register Data from response path - Used by Read path logic
-//-------------------------------------------------------------------------------
-wire	                 hwrite_out;
-wire [2:0]               hwidth_out;
-wire [SCR1_WB_WIDTH-1:0] haddr_out;
-wire [SCR1_WB_WIDTH-1:0] hwdata_out;
-wire [3:0]               hbel_out;
-
-
-assign {hbel_out,hwrite_out,hwidth_out,haddr_out,hwdata_out} = req_fifo_dout;
-
-always_ff @(posedge clk) begin
-    if (wbd_ack_i) begin
-         if (~req_fifo_empty) begin
-             data_fifo.hwidth <= hwidth_out;
-             data_fifo.haddr  <= haddr_out[1:0];
-         end
-    end
-end
-
-`endif // SCR1_DMEM_WB_OUT_BP
+    // RD Clock
+        .rd_clk     (wb_clk          ),
+        .rd_reset_n (wb_rst_n        ),
+        .rd_en      (req_fifo_rd     ),
+        .empty      (req_fifo_empty  ),                
+        .aempty     (                ),                
+        .rd_data    (req_fifo_dout   )
+      );
 
 
 always_comb begin
@@ -390,64 +315,62 @@
 end
 
 
-//-------------------------------------------------------------------------------
-// FIFO response
-//-------------------------------------------------------------------------------
-`ifdef SCR1_DMEM_WB_IN_BP
-
-assign resp_fifo_hready = wbd_ack_i;
-assign resp_fifo.hresp  = (wbd_err_i) ? 1'b0 : 1'b1;
-assign resp_fifo.hwidth = data_fifo.hwidth;
-assign resp_fifo.haddr  = data_fifo.haddr;
-assign resp_fifo.hrdata = wbd_dat_i;
-
-assign wbd_stb_o     = ~req_fifo_empty;
-assign wbd_adr_o    = req_fifo[0].haddr;
-assign wbd_we_o     = req_fifo[0].hwrite;
-assign wbd_dat_o    = req_fifo[0].hwdata;
-
-always_comb begin
-	wbd_sel_o = 0;
-    case (req_fifo[0].hwidth)
-        SCR1_DSIZE_8B : begin
-            wbd_sel_o = 4'b0001 << req_fifo[0].haddr[1:0];
-        end
-        SCR1_DSIZE_16B : begin
-            wbd_sel_o = 4'b0011 << req_fifo[0].haddr[1:0];
-        end
-        SCR1_DSIZE_32B : begin
-            wbd_sel_o = 4'b1111;
-        end
-    endcase
-end
-`else // SCR1_DMEM_WB_IN_BP
-always_ff @(negedge rst_n, posedge clk) begin
-    if (~rst_n) begin
-        resp_fifo_hready <= 1'b0;
-    end else begin
-        resp_fifo_hready <= wbd_ack_i ;
-    end
-end
-
-always_ff @(posedge clk) begin
-    if (wbd_ack_i) begin
-        resp_fifo.hresp  <= (wbd_err_i) ? 1'b0 : 1'b1;
-        resp_fifo.hwidth <= hwidth_out;
-        resp_fifo.haddr  <= haddr_out[1:0];
-        resp_fifo.hrdata <= (wbd_we_o) ? 'h0: wbd_dat_i;
-    end
-end
-
-
 assign wbd_stb_o    = ~req_fifo_empty;
 
 // To avoid unknown progating the design, driven zero when fifo is empty
-assign wbd_adr_o    = (req_fifo_empty) ? 'h0 : haddr_out;
-assign wbd_we_o     = (req_fifo_empty) ? 'h0 : hwrite_out;
-assign wbd_dat_o    = (req_fifo_empty) ? 'h0 : hwdata_out;
-assign wbd_sel_o    = (req_fifo_empty) ? 'h0 : hbel_out;
+assign wbd_adr_o    = (req_fifo_empty) ? 'h0 : req_fifo_dout.haddr;
+assign wbd_we_o     = (req_fifo_empty) ? 'h0 : req_fifo_dout.hwrite;
+assign wbd_dat_o    = (req_fifo_empty) ? 'h0 : req_fifo_dout.hwdata;
+assign wbd_sel_o    = (req_fifo_empty) ? 'h0 : req_fifo_dout.hbel;
 
-`endif // SCR1_DMEM_WB_IN_BP
+
+//-------------------------------------------------------------------------------
+// Response path - Used by Read path logic
+//-------------------------------------------------------------------------------
+type_scr1_resp_fifo_s                       resp_fifo_din;
+type_scr1_resp_fifo_s                       resp_fifo_dout;
+
+
+assign  resp_fifo_din.hresp  = (wbd_err_i) ? 1'b0 : 1'b1;
+assign  resp_fifo_din.hwidth = req_fifo_dout.hwidth;
+assign  resp_fifo_din.haddr  = req_fifo_dout.haddr[1:0];
+assign  resp_fifo_din.hrdata = (wbd_we_o) ? 'h0: wbd_dat_i;
+
+ async_fifo #(
+      .W(SCR1_WB_WIDTH+2+3+1), // Data Width
+      .DP(4),            // FIFO DEPTH
+      .WR_FAST(1),       // We need FF'ed Full
+      .RD_FAST(1)        // We need FF'ed Empty
+     )   u_res_fifo(
+     // Writc Clock
+	.wr_clk      (wb_clk                 ),
+        .wr_reset_n  (wb_rst_n               ),
+        .wr_en       (wbd_ack_i              ),
+        .wr_data     (resp_fifo_din          ),
+        .full        (                       ), // Assmed FIFO will never be full as it's Response a Single Request
+        .afull       (                       ),                 
+
+    // RD Clock
+        .rd_clk     (core_clk                ),
+        .rd_reset_n (core_rst_n              ),
+        .rd_en      (resp_fifo_rd            ),
+        .empty      (resp_fifo_empty         ),                
+        .aempty     (                        ),                
+        .rd_data    (resp_fifo_dout          )
+      );
+
+
+
+assign resp_fifo_rd = !resp_fifo_empty;
+
+assign dmem_rdata = (resp_fifo_rd) ? scr1_conv_wb2mem_rdata(resp_fifo_dout.hwidth, resp_fifo_dout.haddr, resp_fifo_dout.hrdata) : 'h0;
+
+assign dmem_resp = (resp_fifo_rd)
+                    ? (resp_fifo_dout.hresp == 1'b1)
+                        ? SCR1_MEM_RESP_RDY_OK
+                        : SCR1_MEM_RESP_RDY_ER
+                    : SCR1_MEM_RESP_NOTRDY ;
+
 
 
 
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_imem_wb.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_imem_wb.sv
index d91c9e3..fb6c137 100644
--- a/verilog/rtl/syntacore/scr1/src/top/scr1_imem_wb.sv
+++ b/verilog/rtl/syntacore/scr1/src/top/scr1_imem_wb.sv
@@ -21,6 +21,9 @@
 ////              On power up, wishbone output are unkown as it   ////
 ////              driven from fifo output. To avoid unknown       ////
 ////              propgation, we are driving 'h0 when fifo empty  ////
+////     v2:    June 18, 2021, Dinesh A                           ////
+////            core and wishbone is made async and async fifo    ////
+////            added to take care of domain cross-over           ////
 ////                                                              ////
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
@@ -60,8 +63,8 @@
 
 module scr1_imem_wb (
     // Control Signals
-    input   logic                           rst_n,
-    input   logic                           clk,
+    input   logic                           core_rst_n, // core reset
+    input   logic                           core_clk,   // Core clock
 
     // Core Interface
     output  logic                           imem_req_ack,
@@ -71,6 +74,8 @@
     output  logic [1:0]                     imem_resp,
 
     // WB Interface
+    input   logic                           wb_rst_n,   // wishbone reset
+    input   logic                           wb_clk,     // wishbone clock
     output  logic                           wbd_stb_o, // strobe/request
     output  logic   [SCR1_WB_WIDTH-1:0]     wbd_adr_o, // address
     output  logic                           wbd_we_o,  // write
@@ -85,19 +90,10 @@
 //-------------------------------------------------------------------------------
 // Local parameters declaration
 //-------------------------------------------------------------------------------
-`ifndef SCR1_IMEM_WB_OUT_BP
-localparam  SCR1_FIFO_WIDTH = 2;
-localparam  SCR1_FIFO_CNT_WIDTH = $clog2(SCR1_FIFO_WIDTH+1);
-`endif // SCR1_IMEM_WB_OUT_BP
 
 //-------------------------------------------------------------------------------
 // Local types declaration
 //-------------------------------------------------------------------------------
-typedef enum logic {
-    SCR1_FSM_ADDR = 1'b0,
-    SCR1_FSM_DATA = 1'b1,
-    SCR1_FSM_ERR  = 1'bx
-} type_scr1_fsm_e;
 
 typedef struct packed {
     logic   [SCR1_WB_WIDTH-1:0]    haddr;
@@ -111,86 +107,57 @@
 //-------------------------------------------------------------------------------
 // Local signal declaration
 //-------------------------------------------------------------------------------
-type_scr1_fsm_e                             fsm;
+
+//-------------------------------------------------------------------------------
+// Request FIFO
+// ------------------------------------------------------------------------------
 logic                                       req_fifo_rd;
 logic                                       req_fifo_wr;
-logic                                       req_fifo_up;
-`ifdef SCR1_IMEM_WB_OUT_BP
-type_scr1_req_fifo_s                        req_fifo_r;
-type_scr1_req_fifo_s [0:0]                  req_fifo;
-`else // SCR1_IMEM_WB_OUT_BP
-logic [SCR1_WB_WIDTH-1:0]                   req_fifo_dout;
-`endif // SCR1_IMEM_WB_OUT_BP
-
 logic                                       req_fifo_empty;
 logic                                       req_fifo_full;
 
-type_scr1_resp_fifo_s                       resp_fifo;
-logic                                       resp_fifo_hready;
 
-//-------------------------------------------------------------------------------
-// Interface to Core
-//-------------------------------------------------------------------------------
-assign imem_req_ack = ~req_fifo_full;
-assign req_fifo_wr  = ~req_fifo_full & imem_req;
+//-----------------------------------------------------
+// Response FIFO (READ PATH
+// ----------------------------------------------------
+logic                                      resp_fifo_empty;
+logic                                      resp_fifo_rd;
 
-assign imem_rdata = resp_fifo.hrdata;
 
-assign imem_resp = (resp_fifo_hready)
-                    ? (resp_fifo.hresp == 1'b1)
-                        ? SCR1_MEM_RESP_RDY_OK
-                        : SCR1_MEM_RESP_RDY_ER
-                    : SCR1_MEM_RESP_NOTRDY;
 
 //-------------------------------------------------------------------------------
 // REQ_FIFO
 //-------------------------------------------------------------------------------
-`ifdef SCR1_IMEM_WB_OUT_BP
-always_ff @(negedge rst_n, posedge clk) begin
-    if (~rst_n) begin
-        req_fifo_full <= 1'b0;
-    end else begin
-        if (~req_fifo_full) begin
-            req_fifo_full <= imem_req & ~req_fifo_rd;
-        end else begin
-            req_fifo_full <= ~req_fifo_rd;
-        end
-    end
-end
-assign req_fifo_empty = ~(req_fifo_full | imem_req);
+type_scr1_req_fifo_s    req_fifo_din;
+type_scr1_req_fifo_s    req_fifo_dout;
 
-assign req_fifo_up    = ~req_fifo_rd & req_fifo_wr;
-always_ff @(posedge clk) begin
-    if (req_fifo_up) begin
-        req_fifo_r.haddr <= imem_addr;
-    end
-end
+assign req_fifo_wr  = ~req_fifo_full & imem_req;
+assign imem_req_ack = ~req_fifo_full;
 
-assign req_fifo[0] = (req_fifo_full) ? req_fifo_r : imem_addr;
+assign req_fifo_din.haddr = imem_addr;
 
-`else // SCR1_IMEM_WB_OUT_BP
-
-
- sync_fifo #(
+ async_fifo #(
       .W(SCR1_WB_WIDTH), // Data Width
-      .D(2)    // FIFO DEPTH
+      .DP(4),            // FIFO DEPTH
+      .WR_FAST(1),       // We need FF'ed Full
+      .RD_FAST(1)        // We need FF'ed Empty
      )   u_req_fifo(
+     // Writc Clock
+	.wr_clk      (core_clk       ),
+        .wr_reset_n  (core_rst_n     ),
+        .wr_en       (req_fifo_wr    ),
+        .wr_data     (req_fifo_din   ),
+        .full        (req_fifo_full  ),
+        .afull       (               ),                 
 
-       .rd_data    (req_fifo_dout  ),
-
-       .reset_n   (rst_n          ),
-       .clk       (clk            ),
-       .wr_en     (req_fifo_wr    ), // Write
-       .rd_en     (req_fifo_rd    ), // Read
-       .wr_data   (imem_addr      ),
-       .full      (req_fifo_full  ),
-       .empty     (req_fifo_empty )
-);
-
-
-
-
-`endif // SCR1_IMEM_WB_OUT_BP
+    // RD Clock
+        .rd_clk     (wb_clk          ),
+        .rd_reset_n (wb_rst_n        ),
+        .rd_en      (req_fifo_rd     ),
+        .empty      (req_fifo_empty  ),                
+        .aempty     (                ),                
+        .rd_data    (req_fifo_dout   )
+      );
 
 
 always_comb begin
@@ -200,44 +167,53 @@
     end
 end
 
-//-------------------------------------------------------------------------------
-// FIFO response
-//-------------------------------------------------------------------------------
-`ifdef SCR1_IMEM_WB_IN_BP
-assign resp_fifo_hready = wbd_ack_i;
-assign resp_fifo.hresp  = (wbd_err_i) ? 1'b0 : 1'b1;
-assign resp_fifo.hrdata = wbd_dat_i;
-assign wbd_stb_o        = ~req_fifo_empty;
-assign wbd_adr_o        = req_fifo[0];
-assign wbd_we_o         = 0; // Only Read supported
-assign wbd_dat_o        = 32'h0; // No Write
-assign wbd_sel_o        = 4'b1111; // Only Read allowed in imem i/f
-
-
-`else // SCR1_IMEM_WB_IN_BP
-always_ff @(negedge rst_n, posedge clk) begin
-    if (~rst_n) begin
-        resp_fifo_hready <= 1'b0;
-    end else begin
-        resp_fifo_hready <= wbd_ack_i ;
-    end
-end
-
-always_ff @(posedge clk) begin
-    if (wbd_ack_i) begin
-        resp_fifo.hresp  <= (wbd_err_i) ? 1'b0 : 1'b1;
-        resp_fifo.hrdata <= wbd_dat_i;
-    end
-end
-
 assign wbd_stb_o    = ~req_fifo_empty;
 // On Power, to avoid unknow propgating the value
-assign wbd_adr_o    = (req_fifo_empty) ? 'h0 : req_fifo_dout; 
+assign wbd_adr_o    = (req_fifo_empty) ? 'h0 : req_fifo_dout.haddr; 
 assign wbd_we_o     = 0; // Only Read supported
 assign wbd_dat_o    = 32'h0; // No Write
 assign wbd_sel_o    = 4'b1111; // Only Read allowed in imem i/f
-`endif // SCR1_IMEM_WB_IN_BP
+//-------------------------------------------------------------------------------
+// Response path - Used by Read path logic
+//-------------------------------------------------------------------------------
+type_scr1_resp_fifo_s                       resp_fifo_din;
+type_scr1_resp_fifo_s                       resp_fifo_dout;
 
+assign resp_fifo_din.hresp  = (wbd_err_i) ? 1'b0 : 1'b1;
+assign resp_fifo_din.hrdata = wbd_dat_i;
+
+ async_fifo #(
+      .W(SCR1_WB_WIDTH+1), // Data Width
+      .DP(4),            // FIFO DEPTH
+      .WR_FAST(1),       // We need FF'ed Full
+      .RD_FAST(1)        // We need FF'ed Empty
+     )   u_res_fifo(
+     // Writc Clock
+	.wr_clk      (wb_clk                 ),
+        .wr_reset_n  (wb_rst_n               ),
+        .wr_en       (wbd_ack_i              ),
+        .wr_data     (resp_fifo_din          ),
+        .full        (                       ), // Assmed FIFO will never be full as it's Response a Single Request
+        .afull       (                       ),                 
+
+    // RD Clock
+        .rd_clk     (core_clk                ),
+        .rd_reset_n (core_rst_n              ),
+        .rd_en      (resp_fifo_rd            ),
+        .empty      (resp_fifo_empty         ),                
+        .aempty     (                        ),                
+        .rd_data    (resp_fifo_dout          )
+      );
+
+
+assign resp_fifo_rd = !resp_fifo_empty;
+assign imem_rdata   = resp_fifo_dout.hrdata;
+
+assign imem_resp = (resp_fifo_rd)
+                    ? (resp_fifo_dout.hresp == 1'b1)
+                        ? SCR1_MEM_RESP_RDY_OK
+                        : SCR1_MEM_RESP_RDY_ER
+                    : SCR1_MEM_RESP_NOTRDY ;
 
 
 `ifdef SCR1_TRGT_SIMULATION
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv
index 97f565c..d72afd1 100644
--- a/verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv
+++ b/verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv
@@ -17,6 +17,9 @@
 ////  Revision :                                                  ////
 ////     v0:    June 7, 2021, Dinesh A                            ////
 ////             wishbone integration                             ////
+////     v1:    June 17, 2021, Dinesh A                           ////
+////             core and wishbone clock domain are seperated     ////
+////             Async fifo added in imem and dmem path           ////
 ////                                                              ////
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
@@ -69,7 +72,7 @@
     input   logic                                   cpu_rst_n,              // CPU Reset (Core Reset)
     input   logic                                   test_mode,              // Test mode
     input   logic                                   test_rst_n,             // Test mode's reset
-    input   logic                                   clk,                    // System clock
+    input   logic                                   core_clk,               // Core clock
     input   logic                                   rtc_clk,                // Real-time clock
 `ifdef SCR1_DBG_EN
     output  logic                                   sys_rst_n_o,            // External System Reset output
@@ -103,6 +106,8 @@
     output  logic                                   tdo_en,
 `endif // SCR1_DBG_EN
 
+    input   logic                           wb_rst_n,       // Wish bone reset
+    input   logic                           wb_clk,         // wish bone clock
     // Instruction Memory Interface
     output  logic                           wbd_imem_stb_o, // strobe/request
     output  logic   [SCR1_WB_WIDTH-1:0]     wbd_imem_adr_o, // address
@@ -219,7 +224,7 @@
     .STAGES_AMOUNT       (SCR1_CLUSTER_TOP_RST_SYNC_STAGES_NUM)
 ) i_pwrup_rstn_reset_sync (
     .rst_n          (pwrup_rst_n     ),
-    .clk            (clk             ),
+    .clk            (core_clk        ),
     .test_rst_n     (test_rst_n      ),
     .test_mode      (test_mode       ),
     .rst_n_in       (1'b1            ),
@@ -231,7 +236,7 @@
     .STAGES_AMOUNT       (SCR1_CLUSTER_TOP_RST_SYNC_STAGES_NUM)
 ) i_rstn_reset_sync (
     .rst_n          (pwrup_rst_n     ),
-    .clk            (clk             ),
+    .clk            (core_clk        ),
     .test_rst_n     (test_rst_n      ),
     .test_mode      (test_mode       ),
     .rst_n_in       (rst_n           ),
@@ -243,7 +248,7 @@
     .STAGES_AMOUNT       (SCR1_CLUSTER_TOP_RST_SYNC_STAGES_NUM)
 ) i_cpu_rstn_reset_sync (
     .rst_n          (pwrup_rst_n     ),
-    .clk            (clk             ),
+    .clk            (core_clk        ),
     .test_rst_n     (test_rst_n      ),
     .test_mode      (test_mode       ),
     .rst_n_in       (cpu_rst_n       ),
@@ -270,7 +275,7 @@
     .cpu_rst_n                  (cpu_rst_n_sync   ),
     .test_mode                  (test_mode        ),
     .test_rst_n                 (test_rst_n       ),
-    .clk                        (clk              ),
+    .clk                        (core_clk         ),
     .core_rst_n_o               (core_rst_n_local ),
     .core_rdc_qlfy_o            (                 ),
 `ifdef SCR1_DBG_EN
@@ -333,7 +338,7 @@
 scr1_tcm #(
     .SCR1_TCM_SIZE  (`SCR1_DMEM_AWIDTH'(~SCR1_TCM_ADDR_MASK + 1'b1))
 ) i_tcm (
-    .clk            (clk             ),
+    .clk            (core_clk        ),
     .rst_n          (core_rst_n_local),
 
     // Instruction interface to TCM
@@ -362,7 +367,7 @@
 scr1_timer i_timer (
     // Common
     .rst_n          (core_rst_n_local  ),
-    .clk            (clk               ),
+    .clk            (core_clk          ),
     .rtc_clk        (rtc_clk           ),
 
     // Memory interface
@@ -392,7 +397,7 @@
  `endif // SCR1_TCM_EN
 ) i_imem_router (
     .rst_n          (core_rst_n_local ),
-    .clk            (clk              ),
+    .clk            (core_clk         ),
     // Interface to core
     .imem_req_ack   (core_imem_req_ack),
     .imem_req       (core_imem_req    ),
@@ -447,7 +452,7 @@
 
 ) i_dmem_router (
     .rst_n          (core_rst_n_local    ),
-    .clk            (clk                 ),
+    .clk            (core_clk            ),
     // Interface to core
     .dmem_req_ack   (core_dmem_req_ack   ),
     .dmem_req       (core_dmem_req       ),
@@ -502,8 +507,8 @@
 // Instruction memory WB bridge
 //-------------------------------------------------------------------------------
 scr1_imem_wb i_imem_wb (
-    .rst_n          (core_rst_n_local   ),
-    .clk            (clk                ),
+    .core_rst_n     (core_rst_n_local   ),
+    .core_clk       (core_clk           ),
     // Interface to imem router
     .imem_req_ack   (wb_imem_req_ack   ),
     .imem_req       (wb_imem_req       ),
@@ -511,6 +516,8 @@
     .imem_rdata     (wb_imem_rdata     ),
     .imem_resp      (wb_imem_resp      ),
     // WB interface
+    .wb_rst_n       (wb_rst_n          ),
+    .wb_clk         (wb_clk            ),
     .wbd_stb_o      (wbd_imem_stb_o    ), 
     .wbd_adr_o      (wbd_imem_adr_o    ), 
     .wbd_we_o       (wbd_imem_we_o     ),  
@@ -526,8 +533,8 @@
 // Data memory WB bridge
 //-------------------------------------------------------------------------------
 scr1_dmem_wb i_dmem_wb (
-    .rst_n          (core_rst_n_local   ),
-    .clk            (clk                ),
+    .core_rst_n     (core_rst_n_local   ),
+    .core_clk       (core_clk           ),
     // Interface to dmem router
     .dmem_req_ack   (wb_dmem_req_ack   ),
     .dmem_req       (wb_dmem_req       ),
@@ -538,6 +545,8 @@
     .dmem_rdata     (wb_dmem_rdata     ),
     .dmem_resp      (wb_dmem_resp      ),
     // WB interface
+    .wb_rst_n       (wb_rst_n          ),
+    .wb_clk         (wb_clk            ),
     .wbd_stb_o      (wbd_dmem_stb_o    ), 
     .wbd_adr_o      (wbd_dmem_adr_o    ), 
     .wbd_we_o       (wbd_dmem_we_o     ),  
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index b97154e..689eca3 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -46,6 +46,7 @@
      `include "digital_core/src/glbl_cfg.sv"
      `include "digital_core/src/digital_core.sv"
 
+     `include "lib/wb_stagging.sv"
      `include "wb_interconnect/src/wb_arb.sv"
      `include "wb_interconnect/src/wb_interconnect.sv"
 
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 0ff3294..8e7547b 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -95,9 +95,9 @@
 	.vssd2(vssd2),	// User area 2 digital ground
     `endif
 
-    .clk(wb_clk_i),
-    .rst_n(!wb_rst_i),
-    .rtc_clk(user_clock2),
+    .wb_clk_i(wb_clk_i),
+    .wb_rst_i(wb_rst_i),
+    .user_clock2(user_clock2),
 
     // MGMT SoC Wishbone Slave
 
@@ -124,7 +124,7 @@
     .io_oeb(io_oeb),
 
     // IRQ
-    .irq(user_irq)
+    .user_irq(user_irq)
 );
 
 endmodule	// user_project_wrapper
diff --git a/verilog/rtl/wb_interconnect/src/wb_arb.sv b/verilog/rtl/wb_interconnect/src/wb_arb.sv
index b127d5c..a477c94 100644
--- a/verilog/rtl/wb_interconnect/src/wb_arb.sv
+++ b/verilog/rtl/wb_interconnect/src/wb_arb.sv
@@ -107,7 +107,7 @@
          grant2:
       	// if this req is dropped or next is asserted, check for other req's
       	if(!req[2] ) begin
-      	   if(req[0])	next_state = grant0;
+      	   if(req[0])	        next_state = grant0;
       	   else if(req[1])	next_state = grant1;
       	end
       endcase
diff --git a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
index d626b95..3eb688e 100644
--- a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
+++ b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
@@ -17,6 +17,9 @@
 ////                                                              ////
 ////  Revision :                                                  ////
 ////    0.1 - 12th June 2021, Dinesh A                            ////
+////    0.2 - 17th June 2021, Dinesh A                            ////
+////          Stagging FF added at Slave Interface to break       ////
+////          path                                                ////
 ////                                                              ////
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
@@ -58,7 +61,6 @@
          input   logic  	m0_wbd_we_i,
          input   logic  	m0_wbd_cyc_i,
          input   logic  	m0_wbd_stb_i,
-         input   logic [3:0] 	m0_wbd_tid_i, // target id
          output  logic	[31:0]	m0_wbd_dat_o,
          output  logic		m0_wbd_ack_o,
          output  logic		m0_wbd_err_o,
@@ -70,7 +72,6 @@
          input	logic 	        m1_wbd_we_i,
          input	logic 	        m1_wbd_cyc_i,
          input	logic 	        m1_wbd_stb_i,
-         input  logic [3:0] 	m1_wbd_tid_i, // target id
          output	logic [31:0]	m1_wbd_dat_o,
          output	logic 	        m1_wbd_ack_o,
          output	logic 	        m1_wbd_err_o,
@@ -82,7 +83,6 @@
          input	logic 	        m2_wbd_we_i,
          input	logic 	        m2_wbd_cyc_i,
          input	logic 	        m2_wbd_stb_i,
-         input  logic [3:0] 	m2_wbd_tid_i, // target id
          output	logic [31:0]	m2_wbd_dat_o,
          output	logic 	        m2_wbd_ack_o,
          output	logic 	        m2_wbd_err_o,
@@ -115,7 +115,7 @@
          input	logic 	        s2_wbd_ack_i,
          input	logic 	        s2_wbd_err_i,
          output	logic [31:0]	s2_wbd_dat_o,
-         output	logic [31:0]	s2_wbd_adr_o,
+         output	logic [7:0]	s2_wbd_adr_o, // glbl reg need only 8 bits
          output	logic [3:0]	s2_wbd_sel_o,
          output	logic 	        s2_wbd_we_o,
          output	logic 	        s2_wbd_cyc_o,
@@ -168,9 +168,41 @@
 type_wb_rd_intf  s2_wb_rd;
 
 
-type_wb_wr_intf  i_bus_m;  // Multiplexed Master I/F
-type_wb_rd_intf  i_bus_s;  // Multiplexed Slave I/F
+type_wb_wr_intf  m_bus_wr;  // Multiplexed Master I/F
+type_wb_rd_intf  m_bus_rd;  // Multiplexed Slave I/F
 
+type_wb_wr_intf  s_bus_wr;  // Multiplexed Master I/F
+type_wb_rd_intf  s_bus_rd;  // Multiplexed Slave I/F
+//------------------------------
+// RISC Data Memory Map
+// 0x0000_0000 to 0x0FFF_FFFF  - SPI FLASH MEMORY
+// 0x1000_0000 to 0x1000_00FF  - SPI REGISTER
+// 0x2000_0000 to 0x2FFF_FFFF  - SDRAM
+// 0x3000_0000 to 0x3000_00FF  - GLOBAL REGISTER
+//-----------------------------
+// 
+wire [3:0] m0_wbd_tid_i     = (m0_wbd_adr_i[31:28] == 4'b0000 ) ? 4'b0000 :
+                              (m0_wbd_adr_i[31:28] == 4'b0001 ) ? 4'b0000 :
+                              (m0_wbd_adr_i[31:28] == 4'b0010 ) ? 4'b0001 :
+                              (m0_wbd_adr_i[31:28] == 4'b0011 ) ? 4'b0010 : 4'b0000;
+
+wire [3:0] m1_wbd_tid_i     = (m1_wbd_adr_i[31:28] == 4'b0000 ) ? 4'b0000 :
+                              (m1_wbd_adr_i[31:28] == 4'b0001 ) ? 4'b0000 :
+                              (m1_wbd_adr_i[31:28] == 4'b0010 ) ? 4'b0001 : 
+                              (m1_wbd_adr_i[31:28] == 4'b0011 ) ? 4'b0010 : 4'b0000;
+
+
+//-------------------------------------------------------------------
+// EXTERNAL MEMORY MAP
+// 0x3000_0000 to 0x3000_00FF -  GLOBAL REGISTER
+// 0x4000_0000 to 0x4FFF_FFFF -  SPI FLASH MEMORY
+// 0x5000_0000 to 0x5000_00FF -  SPI REGISTER
+// 0x6000_0000 to 0x6FFF_FFFF -  SDRAM
+//
+wire [3:0] m2_wbd_tid_i       = (m2_wbd_adr_i[31:28] == 4'b0100 ) ? 4'b0000 :
+                                (m2_wbd_adr_i[31:28] == 4'b0101 ) ? 4'b0000 :
+                                (m2_wbd_adr_i[31:28] == 4'b0110 ) ? 4'b0001 :
+                                (m2_wbd_adr_i[31:28] == 4'b0011 ) ? 4'b0010 : 4'b0000;
 
 //----------------------------------------
 // Master Mapping
@@ -211,43 +243,43 @@
 assign m2_wbd_ack_o  =  m2_wb_rd.wbd_ack;
 assign m2_wbd_err_o  =  m2_wb_rd.wbd_err;
 
-assign s0_wb_rd.wbd_dat  = s0_wbd_dat_i ;
-assign s0_wb_rd.wbd_ack  = s0_wbd_ack_i ;
-assign s0_wb_rd.wbd_err  = s0_wbd_err_i ;
-
-assign s1_wb_rd.wbd_dat  = s1_wbd_dat_i ;
-assign s1_wb_rd.wbd_ack  = s1_wbd_ack_i ;
-assign s1_wb_rd.wbd_err  = s1_wbd_err_i ;
-
-assign s2_wb_rd.wbd_dat  = s2_wbd_dat_i ;
-assign s2_wb_rd.wbd_ack  = s2_wbd_ack_i ;
-assign s2_wb_rd.wbd_err  = s2_wbd_err_i ;
-
-
 //----------------------------------------
 // Slave Mapping
 // -------------------------------------
+// Masked Now and added stagging FF now
+ assign  s0_wbd_dat_o =  s0_wb_wr.wbd_dat ;
+ assign  s0_wbd_adr_o =  s0_wb_wr.wbd_adr ;
+ assign  s0_wbd_sel_o =  s0_wb_wr.wbd_sel ;
+ assign  s0_wbd_we_o  =  s0_wb_wr.wbd_we  ;
+ assign  s0_wbd_cyc_o =  s0_wb_wr.wbd_cyc ;
+ assign  s0_wbd_stb_o =  s0_wb_wr.wbd_stb ;
+                      
+ assign  s1_wbd_dat_o =  s1_wb_wr.wbd_dat ;
+ assign  s1_wbd_adr_o =  s1_wb_wr.wbd_adr ;
+ assign  s1_wbd_sel_o =  s1_wb_wr.wbd_sel ;
+ assign  s1_wbd_we_o  =  s1_wb_wr.wbd_we  ;
+ assign  s1_wbd_cyc_o =  s1_wb_wr.wbd_cyc ;
+ assign  s1_wbd_stb_o =  s1_wb_wr.wbd_stb ;
+                      
+ assign  s2_wbd_dat_o =  s2_wb_wr.wbd_dat ;
+ assign  s2_wbd_adr_o =  s2_wb_wr.wbd_adr[7:0] ; // Global Reg Need 8 bit
+ assign  s2_wbd_sel_o =  s2_wb_wr.wbd_sel ;
+ assign  s2_wbd_we_o  =  s2_wb_wr.wbd_we  ;
+ assign  s2_wbd_cyc_o =  s2_wb_wr.wbd_cyc ;
+ assign  s2_wbd_stb_o =  s2_wb_wr.wbd_stb ;
+ 
+ assign s0_wb_rd.wbd_dat  = s0_wbd_dat_i ;
+ assign s0_wb_rd.wbd_ack  = s0_wbd_ack_i ;
+ assign s0_wb_rd.wbd_err  = s0_wbd_err_i ;
+ 
+ assign s1_wb_rd.wbd_dat  = s1_wbd_dat_i ;
+ assign s1_wb_rd.wbd_ack  = s1_wbd_ack_i ;
+ assign s1_wb_rd.wbd_err  = s1_wbd_err_i ;
+ 
+ assign s2_wb_rd.wbd_dat  = s2_wbd_dat_i ;
+ assign s2_wb_rd.wbd_ack  = s2_wbd_ack_i ;
+ assign s2_wb_rd.wbd_err  = s2_wbd_err_i ;
 
-assign  s0_wbd_dat_o =  s0_wb_wr.wbd_dat ;
-assign  s0_wbd_adr_o =  s0_wb_wr.wbd_adr ;
-assign  s0_wbd_sel_o =  s0_wb_wr.wbd_sel ;
-assign  s0_wbd_we_o  =  s0_wb_wr.wbd_we  ;
-assign  s0_wbd_cyc_o =  s0_wb_wr.wbd_cyc ;
-assign  s0_wbd_stb_o =  s0_wb_wr.wbd_stb ;
-                     
-assign  s1_wbd_dat_o =  s1_wb_wr.wbd_dat ;
-assign  s1_wbd_adr_o =  s1_wb_wr.wbd_adr ;
-assign  s1_wbd_sel_o =  s1_wb_wr.wbd_sel ;
-assign  s1_wbd_we_o  =  s1_wb_wr.wbd_we  ;
-assign  s1_wbd_cyc_o =  s1_wb_wr.wbd_cyc ;
-assign  s1_wbd_stb_o =  s1_wb_wr.wbd_stb ;
-                     
-assign  s2_wbd_dat_o =  s2_wb_wr.wbd_dat ;
-assign  s2_wbd_adr_o =  s2_wb_wr.wbd_adr ;
-assign  s2_wbd_sel_o =  s2_wb_wr.wbd_sel ;
-assign  s2_wbd_we_o  =  s2_wb_wr.wbd_we  ;
-assign  s2_wbd_cyc_o =  s2_wb_wr.wbd_cyc ;
-assign  s2_wbd_stb_o =  s2_wb_wr.wbd_stb ;
 
 //
 // arbitor 
@@ -257,9 +289,9 @@
 wb_arb	u_wb_arb(
 	.clk(clk_i), 
 	.rstn(rst_n),
-	.req({	m2_wbd_cyc_i,
-		m1_wbd_cyc_i,
-		m0_wbd_cyc_i}),
+	.req({	m2_wbd_stb_i & !m2_wbd_ack_o,
+		m1_wbd_stb_i & !m1_wbd_ack_o,
+		m0_wbd_stb_i & !m0_wbd_ack_o}),
 	.gnt(gnt)
 );
 
@@ -267,37 +299,67 @@
 // Generate Multiplexed Master Interface based on grant
 always_comb begin
      case(gnt)
-        3'h0:	   i_bus_m = m0_wb_wr;
-        3'h1:	   i_bus_m = m1_wb_wr;
-        3'h2:	   i_bus_m = m2_wb_wr;
-        default:   i_bus_m = m0_wb_wr;
+        3'h0:	   m_bus_wr = m0_wb_wr;
+        3'h1:	   m_bus_wr = m1_wb_wr;
+        3'h2:	   m_bus_wr = m2_wb_wr;
+        default:   m_bus_wr = m0_wb_wr;
      endcase			
 end
 
 
 // Generate Multiplexed Slave Interface based on target Id
-wire [3:0] wbd_tid =  i_bus_m.wbd_tid; // to fix iverilog warning
+wire [3:0] s_wbd_tid =  s_bus_wr.wbd_tid; // to fix iverilog warning
 always_comb begin
-     case(wbd_tid)
-        3'h0:	   i_bus_s = s0_wb_rd;
-        3'h1:	   i_bus_s = s1_wb_rd;
-        3'h2:	   i_bus_s = s2_wb_rd;
-        default:   i_bus_s = s0_wb_rd;
+     case(s_wbd_tid)
+        3'h0:	   s_bus_rd = s0_wb_rd;
+        3'h1:	   s_bus_rd = s1_wb_rd;
+        3'h2:	   s_bus_rd = s2_wb_rd;
+        default:   s_bus_rd = s0_wb_rd;
      endcase			
 end
 
 
 // Connect Master => Slave
-assign  s0_wb_wr = (i_bus_m.wbd_tid == 2'b00) ? i_bus_m : 'h0;
-assign  s1_wb_wr = (i_bus_m.wbd_tid == 2'b01) ? i_bus_m : 'h0;
-assign  s2_wb_wr = (i_bus_m.wbd_tid == 2'b10) ? i_bus_m : 'h0;
+assign  s0_wb_wr = (s_wbd_tid == 2'b00) ? s_bus_wr : 'h0;
+assign  s1_wb_wr = (s_wbd_tid == 2'b01) ? s_bus_wr : 'h0;
+assign  s2_wb_wr = (s_wbd_tid == 2'b10) ? s_bus_wr : 'h0;
 
 // Connect Slave to Master
-assign  m0_wb_rd = (gnt == 2'b00) ? i_bus_s : 'h0;
-assign  m1_wb_rd = (gnt == 2'b01) ? i_bus_s : 'h0;
-assign  m2_wb_rd = (gnt == 2'b10) ? i_bus_s : 'h0;
+assign  m0_wb_rd = (gnt == 2'b00) ? m_bus_rd : 'h0;
+assign  m1_wb_rd = (gnt == 2'b01) ? m_bus_rd : 'h0;
+assign  m2_wb_rd = (gnt == 2'b10) ? m_bus_rd : 'h0;
 
 
+// Stagging FF to break write and read timing path
+wb_stagging u_m_wb_stage(
+         .clk_i            (clk_i              ), 
+         .rst_n            (rst_n              ),
+         // WishBone Input master I/P
+         .m_wbd_dat_i      (m_bus_wr.wbd_dat   ),
+         .m_wbd_adr_i      (m_bus_wr.wbd_adr   ),
+         .m_wbd_sel_i      (m_bus_wr.wbd_sel   ),
+         .m_wbd_we_i       (m_bus_wr.wbd_we    ),
+         .m_wbd_cyc_i      (m_bus_wr.wbd_cyc   ),
+         .m_wbd_stb_i      (m_bus_wr.wbd_stb   ),
+         .m_wbd_tid_i      (m_bus_wr.wbd_tid   ),
+         .m_wbd_dat_o      (m_bus_rd.wbd_dat   ),
+         .m_wbd_ack_o      (m_bus_rd.wbd_ack   ),
+         .m_wbd_err_o      (m_bus_rd.wbd_err   ),
+
+         // Slave Interface
+         .s_wbd_dat_i      (s_bus_rd.wbd_dat   ),
+         .s_wbd_ack_i      (s_bus_rd.wbd_ack   ),
+         .s_wbd_err_i      (s_bus_rd.wbd_err   ),
+         .s_wbd_dat_o      (s_bus_wr.wbd_dat    ),
+         .s_wbd_adr_o      (s_bus_wr.wbd_adr    ),
+         .s_wbd_sel_o      (s_bus_wr.wbd_sel    ),
+         .s_wbd_we_o       (s_bus_wr.wbd_we     ),
+         .s_wbd_cyc_o      (s_bus_wr.wbd_cyc    ),
+         .s_wbd_stb_o      (s_bus_wr.wbd_stb    ),
+         .s_wbd_tid_o      (s_bus_wr.wbd_tid    )
+
+);
+
 
 endmodule