diff --git a/openlane/clk_buf/config.tcl b/openlane/clk_buf/config.tcl
deleted file mode 100644
index bf8136d..0000000
--- a/openlane/clk_buf/config.tcl
+++ /dev/null
@@ -1,73 +0,0 @@
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
-
-# Global
-# ------
-
-set script_dir [file dirname [file normalize [info script]]]
-
-set ::env(DESIGN_NAME) clk_buf
-set verilog_root $script_dir/../../verilog/
-set lef_root $script_dir/../../lef/
-set gds_root $script_dir/../../gds/
-#section end
-
-# User Configurations
-#
-set ::env(DESIGN_IS_CORE) 0
-set ::env(FP_PDN_CORE_RING) "0"
-
-
-## Source Verilog Files
-set ::env(VERILOG_FILES) "\
-	$script_dir/../../verilog/rtl/lib/clk_buf.v"
-
-## Clock configurations
-#set ::env(CLOCK_PORT) "clk_in"
-
-#set ::env(CLOCK_PERIOD) "10"
-
-## Internal Macros
-### Macro Placement
-set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
-
-set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 60 100"
-
-
-
-
-set ::env(VDD_PIN) [list {vccd1}]
-set ::env(GND_PIN) [list {vssd1}]
-
-set ::env(SYNTH_READ_BLACKBOX_LIB) 1
-
-# Fill this
-set ::env(CLOCK_TREE_SYNTH) 0
-
-set ::env(CELL_PAD) 4
-
-set ::env(FP_CORE_UTIL) 60
-#set ::env(PL_RANDOM_GLB_PLACEMENT) 1
-
-set ::env(BOTTOM_MARGIN_MULT) 2
-set ::env(TOP_MARGIN_MULT) 2
-set ::env(GLB_RT_MAXLAYER) 4
-
-set ::env(FP_PDN_VPITCH) 30
-set ::env(FP_PDN_HPITCH) 30
-set ::env(FP_PDN_VWIDTH) 3
-set ::env(FP_PDN_HWIDTH) 3
diff --git a/openlane/clk_buf/pin_order.cfg b/openlane/clk_buf/pin_order.cfg
deleted file mode 100644
index 1b25a6f..0000000
--- a/openlane/clk_buf/pin_order.cfg
+++ /dev/null
@@ -1,9 +0,0 @@
-#BUS_SORT
-
-#MANUAL_PLACE
-
-#N
-clk_o              0000 0
-
-#S
-clk_i              0000 0
diff --git a/openlane/glbl_cfg/base.sdc b/openlane/glbl_cfg/base.sdc
deleted file mode 100644
index 92c03ea..0000000
--- a/openlane/glbl_cfg/base.sdc
+++ /dev/null
@@ -1,72 +0,0 @@
-# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
-
-
-set_units -time ns
-set ::env(WB_CLOCK_PERIOD) "10"
-set ::env(WB_CLOCK_PORT) "mclk"
-
-######################################
-# WB Clock domain input output
-######################################
-create_clock [get_ports $::env(WB_CLOCK_PORT)]  -name $::env(WB_CLOCK_PORT)  -period $::env(WB_CLOCK_PERIOD)
-set wb_input_delay_value [expr $::env(WB_CLOCK_PERIOD) * 0.6]
-set wb_output_delay_value [expr $::env(WB_CLOCK_PERIOD) * 0.6]
-puts "\[INFO\]: Setting wb output delay to:$wb_output_delay_value"
-puts "\[INFO\]: Setting wb input delay to: $wb_input_delay_value"
-
-set_clock_uncertainty -from $::env(WB_CLOCK_PORT) -to $::env(WB_CLOCK_PORT)  -setup 0.400
-set_clock_uncertainty -from $::env(WB_CLOCK_PORT) -to $::env(WB_CLOCK_PORT)  -hold  0.050
-
-set_input_delay 2.0 -clock [get_clocks $::env(WB_CLOCK_PORT)] {reset_n}
-
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port reg_cs*]
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port reg_wr*]
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port reg_addr*]
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port reg_wdata*]
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port reg_be*]
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port sdr_init_done*]
-
-set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port reg_rdata*]
-set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port reg_ack*]
-set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port fuse_mhartid*]
-set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port irq_lines*]
-set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port soft_irq*]
-set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port user_irq*]
-set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_width*]
-set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_colbits*]
-set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_tras_d*]
-set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_trp_d*]
-set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_trcd_d*]
-set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_en*]
-set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_req_depth*]
-set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_mode_reg*]
-set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_cas*]
-set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_trcar_d*]
-set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_twr_d*]
-set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_rfsh*]
-set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_cas*]
-set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_trcar_d*]
-set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_twr_d*]
-set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port cfg_sdr_rfsh*]
-
-
-# TODO set this as parameter
-set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
-set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
-puts "\[INFO\]: Setting load to: $cap_load"
-set_load  $cap_load [all_outputs]
-
diff --git a/openlane/glbl_cfg/config.tcl b/openlane/glbl_cfg/config.tcl
deleted file mode 100755
index 0605a4b..0000000
--- a/openlane/glbl_cfg/config.tcl
+++ /dev/null
@@ -1,85 +0,0 @@
-# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
-
-# Global
-# ------
-
-set script_dir [file dirname [file normalize [info script]]]
-# Name
-set ::env(DESIGN_NAME) glbl_cfg
-
-set ::env(DESIGN_IS_CORE) "0"
-set ::env(FP_PDN_CORE_RING) "0"
-
-# Timing configuration
-set ::env(CLOCK_PERIOD) "10"
-set ::env(CLOCK_PORT) "mclk"
-
-set ::env(SYNTH_MAX_FANOUT) 4
-
-# Sources
-# -------
-
-# Local sources + no2usb sources
-set ::env(VERILOG_FILES) "\
-        $script_dir/../../verilog/rtl/lib/registers.v                  \
-        $script_dir/../../verilog/rtl/lib/clk_ctl.v                    \
-        $script_dir/../../verilog/rtl/digital_core/src/glbl_cfg.sv     \
-	"
-
-set ::env(SDC_FILE) "$script_dir/base.sdc"
-set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
-
-set ::env(LEC_ENABLE) 0
-
-set ::env(VDD_PIN) [list {vccd1}]
-set ::env(GND_PIN) [list {vssd1}]
-
-
-
-# Floorplanning
-# -------------
-
-set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
-
-set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 300 400"
-
-
-# If you're going to use multiple power domains, then keep this disabled.
-set ::env(RUN_CVC) 0
-
-#set ::env(PDN_CFG) $script_dir/pdn.tcl
-
-
-set ::env(PL_ROUTABILITY_DRIVEN) 1
-
-set ::env(FP_IO_VEXTEND) 4
-set ::env(FP_IO_HEXTEND) 4
-
-# helps in anteena fix
-set ::env(USE_ARC_ANTENNA_CHECK) "0"
-
-
-set ::env(GLB_RT_MAXLAYER) 4
-set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
-
-set ::env(DIODE_INSERTION_STRATEGY) 5
-
-set ::env(FP_PDN_VPITCH) 100
-set ::env(FP_PDN_HPITCH) 100
-set ::env(FP_PDN_VWIDTH) 5
-set ::env(FP_PDN_HWIDTH) 5
diff --git a/openlane/glbl_cfg/pdn.tcl b/openlane/glbl_cfg/pdn.tcl
deleted file mode 100644
index 1fe689b..0000000
--- a/openlane/glbl_cfg/pdn.tcl
+++ /dev/null
@@ -1,49 +0,0 @@
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-
-# Power nets
-set ::power_nets $::env(VDD_PIN)
-set ::ground_nets $::env(GND_PIN)
-
-set ::macro_blockage_layer_list "li1 met1 met2 met3 met4 met5"
-
-pdngen::specify_grid stdcell {
-    name grid
-    rails {
-	    met1 {width 0.48 pitch $::env(PLACE_SITE_HEIGHT) offset 0}
-    }
-    straps {
-	    met4 {width 1.6 pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)}
-	    met5 {width 1.6 pitch $::env(FP_PDN_HPITCH) offset $::env(FP_PDN_HOFFSET)}
-    }
-    connect {{met1 met4} {met4 met5}}
-}
-
-pdngen::specify_grid macro {
-    power_pins "VPWR"
-    ground_pins "VGND"
-    blockages "li1 met1 met2 met3 met4"
-    straps { 
-    } 
-    connect {{met4_PIN_ver met5}}
-}
-
-set ::halo 5
-
-# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
-set ::rails_start_with "POWER" ;
-
-# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
-set ::stripes_start_with "POWER" ;
diff --git a/openlane/glbl_cfg/pin_order.cfg b/openlane/glbl_cfg/pin_order.cfg
deleted file mode 100644
index f111f5a..0000000
--- a/openlane/glbl_cfg/pin_order.cfg
+++ /dev/null
@@ -1,204 +0,0 @@
-#BUS_SORT
-
-#MANUAL_PLACE
-
-#N
-reset_n               0000 0        
-user_irq\[2\]          
-user_irq\[1\]          
-user_irq\[0\]          
-
-#W
-sdr_init_done          0000 0
-cfg_sdr_width\[1]      
-cfg_sdr_width\[0]      
-cfg_colbits\[1\]       
-cfg_colbits\[0\]       
-cfg_sdr_tras_d\[3\]    
-cfg_sdr_tras_d\[2\]    
-cfg_sdr_tras_d\[1\]    
-cfg_sdr_tras_d\[0\]    
-cfg_sdr_trp_d\[3\]     
-cfg_sdr_trp_d\[2\]     
-cfg_sdr_trp_d\[1\]     
-cfg_sdr_trp_d\[0\]     
-cfg_sdr_trcd_d\[3\]    
-cfg_sdr_trcd_d\[2\]    
-cfg_sdr_trcd_d\[1\]    
-cfg_sdr_trcd_d\[0\]    
-cfg_sdr_en             
-cfg_req_depth\[1\]     
-cfg_req_depth\[0\]     
-cfg_sdr_mode_reg\[12\] 
-cfg_sdr_mode_reg\[11\] 
-cfg_sdr_mode_reg\[10\] 
-cfg_sdr_mode_reg\[9\] 
-cfg_sdr_mode_reg\[8\] 
-cfg_sdr_mode_reg\[7\] 
-cfg_sdr_mode_reg\[6\] 
-cfg_sdr_mode_reg\[5\] 
-cfg_sdr_mode_reg\[4\] 
-cfg_sdr_mode_reg\[3\] 
-cfg_sdr_mode_reg\[2\] 
-cfg_sdr_mode_reg\[1\] 
-cfg_sdr_mode_reg\[0\] 
-cfg_sdr_cas\[2\]      
-cfg_sdr_cas\[1\]      
-cfg_sdr_cas\[0\]      
-cfg_sdr_trcar_d\[3\]  
-cfg_sdr_trcar_d\[2\]  
-cfg_sdr_trcar_d\[1\]  
-cfg_sdr_trcar_d\[0\]  
-cfg_sdr_twr_d\[3\]    
-cfg_sdr_twr_d\[2\]    
-cfg_sdr_twr_d\[1\]    
-cfg_sdr_twr_d\[0\]    
-cfg_sdr_rfsh\[11\]    
-cfg_sdr_rfsh\[10\]    
-cfg_sdr_rfsh\[9\]    
-cfg_sdr_rfsh\[8\]    
-cfg_sdr_rfsh\[7\]    
-cfg_sdr_rfsh\[6\]    
-cfg_sdr_rfsh\[5\]    
-cfg_sdr_rfsh\[4\]    
-cfg_sdr_rfsh\[3\]    
-cfg_sdr_rfsh\[2\]    
-cfg_sdr_rfsh\[1\]    
-cfg_sdr_rfsh\[0\]    
-cfg_sdr_rfmax\[2\]   
-cfg_sdr_rfmax\[1\]   
-cfg_sdr_rfmax\[0\]   
-mclk                   0150 0
-
-#S
-reg_cs               0000 0
-reg_wr               
-reg_addr\[7\]        
-reg_addr\[6\]        
-reg_addr\[5\]        
-reg_addr\[4\]        
-reg_addr\[3\]        
-reg_addr\[2\]        
-reg_addr\[1\]        
-reg_addr\[0\]        
-reg_be\[3\]          
-reg_be\[2\]          
-reg_be\[1\]          
-reg_be\[0\]          
-reg_wdata\[31\]      
-reg_wdata\[30\]      
-reg_wdata\[29\]      
-reg_wdata\[28\]      
-reg_wdata\[27\]      
-reg_wdata\[26\]      
-reg_wdata\[25\]      
-reg_wdata\[24\]      
-reg_wdata\[23\]      
-reg_wdata\[22\]      
-reg_wdata\[21\]      
-reg_wdata\[20\]      
-reg_wdata\[19\]      
-reg_wdata\[18\]      
-reg_wdata\[17\]      
-reg_wdata\[16\]      
-reg_wdata\[15\]      
-reg_wdata\[14\]      
-reg_wdata\[13\]      
-reg_wdata\[12\]      
-reg_wdata\[11\]      
-reg_wdata\[10\]      
-reg_wdata\[9\]      
-reg_wdata\[8\]      
-reg_wdata\[7\]      
-reg_wdata\[6\]      
-reg_wdata\[5\]      
-reg_wdata\[4\]      
-reg_wdata\[3\]      
-reg_wdata\[2\]      
-reg_wdata\[1\]      
-reg_wdata\[0\]      
-reg_rdata\[31\]     
-reg_rdata\[30\]     
-reg_rdata\[29\]     
-reg_rdata\[28\]     
-reg_rdata\[27\]     
-reg_rdata\[26\]     
-reg_rdata\[25\]     
-reg_rdata\[24\]     
-reg_rdata\[23\]     
-reg_rdata\[22\]     
-reg_rdata\[21\]     
-reg_rdata\[20\]     
-reg_rdata\[19\]     
-reg_rdata\[18\]     
-reg_rdata\[17\]     
-reg_rdata\[16\]     
-reg_rdata\[15\]     
-reg_rdata\[14\]     
-reg_rdata\[13\]     
-reg_rdata\[12\]     
-reg_rdata\[11\]     
-reg_rdata\[10\]     
-reg_rdata\[9\]      
-reg_rdata\[8\]      
-reg_rdata\[7\]      
-reg_rdata\[6\]      
-reg_rdata\[5\]      
-reg_rdata\[4\]      
-reg_rdata\[3\]      
-reg_rdata\[2\]      
-reg_rdata\[1\]      
-reg_rdata\[0\]      
-reg_ack             
-
-
-irq_lines\[15\]    200 0 2    
-irq_lines\[14\]        
-irq_lines\[13\]        
-irq_lines\[12\]        
-irq_lines\[11\]        
-irq_lines\[10\]        
-irq_lines\[9\]         
-irq_lines\[8\]         
-irq_lines\[7\]         
-irq_lines\[6\]         
-irq_lines\[5\]         
-irq_lines\[4\]         
-irq_lines\[3\]         
-irq_lines\[2\]         
-irq_lines\[1\]         
-irq_lines\[0\]         
-soft_irq               
-fuse_mhartid\[31\]     
-fuse_mhartid\[30\]     
-fuse_mhartid\[29\]     
-fuse_mhartid\[28\]     
-fuse_mhartid\[27\]     
-fuse_mhartid\[26\]     
-fuse_mhartid\[25\]     
-fuse_mhartid\[24\]     
-fuse_mhartid\[23\]     
-fuse_mhartid\[22\]     
-fuse_mhartid\[21\]     
-fuse_mhartid\[20\]     
-fuse_mhartid\[19\]     
-fuse_mhartid\[18\]     
-fuse_mhartid\[17\]     
-fuse_mhartid\[16\]     
-fuse_mhartid\[15\]     
-fuse_mhartid\[14\]     
-fuse_mhartid\[13\]     
-fuse_mhartid\[12\]     
-fuse_mhartid\[11\]     
-fuse_mhartid\[10\]     
-fuse_mhartid\[9\]      
-fuse_mhartid\[8\]      
-fuse_mhartid\[7\]      
-fuse_mhartid\[6\]      
-fuse_mhartid\[5\]      
-fuse_mhartid\[4\]      
-fuse_mhartid\[3\]      
-fuse_mhartid\[2\]      
-fuse_mhartid\[1\]      
-fuse_mhartid\[0\]      
-
diff --git a/openlane/pinmux/config.tcl b/openlane/pinmux/config.tcl
index 692bbaf..0cb3217 100755
--- a/openlane/pinmux/config.tcl
+++ b/openlane/pinmux/config.tcl
@@ -36,6 +36,7 @@
 
 # Local sources + no2usb sources
 set ::env(VERILOG_FILES) "\
+     $script_dir/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \
      $script_dir/../../verilog/rtl/pinmux/src/pinmux.sv \
      $script_dir/../../verilog/rtl/pinmux/src/pinmux_reg.sv \
      $script_dir/../../verilog/rtl/pinmux/src/gpio_intr.sv \
diff --git a/openlane/pinmux/pin_order.cfg b/openlane/pinmux/pin_order.cfg
index c502b5a..5e95fb1 100644
--- a/openlane/pinmux/pin_order.cfg
+++ b/openlane/pinmux/pin_order.cfg
@@ -2,75 +2,14 @@
 #MANUAL_PLACE
 
 #N
+wbd_clk_int             0000 0  4
+cfg_cska_pinmux\[3\]
+cfg_cska_pinmux\[2\]
+cfg_cska_pinmux\[1\]
+cfg_cska_pinmux\[0\]
+wbd_clk_pinmux
 mclk            
 h_reset_n             
-irq_lines\[15\]     
-irq_lines\[14\]     
-irq_lines\[13\]     
-irq_lines\[12\]     
-irq_lines\[11\]     
-irq_lines\[10\]     
-irq_lines\[9\]     
-irq_lines\[8\]     
-irq_lines\[7\]     
-irq_lines\[6\]     
-irq_lines\[5\]     
-irq_lines\[4\]     
-irq_lines\[3\]     
-irq_lines\[2\]     
-irq_lines\[1\]     
-irq_lines\[0\]     
-user_irq\[2\]
-user_irq\[1\]
-user_irq\[0\]
-soft_irq           
-fuse_mhartid\[31\] 
-fuse_mhartid\[30\] 
-fuse_mhartid\[29\] 
-fuse_mhartid\[28\] 
-fuse_mhartid\[27\] 
-fuse_mhartid\[26\] 
-fuse_mhartid\[25\] 
-fuse_mhartid\[24\] 
-fuse_mhartid\[23\] 
-fuse_mhartid\[22\] 
-fuse_mhartid\[21\] 
-fuse_mhartid\[20\] 
-fuse_mhartid\[19\] 
-fuse_mhartid\[18\] 
-fuse_mhartid\[17\] 
-fuse_mhartid\[16\] 
-fuse_mhartid\[15\] 
-fuse_mhartid\[14\] 
-fuse_mhartid\[13\] 
-fuse_mhartid\[12\] 
-fuse_mhartid\[11\] 
-fuse_mhartid\[10\] 
-fuse_mhartid\[9\] 
-fuse_mhartid\[8\] 
-fuse_mhartid\[7\] 
-fuse_mhartid\[6\] 
-fuse_mhartid\[5\] 
-fuse_mhartid\[4\] 
-fuse_mhartid\[3\] 
-fuse_mhartid\[2\] 
-fuse_mhartid\[1\] 
-fuse_mhartid\[0\] 
-
-ssram_sck
-ssram_ss
-ssram_oen\[3\]
-ssram_oen\[2\]
-ssram_oen\[1\]
-ssram_oen\[0\]
-ssram_do\[3\]
-ssram_do\[2\]
-ssram_do\[1\]
-ssram_do\[0\]
-ssram_di\[3\] 
-ssram_di\[2\] 
-ssram_di\[1\] 
-ssram_di\[0\] 
 
 usb_dp_o 
 usb_dn_o 
@@ -284,63 +223,118 @@
 digital_io_out\[14\]
 digital_io_oen\[14\]
 
-#WR
-digital_io_in\[24\]
-digital_io_out\[24\]
-digital_io_oen\[24\]
-digital_io_in\[25\]
-digital_io_out\[25\]
-digital_io_oen\[25\]
-digital_io_in\[26\]
-digital_io_out\[26\]
-digital_io_oen\[26\]
-digital_io_in\[27\]
-digital_io_out\[27\]
-digital_io_oen\[27\]
-digital_io_in\[28\]
-digital_io_out\[28\]
-digital_io_oen\[28\]
-digital_io_in\[29\]
-digital_io_out\[29\]
-digital_io_oen\[29\]
-digital_io_in\[30\]
-digital_io_out\[30\]
-digital_io_oen\[30\]
-digital_io_in\[31\]
-digital_io_out\[31\]
-digital_io_oen\[31\]
-digital_io_in\[32\]
-digital_io_out\[32\]
-digital_io_oen\[32\]
-digital_io_in\[33\]
-digital_io_out\[33\]
-digital_io_oen\[33\]
-digital_io_in\[34\]
-digital_io_out\[34\]
-digital_io_oen\[34\]
-digital_io_in\[35\]
-digital_io_out\[35\]
-digital_io_oen\[35\]
-digital_io_in\[36\]
-digital_io_out\[36\]
-digital_io_oen\[36\]
-digital_io_in\[37\]
-digital_io_out\[37\]
-digital_io_oen\[37\]
-
 #W
-sflash_di\[3\] 0200 0
-sflash_di\[2\]
-sflash_di\[1\]
-sflash_di\[0\]
-sflash_do\[3\]
-sflash_do\[2\]
-sflash_do\[1\]
-sflash_do\[0\]
-sflash_sck   
-sflash_ss
-sflash_oen\[3\]
-sflash_oen\[2\]
+digital_io_oen\[37\]  000 0 2
+digital_io_out\[37\]
+digital_io_in\[37\]
+digital_io_oen\[36\]
+digital_io_out\[36\]
+digital_io_in\[36\]
+digital_io_oen\[35\]
+digital_io_out\[35\]
+digital_io_in\[35\]
+digital_io_oen\[34\]
+digital_io_out\[34\]
+digital_io_in\[34\]
+digital_io_oen\[33\]
+digital_io_out\[33\]
+digital_io_in\[33\]
+digital_io_oen\[32\]
+digital_io_out\[32\]
+digital_io_in\[32\]
+digital_io_oen\[31\]
+digital_io_out\[31\]
+digital_io_in\[31\]
+digital_io_oen\[30\]
+digital_io_out\[30\]
+digital_io_in\[30\]
+digital_io_oen\[29\]
+digital_io_out\[29\]
+digital_io_in\[29\]
+digital_io_oen\[28\]
+digital_io_out\[28\]
+
+irq_lines\[15\]     200 0 2
+irq_lines\[14\]     
+irq_lines\[13\]     
+irq_lines\[12\]     
+irq_lines\[11\]     
+irq_lines\[10\]     
+irq_lines\[9\]     
+irq_lines\[8\]     
+irq_lines\[7\]     
+irq_lines\[6\]     
+irq_lines\[5\]     
+irq_lines\[4\]     
+irq_lines\[3\]     
+irq_lines\[2\]     
+irq_lines\[1\]     
+irq_lines\[0\]     
+soft_irq           
+fuse_mhartid\[31\] 
+fuse_mhartid\[30\] 
+fuse_mhartid\[29\] 
+fuse_mhartid\[28\] 
+fuse_mhartid\[27\] 
+fuse_mhartid\[26\] 
+fuse_mhartid\[25\] 
+fuse_mhartid\[24\] 
+fuse_mhartid\[23\] 
+fuse_mhartid\[22\] 
+fuse_mhartid\[21\] 
+fuse_mhartid\[20\] 
+fuse_mhartid\[19\] 
+fuse_mhartid\[18\] 
+fuse_mhartid\[17\] 
+fuse_mhartid\[16\] 
+fuse_mhartid\[15\] 
+fuse_mhartid\[14\] 
+fuse_mhartid\[13\] 
+fuse_mhartid\[12\] 
+fuse_mhartid\[11\] 
+fuse_mhartid\[10\] 
+fuse_mhartid\[9\] 
+fuse_mhartid\[8\] 
+fuse_mhartid\[7\] 
+fuse_mhartid\[6\] 
+fuse_mhartid\[5\] 
+fuse_mhartid\[4\] 
+fuse_mhartid\[3\] 
+fuse_mhartid\[2\] 
+fuse_mhartid\[1\] 
+fuse_mhartid\[0\] 
+
+user_irq\[0\]
+user_irq\[1\]
+user_irq\[2\]
+
+
+digital_io_in\[28\]  0300 0 2
+digital_io_oen\[27\]
+digital_io_out\[27\]
+digital_io_in\[27\]
+digital_io_oen\[26\]
+digital_io_out\[26\]
+digital_io_in\[26\]
+digital_io_oen\[25\]
+digital_io_out\[25\]
+digital_io_in\[25\]
+digital_io_oen\[24\]
+digital_io_out\[24\]
+digital_io_in\[24\]
+
+sflash_oen\[0\]    400 0 2
 sflash_oen\[1\]
-sflash_oen\[0\]
+sflash_oen\[2\]
+sflash_oen\[3\]
+sflash_ss
+sflash_sck   
+sflash_do\[0\]
+sflash_do\[1\]
+sflash_do\[2\]
+sflash_do\[3\]
+sflash_di\[0\]      
+sflash_di\[1\]      
+sflash_di\[2\]      
+sflash_di\[3\]      
 
diff --git a/openlane/qspim/base.sdc b/openlane/qspim/base.sdc
index 35f2f48..ef37d62 100644
--- a/openlane/qspim/base.sdc
+++ b/openlane/qspim/base.sdc
@@ -1,93 +1,351 @@
-# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
-
-
-set_units -time ns
-set ::env(WB_CLOCK_PERIOD) "10"
-set ::env(WB_CLOCK_PORT) "mclk"
-
-set ::env(SPI_CLOCK_PORT)  "spiclk"
-set ::env(SPI_CLOCK_PERIOD) "20"
-
-######################################
-# WB Clock domain input output
-######################################
-create_clock [get_ports $::env(WB_CLOCK_PORT)]  -name $::env(WB_CLOCK_PORT)  -period $::env(WB_CLOCK_PERIOD)
-
-create_generated_clock -name $::env(SPI_CLOCK_PORT) -source [get_ports $::env(WB_CLOCK_PORT)] -master_clock $::env(WB_CLOCK_PORT) -divide_by 2  -add -comment "SPI Clock Out"  [get_port spi_clk]
-
-set wb_input_delay_value [expr $::env(WB_CLOCK_PERIOD) * 0.6]
-set wb_output_delay_value [expr $::env(WB_CLOCK_PERIOD) * 0.6]
-puts "\[INFO\]: Setting wb output delay to:$wb_output_delay_value"
-puts "\[INFO\]: Setting wb input delay to: $wb_input_delay_value"
-
-
-set_input_delay 2.0 -clock [get_clocks $::env(WB_CLOCK_PORT)] {rst_n}
-
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbd_stb_i*]
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbd_adr_i*]
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbd_we_i*]
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbd_dat_i*]
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbd_sel_i*]
-
-
-set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbd_dat_o*]
-set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbd_ack_o*]
-set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port wbd_err_o*]
-set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_PORT)] [get_port spi_debug*]
-
-### SPI I/F constaints
-set spi_input_delay_value  [expr $::env(SPI_CLOCK_PERIOD) * 0.6]
-set spi_output_delay_value [expr $::env(SPI_CLOCK_PERIOD) * 0.6]
-
-set_input_delay  6   -max -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port spi_sdi[3]]
-set_input_delay  6   -max -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port spi_sdi[2]]
-set_input_delay  6   -max -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port spi_sdi[1]]
-set_input_delay  6   -max -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port spi_sdi[0]]
-
-set_input_delay  0   -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port spi_sdi[3]]
-set_input_delay  0   -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port spi_sdi[2]]
-set_input_delay  0   -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port spi_sdi[1]]
-set_input_delay  0   -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port spi_sdi[0]]
-
-#io_out[0] is spiclcok
-#set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_out[0]]
-set_output_delay 6  -max -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port spi_csn0]
-set_output_delay 6  -max -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port spi_sdo[3]]
-set_output_delay 6  -max -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port spi_sdo[2]]
-set_output_delay 6  -max -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port spi_sdo[1]]
-
-
-set_output_delay -0.5   -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port spi_csn0]
-set_output_delay -0.5   -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port spi_sdo[3]]
-set_output_delay -0.5   -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port spi_sdo[2]]
-set_output_delay -0.5   -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port spi_sdo[1]]
-set_output_delay -0.5   -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port spi_sdo[0]]
-
-# Chip select asserted multiple cycle eariler than spi clock
-set_output_delay 0   -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port spi_csn0]
-
-
-set_clock_uncertainty -from $::env(SPI_CLOCK_PORT) -to $::env(SPI_CLOCK_PORT) -setup 0.800
-set_clock_uncertainty -from $::env(WB_CLOCK_PORT)  -to $::env(WB_CLOCK_PORT)  -setup 0.800
-set_clock_uncertainty -from $::env(SPI_CLOCK_PORT) -to $::env(SPI_CLOCK_PORT) -hold  0.050
-set_clock_uncertainty -from $::env(WB_CLOCK_PORT)  -to $::env(WB_CLOCK_PORT)  -hold  0.050
-
-# TODO set this as parameter
-set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
-set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
-puts "\[INFO\]: Setting load to: $cap_load"
-set_load  $cap_load [all_outputs]
+###############################################################################
+# Created by write_sdc
+# Sat Nov  6 13:48:28 2021
+###############################################################################
+current_design qspim_top
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name mclk -period 10.0000 [get_ports {mclk}]
+set_propagated_clock [get_clocks {mclk}]
+create_generated_clock -name spiclk -add -source [get_ports {mclk}] -master_clock [get_clocks {mclk}] -divide_by 2 -comment {SPI Clock Out} [get_ports {spi_clk}]
+set_propagated_clock [get_clocks {spiclk}]
+set_clock_uncertainty -rise_from [get_clocks {mclk}] -rise_to [get_clocks {mclk}]      -hold  0.1000
+set_clock_uncertainty -rise_from [get_clocks {mclk}] -rise_to [get_clocks {mclk}]      -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {mclk}] -fall_to [get_clocks {mclk}]      -hold  0.1000
+set_clock_uncertainty -rise_from [get_clocks {mclk}] -fall_to [get_clocks {mclk}]      -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {mclk}] -rise_to [get_clocks {mclk}]      -hold  0.1000
+set_clock_uncertainty -fall_from [get_clocks {mclk}] -rise_to [get_clocks {mclk}]      -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {mclk}] -fall_to [get_clocks {mclk}]      -hold  0.1000
+set_clock_uncertainty -fall_from [get_clocks {mclk}] -fall_to [get_clocks {mclk}]      -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {spiclk}] -rise_to [get_clocks {spiclk}]  -hold  0.1000
+set_clock_uncertainty -rise_from [get_clocks {spiclk}] -rise_to [get_clocks {spiclk}]  -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {spiclk}] -fall_to [get_clocks {spiclk}]  -hold  0.1000
+set_clock_uncertainty -rise_from [get_clocks {spiclk}] -fall_to [get_clocks {spiclk}]  -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {spiclk}] -rise_to [get_clocks {spiclk}]  -hold  0.1000
+set_clock_uncertainty -fall_from [get_clocks {spiclk}] -rise_to [get_clocks {spiclk}]  -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {spiclk}] -fall_to [get_clocks {spiclk}]  -hold  0.1000
+set_clock_uncertainty -fall_from [get_clocks {spiclk}] -fall_to [get_clocks {spiclk}]  -setup 0.2000
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {rst_n}]
+set_input_delay 0.0000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_sdi[0]}]
+set_input_delay 6.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_sdi[0]}]
+set_input_delay 0.0000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_sdi[1]}]
+set_input_delay 6.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_sdi[1]}]
+set_input_delay 0.0000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_sdi[2]}]
+set_input_delay 6.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_sdi[2]}]
+set_input_delay 0.0000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_sdi[3]}]
+set_input_delay 6.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_sdi[3]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[0]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[10]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[11]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[12]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[13]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[14]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[15]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[16]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[17]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[18]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[19]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[1]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[20]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[21]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[22]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[23]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[24]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[25]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[26]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[27]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[28]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[29]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[2]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[30]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[31]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[3]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[4]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[5]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[6]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[7]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[8]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[9]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[0]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[10]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[11]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[12]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[13]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[14]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[15]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[16]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[17]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[18]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[19]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[1]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[20]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[21]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[22]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[23]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[24]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[25]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[26]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[27]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[28]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[29]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[2]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[30]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[31]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[3]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[4]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[5]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[6]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[7]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[8]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[9]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_sel_i[0]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_sel_i[1]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_sel_i[2]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_sel_i[3]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_stb_i}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_we_i}]
+set_output_delay 0.0000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_csn0}]
+set_output_delay 6.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_csn0}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[0]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[10]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[11]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[12]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[13]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[14]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[15]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[16]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[17]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[18]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[19]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[1]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[20]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[21]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[22]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[23]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[24]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[25]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[26]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[27]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[28]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[29]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[2]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[30]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[31]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[3]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[4]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[5]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[6]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[7]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[8]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[9]}]
+set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_sdo[0]}]
+set_output_delay 6.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_sdo[0]}]
+set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_sdo[1]}]
+set_output_delay 6.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_sdo[1]}]
+set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_sdo[2]}]
+set_output_delay 6.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_sdo[2]}]
+set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_sdo[3]}]
+set_output_delay 6.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_sdo[3]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_ack_o}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[0]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[10]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[11]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[12]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[13]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[14]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[15]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[16]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[17]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[18]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[19]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[1]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[20]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[21]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[22]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[23]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[24]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[25]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[26]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[27]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[28]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[29]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[2]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[30]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[31]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[3]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[4]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[5]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[6]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[7]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[8]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[9]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_err_o}]
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {spi_clk}]
+set_load -pin_load 0.0334 [get_ports {spi_csn0}]
+set_load -pin_load 0.0334 [get_ports {wbd_ack_o}]
+set_load -pin_load 0.0334 [get_ports {wbd_clk_spi}]
+set_load -pin_load 0.0334 [get_ports {wbd_err_o}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[31]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[30]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[29]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[28]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[27]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[26]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[25]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[24]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[23]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[22]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[21]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[20]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[19]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[18]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[17]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[16]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[15]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[14]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[13]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[12]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[11]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[10]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[9]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[8]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[7]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[6]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[5]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[4]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[3]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[2]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[1]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[0]}]
+set_load -pin_load 0.0334 [get_ports {spi_oen[3]}]
+set_load -pin_load 0.0334 [get_ports {spi_oen[2]}]
+set_load -pin_load 0.0334 [get_ports {spi_oen[1]}]
+set_load -pin_load 0.0334 [get_ports {spi_oen[0]}]
+set_load -pin_load 0.0334 [get_ports {spi_sdo[3]}]
+set_load -pin_load 0.0334 [get_ports {spi_sdo[2]}]
+set_load -pin_load 0.0334 [get_ports {spi_sdo[1]}]
+set_load -pin_load 0.0334 [get_ports {spi_sdo[0]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[31]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[30]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[29]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[28]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[27]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[26]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[25]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[24]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[23]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[22]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[21]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[20]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[19]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[18]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[17]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[16]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[15]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[14]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[13]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[12]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[11]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[10]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[9]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[8]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[7]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[6]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[5]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[4]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[3]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[2]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[1]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mclk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rst_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_stb_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_we_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_sp_co[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_sp_co[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_sp_co[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_sp_co[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_spi[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_spi[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_spi[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_spi[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spi_sdi[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spi_sdi[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spi_sdi[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spi_sdi[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_sel_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_sel_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_sel_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_sel_i[0]}]
+###############################################################################
+# Design Rules
+###############################################################################
diff --git a/openlane/qspim/config.tcl b/openlane/qspim/config.tcl
index 9666942..57a2226 100755
--- a/openlane/qspim/config.tcl
+++ b/openlane/qspim/config.tcl
@@ -36,6 +36,7 @@
 
 # Local sources + no2usb sources
 set ::env(VERILOG_FILES) "\
+        $script_dir/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \
         $script_dir/../../verilog/rtl/qspim/src/qspim_top.sv \
         $script_dir/../../verilog/rtl/qspim/src/qspim_if.sv \
         $script_dir/../../verilog/rtl/qspim/src/qspim_regs.sv \
@@ -87,12 +88,12 @@
 set ::env(FP_PDN_VWIDTH) 5
 set ::env(FP_PDN_HWIDTH) 5
 
-set ::env(GLB_RT_MAXLAYER) 4
+set ::env(GLB_RT_MAXLAYER) 5
 set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
 set ::env(DIODE_INSERTION_STRATEGY) 4
 
 
 set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
-set ::env(QUIT_ON_MAGIC_DRC) "0"
+set ::env(QUIT_ON_MAGIC_DRC) "1"
 set ::env(QUIT_ON_LVS_ERROR) "0"
 set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
diff --git a/openlane/qspim/pin_order.cfg b/openlane/qspim/pin_order.cfg
index 5a26f7d..e45ddae 100644
--- a/openlane/qspim/pin_order.cfg
+++ b/openlane/qspim/pin_order.cfg
@@ -2,7 +2,17 @@
 #MANUAL_PLACE
 
 #W
-mclk                   0000 0
+cfg_cska_sp_co\[3\]   0000 0
+cfg_cska_sp_co\[2\]
+cfg_cska_sp_co\[1\]
+cfg_cska_sp_co\[0\]
+cfg_cska_spi\[3\]
+cfg_cska_spi\[2\]
+cfg_cska_spi\[1\]
+cfg_cska_spi\[0\]
+wbd_clk_int
+wbd_clk_spi
+mclk                   
 rst_n                  
 
 #E
diff --git a/openlane/syntacore/base.sdc b/openlane/syntacore/base.sdc
index 53a9082..47606b8 100644
--- a/openlane/syntacore/base.sdc
+++ b/openlane/syntacore/base.sdc
@@ -1,89 +1,947 @@
-# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+###############################################################################
+# Created by write_sdc
+# Mon Nov  8 09:31:35 2021
+###############################################################################
+current_design scr1_top_wb
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name core_clk -period 20.0000 [get_ports {core_clk}]
+create_clock -name rtc_clk -period 40.0000 [get_ports {rtc_clk}]
+create_clock -name wb_clk -period 10.0000 [get_ports {wb_clk}]
+set_clock_uncertainty -rise_from [get_clocks {core_clk}] -rise_to [get_clocks {core_clk}]  -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {core_clk}] -rise_to [get_clocks {core_clk}]  -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {core_clk}] -fall_to [get_clocks {core_clk}]  -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {core_clk}] -fall_to [get_clocks {core_clk}]  -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {core_clk}] -rise_to [get_clocks {core_clk}]  -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {core_clk}] -rise_to [get_clocks {core_clk}]  -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {core_clk}] -fall_to [get_clocks {core_clk}]  -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {core_clk}] -fall_to [get_clocks {core_clk}]  -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rtc_clk}]  -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rtc_clk}]  -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rtc_clk}]  -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rtc_clk}]  -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rtc_clk}]  -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rtc_clk}]  -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rtc_clk}]  -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rtc_clk}]  -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {wb_clk}] -rise_to [get_clocks {wb_clk}]  -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {wb_clk}] -rise_to [get_clocks {wb_clk}]  -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {wb_clk}] -fall_to [get_clocks {wb_clk}]  -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {wb_clk}] -fall_to [get_clocks {wb_clk}]  -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {wb_clk}] -rise_to [get_clocks {wb_clk}]  -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {wb_clk}] -rise_to [get_clocks {wb_clk}]  -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {wb_clk}] -fall_to [get_clocks {wb_clk}]  -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {wb_clk}] -fall_to [get_clocks {wb_clk}]  -setup 0.2000
+set_clock_groups -name async_clock -asynchronous \
+ -group [get_clocks {core_clk}]\
+ -group [get_clocks {rtc_clk}]\
+ -group [get_clocks {wb_clk}] -comment {Async Clock group}
 
 
-set_units -time ns
-#Wishbone Clock
-set ::env(WB_CLOCK_PERIOD)    "10"
-set ::env(WB_CLOCK_PORT)      "wb_clk"
-set ::env(WB_CLOCK_NAME)      "wb_clk"
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[0]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[10]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[11]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[12]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[13]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[14]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[15]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[16]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[17]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[18]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[19]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[1]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[20]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[21]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[22]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[23]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[24]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[25]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[26]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[27]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[28]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[29]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[2]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[30]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[31]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[3]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[4]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[5]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[6]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[7]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[8]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[9]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[0]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[10]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[11]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[12]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[13]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[14]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[15]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[16]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[17]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[18]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[19]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[1]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[20]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[21]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[22]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[23]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[24]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[25]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[26]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[27]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[28]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[29]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[2]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[30]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[31]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[3]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[4]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[5]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[6]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[7]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[8]}]
+set_input_delay 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[9]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr0[0]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr0[1]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr0[2]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr0[3]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr0[4]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr0[5]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr0[6]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr0[7]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr0[8]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr1[0]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr1[1]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr1[2]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr1[3]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr1[4]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr1[5]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr1[6]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr1[7]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr1[8]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_csb0}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_csb1}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[0]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[10]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[11]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[12]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[13]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[14]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[15]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[16]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[17]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[18]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[19]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[1]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[20]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[21]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[22]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[23]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[24]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[25]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[26]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[27]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[28]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[29]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[2]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[30]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[31]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[3]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[4]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[5]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[6]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[7]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[8]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[9]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_web0}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_wmask0[0]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_wmask0[1]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_wmask0[2]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_wmask0[3]}]
 
-#Risc Core Clock
-set ::env(CORE_CLOCK_PERIOD) "20"
-set ::env(CORE_CLOCK_PORT)   "core_clk"
-set ::env(CORE_CLOCK_NAME)   "core_clk"
+set_input_delay 5.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_rst_n}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_ack_i}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[0]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[10]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[11]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[12]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[13]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[14]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[15]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[16]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[17]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[18]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[19]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[1]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[20]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[21]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[22]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[23]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[24]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[25]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[26]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[27]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[28]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[29]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[2]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[30]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[31]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[3]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[4]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[5]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[6]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[7]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[8]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[9]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_err_i}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_ack_i}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[0]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[10]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[11]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[12]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[13]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[14]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[15]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[16]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[17]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[18]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[19]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[1]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[20]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[21]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[22]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[23]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[24]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[25]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[26]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[27]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[28]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[29]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[2]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[30]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[31]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[3]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[4]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[5]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[6]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[7]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[8]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[9]}]
+set_input_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_err_i}]
 
-#RTC Core Clock
-set ::env(RTC_CLOCK_PERIOD) "40"
-set ::env(RTC_CLOCK_PORT)   "rtc_clk"
-set ::env(RTC_CLOCK_NAME)   "rtc_clk"
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[0]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[10]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[11]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[12]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[13]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[14]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[15]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[16]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[17]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[18]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[19]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[1]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[20]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[21]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[22]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[23]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[24]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[25]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[26]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[27]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[28]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[29]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[2]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[30]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[31]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[3]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[4]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[5]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[6]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[7]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[8]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[9]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[0]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[10]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[11]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[12]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[13]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[14]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[15]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[16]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[17]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[18]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[19]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[1]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[20]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[21]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[22]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[23]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[24]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[25]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[26]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[27]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[28]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[29]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[2]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[30]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[31]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[3]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[4]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[5]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[6]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[7]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[8]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[9]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_sel_o[0]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_sel_o[1]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_sel_o[2]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_sel_o[3]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_stb_o}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_we_o}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[0]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[10]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[11]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[12]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[13]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[14]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[15]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[16]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[17]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[18]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[19]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[1]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[20]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[21]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[22]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[23]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[24]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[25]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[26]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[27]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[28]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[29]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[2]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[30]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[31]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[3]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[4]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[5]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[6]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[7]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[8]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[9]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[0]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[10]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[11]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[12]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[13]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[14]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[15]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[16]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[17]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[18]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[19]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[1]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[20]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[21]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[22]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[23]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[24]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[25]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[26]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[27]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[28]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[29]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[2]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[30]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[31]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[3]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[4]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[5]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[6]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[7]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[8]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[9]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_sel_o[0]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_sel_o[1]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_sel_o[2]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_sel_o[3]}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_stb_o}]
+set_output_delay 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_we_o}]
+set_false_path\
+    -from [get_ports {soft_irq}]
+set_false_path\
+    -to [list [get_ports {riscv_debug[0]}]\
+           [get_ports {riscv_debug[10]}]\
+           [get_ports {riscv_debug[11]}]\
+           [get_ports {riscv_debug[12]}]\
+           [get_ports {riscv_debug[13]}]\
+           [get_ports {riscv_debug[14]}]\
+           [get_ports {riscv_debug[15]}]\
+           [get_ports {riscv_debug[16]}]\
+           [get_ports {riscv_debug[17]}]\
+           [get_ports {riscv_debug[18]}]\
+           [get_ports {riscv_debug[19]}]\
+           [get_ports {riscv_debug[1]}]\
+           [get_ports {riscv_debug[20]}]\
+           [get_ports {riscv_debug[21]}]\
+           [get_ports {riscv_debug[22]}]\
+           [get_ports {riscv_debug[23]}]\
+           [get_ports {riscv_debug[24]}]\
+           [get_ports {riscv_debug[25]}]\
+           [get_ports {riscv_debug[26]}]\
+           [get_ports {riscv_debug[27]}]\
+           [get_ports {riscv_debug[28]}]\
+           [get_ports {riscv_debug[29]}]\
+           [get_ports {riscv_debug[2]}]\
+           [get_ports {riscv_debug[30]}]\
+           [get_ports {riscv_debug[31]}]\
+           [get_ports {riscv_debug[32]}]\
+           [get_ports {riscv_debug[33]}]\
+           [get_ports {riscv_debug[34]}]\
+           [get_ports {riscv_debug[35]}]\
+           [get_ports {riscv_debug[36]}]\
+           [get_ports {riscv_debug[37]}]\
+           [get_ports {riscv_debug[38]}]\
+           [get_ports {riscv_debug[39]}]\
+           [get_ports {riscv_debug[3]}]\
+           [get_ports {riscv_debug[40]}]\
+           [get_ports {riscv_debug[41]}]\
+           [get_ports {riscv_debug[42]}]\
+           [get_ports {riscv_debug[43]}]\
+           [get_ports {riscv_debug[44]}]\
+           [get_ports {riscv_debug[45]}]\
+           [get_ports {riscv_debug[46]}]\
+           [get_ports {riscv_debug[47]}]\
+           [get_ports {riscv_debug[48]}]\
+           [get_ports {riscv_debug[49]}]\
+           [get_ports {riscv_debug[4]}]\
+           [get_ports {riscv_debug[50]}]\
+           [get_ports {riscv_debug[51]}]\
+           [get_ports {riscv_debug[52]}]\
+           [get_ports {riscv_debug[53]}]\
+           [get_ports {riscv_debug[54]}]\
+           [get_ports {riscv_debug[55]}]\
+           [get_ports {riscv_debug[56]}]\
+           [get_ports {riscv_debug[57]}]\
+           [get_ports {riscv_debug[58]}]\
+           [get_ports {riscv_debug[59]}]\
+           [get_ports {riscv_debug[5]}]\
+           [get_ports {riscv_debug[60]}]\
+           [get_ports {riscv_debug[61]}]\
+           [get_ports {riscv_debug[62]}]\
+           [get_ports {riscv_debug[63]}]\
+           [get_ports {riscv_debug[6]}]\
+           [get_ports {riscv_debug[7]}]\
+           [get_ports {riscv_debug[8]}]\
+           [get_ports {riscv_debug[9]}]]
 
-######################################
-# CORE Clock domain input output
-######################################
-create_clock [get_ports $::env(CORE_CLOCK_PORT)]  -name $::env(CORE_CLOCK_NAME)  -period $::env(CORE_CLOCK_PERIOD)
-set core_input_delay_value [expr $::env(CORE_CLOCK_PERIOD) * 0.6]
-set core_output_delay_value [expr $::env(CORE_CLOCK_PERIOD) * 0.6]
-puts "\[INFO\]: Setting core output delay to: $core_output_delay_value"
-puts "\[INFO\]: Setting core input delay to: $core_input_delay_value"
-set core_clk_indx [lsearch [all_inputs] [get_port $::env(CORE_CLOCK_NAME)]]
-set core_rst_indx [lsearch [all_inputs] [get_port cpu_rst_n]]
-set all_inputs_wo_core_clk_rst [lreplace [all_inputs] $core_clk_indx $core_rst_indx]
-set all_outputs_core [all_outputs] 
-
-set_input_delay $core_input_delay_value  -clock [get_clocks $::env(CORE_CLOCK_NAME)] $all_inputs_wo_core_clk_rst
-set_input_delay 5.0 -clock [get_clocks $::env(CORE_CLOCK_NAME)] {cpu_rst_n}
-set_output_delay $core_output_delay_value  -clock [get_clocks $::env(CORE_CLOCK_NAME)] $all_outputs_core
-
-create_clock [get_ports $::env(RTC_CLOCK_PORT)]  -name $::env(RTC_CLOCK_NAME)  -period $::env(RTC_CLOCK_PERIOD)
-
-######################################
-# WB Clock domain input output
-######################################
-create_clock [get_ports $::env(WB_CLOCK_PORT)]  -name $::env(WB_CLOCK_NAME)  -period $::env(WB_CLOCK_PERIOD)
-set wb_input_delay_value [expr $::env(WB_CLOCK_PERIOD) * 0.45]
-set wb_output_delay_value [expr $::env(WB_CLOCK_PERIOD) * 0.45]
-puts "\[INFO\]: Setting wb output delay to:$wb_output_delay_value"
-puts "\[INFO\]: Setting wb input delay to: $wb_input_delay_value"
-set wb_clk_indx [lsearch [all_inputs] [get_port $::env(WB_CLOCK_NAME)]]
-set wb_rst_indx [lsearch [all_inputs] [get_port wb_rst_n]]
-set all_inputs_wo_wb_clk_rst [lreplace [all_inputs] $wb_clk_indx $wb_rst_indx]
-set all_outputs_wb [all_outputs]
-
-set_false_path -to riscv_debug*
-set_false_path -from soft_irq
-
-set_input_delay $wb_input_delay_value  -clock [get_clocks $::env(WB_CLOCK_NAME)] $all_inputs_wo_wb_clk_rst
-set_input_delay 5.0 -clock [get_clocks $::env(WB_CLOCK_NAME)] {wb_rst_n}
-set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WB_CLOCK_NAME)] $all_outputs_wb
-
-#### Clock Async Defination
-set_clock_groups -name async_clock -asynchronous -comment "Async Clock group" -group [get_clocks $::env(WB_CLOCK_NAME)] -group [get_clocks $::env(CORE_CLOCK_NAME)] -group [get_clocks $::env(RTC_CLOCK_NAME)]
-
-set_clock_uncertainty -from $::env(WB_CLOCK_NAME)    -to $::env(WB_CLOCK_NAME)    -setup 0.400
-set_clock_uncertainty -from $::env(CORE_CLOCK_NAME)  -to $::env(CORE_CLOCK_NAME)   -setup 0.400
-set_clock_uncertainty -from $::env(RTC_CLOCK_NAME)   -to $::env(RTC_CLOCK_NAME)   -setup 0.400
-
-set_clock_uncertainty -from $::env(WB_CLOCK_NAME)    -to $::env(WB_CLOCK_NAME)    -hold 0.050
-set_clock_uncertainty -from $::env(CORE_CLOCK_NAME)  -to $::env(CORE_CLOCK_NAME)   -hold 0.050
-set_clock_uncertainty -from $::env(RTC_CLOCK_NAME)   -to $::env(RTC_CLOCK_NAME)   -hold 0.050
-
-
-# TODO set this as parameter
-set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
-set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
-puts "\[INFO\]: Setting load to: $cap_load"
-set_load  $cap_load [all_outputs]
+set_false_path -from [get_ports {fuse_mhartid[0]}]
+set_false_path -from [get_ports {fuse_mhartid[10]}]
+set_false_path -from [get_ports {fuse_mhartid[11]}]
+set_false_path -from [get_ports {fuse_mhartid[12]}]
+set_false_path -from [get_ports {fuse_mhartid[13]}]
+set_false_path -from [get_ports {fuse_mhartid[14]}]
+set_false_path -from [get_ports {fuse_mhartid[15]}]
+set_false_path -from [get_ports {fuse_mhartid[16]}]
+set_false_path -from [get_ports {fuse_mhartid[17]}]
+set_false_path -from [get_ports {fuse_mhartid[18]}]
+set_false_path -from [get_ports {fuse_mhartid[19]}]
+set_false_path -from [get_ports {fuse_mhartid[1]}]
+set_false_path -from [get_ports {fuse_mhartid[20]}]
+set_false_path -from [get_ports {fuse_mhartid[21]}]
+set_false_path -from [get_ports {fuse_mhartid[22]}]
+set_false_path -from [get_ports {fuse_mhartid[23]}]
+set_false_path -from [get_ports {fuse_mhartid[24]}]
+set_false_path -from [get_ports {fuse_mhartid[25]}]
+set_false_path -from [get_ports {fuse_mhartid[26]}]
+set_false_path -from [get_ports {fuse_mhartid[27]}]
+set_false_path -from [get_ports {fuse_mhartid[28]}]
+set_false_path -from [get_ports {fuse_mhartid[29]}]
+set_false_path -from [get_ports {fuse_mhartid[2]}]
+set_false_path -from [get_ports {fuse_mhartid[30]}]
+set_false_path -from [get_ports {fuse_mhartid[31]}]
+set_false_path -from [get_ports {fuse_mhartid[3]}]
+set_false_path -from [get_ports {fuse_mhartid[4]}]
+set_false_path -from [get_ports {fuse_mhartid[5]}]
+set_false_path -from [get_ports {fuse_mhartid[6]}]
+set_false_path -from [get_ports {fuse_mhartid[7]}]
+set_false_path -from [get_ports {fuse_mhartid[8]}]
+set_false_path -from [get_ports {fuse_mhartid[9]}]
+set_false_path -from [get_ports {irq_lines[0]}]
+set_false_path -from [get_ports {irq_lines[10]}]
+set_false_path -from [get_ports {irq_lines[11]}]
+set_false_path -from [get_ports {irq_lines[12]}]
+set_false_path -from [get_ports {irq_lines[13]}]
+set_false_path -from [get_ports {irq_lines[14]}]
+set_false_path -from [get_ports {irq_lines[15]}]
+set_false_path -from [get_ports {irq_lines[1]}]
+set_false_path -from [get_ports {irq_lines[2]}]
+set_false_path -from [get_ports {irq_lines[3]}]
+set_false_path -from [get_ports {irq_lines[4]}]
+set_false_path -from [get_ports {irq_lines[5]}]
+set_false_path -from [get_ports {irq_lines[6]}]
+set_false_path -from [get_ports {irq_lines[7]}]
+set_false_path -from [get_ports {irq_lines[8]}]
+set_false_path -from [get_ports {irq_lines[9]}]
+set_false_path -from [get_ports {pwrup_rst_n}]
+set_false_path -from [get_ports {rst_n}]
+set_false_path -from [get_ports {soft_irq}]
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {sram_csb0}]
+set_load -pin_load 0.0334 [get_ports {sram_csb1}]
+set_load -pin_load 0.0334 [get_ports {sram_web0}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_stb_o}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_we_o}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_stb_o}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_we_o}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[63]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[62]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[61]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[60]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[59]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[58]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[57]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[56]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[55]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[54]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[53]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[52]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[51]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[50]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[49]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[48]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[47]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[46]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[45]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[44]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[43]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[42]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[41]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[40]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[39]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[38]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[37]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[36]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[35]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[34]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[33]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[32]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[31]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[30]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[29]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[28]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[27]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[26]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[25]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[24]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[23]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[22]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[21]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[20]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[19]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[18]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[17]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[16]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[15]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[14]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[13]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[12]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[11]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[10]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[9]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[8]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[7]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[6]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[5]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[4]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[3]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[2]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[1]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[0]}]
+set_load -pin_load 0.0334 [get_ports {sram_addr0[8]}]
+set_load -pin_load 0.0334 [get_ports {sram_addr0[7]}]
+set_load -pin_load 0.0334 [get_ports {sram_addr0[6]}]
+set_load -pin_load 0.0334 [get_ports {sram_addr0[5]}]
+set_load -pin_load 0.0334 [get_ports {sram_addr0[4]}]
+set_load -pin_load 0.0334 [get_ports {sram_addr0[3]}]
+set_load -pin_load 0.0334 [get_ports {sram_addr0[2]}]
+set_load -pin_load 0.0334 [get_ports {sram_addr0[1]}]
+set_load -pin_load 0.0334 [get_ports {sram_addr0[0]}]
+set_load -pin_load 0.0334 [get_ports {sram_addr1[8]}]
+set_load -pin_load 0.0334 [get_ports {sram_addr1[7]}]
+set_load -pin_load 0.0334 [get_ports {sram_addr1[6]}]
+set_load -pin_load 0.0334 [get_ports {sram_addr1[5]}]
+set_load -pin_load 0.0334 [get_ports {sram_addr1[4]}]
+set_load -pin_load 0.0334 [get_ports {sram_addr1[3]}]
+set_load -pin_load 0.0334 [get_ports {sram_addr1[2]}]
+set_load -pin_load 0.0334 [get_ports {sram_addr1[1]}]
+set_load -pin_load 0.0334 [get_ports {sram_addr1[0]}]
+set_load -pin_load 0.0334 [get_ports {sram_din0[31]}]
+set_load -pin_load 0.0334 [get_ports {sram_din0[30]}]
+set_load -pin_load 0.0334 [get_ports {sram_din0[29]}]
+set_load -pin_load 0.0334 [get_ports {sram_din0[28]}]
+set_load -pin_load 0.0334 [get_ports {sram_din0[27]}]
+set_load -pin_load 0.0334 [get_ports {sram_din0[26]}]
+set_load -pin_load 0.0334 [get_ports {sram_din0[25]}]
+set_load -pin_load 0.0334 [get_ports {sram_din0[24]}]
+set_load -pin_load 0.0334 [get_ports {sram_din0[23]}]
+set_load -pin_load 0.0334 [get_ports {sram_din0[22]}]
+set_load -pin_load 0.0334 [get_ports {sram_din0[21]}]
+set_load -pin_load 0.0334 [get_ports {sram_din0[20]}]
+set_load -pin_load 0.0334 [get_ports {sram_din0[19]}]
+set_load -pin_load 0.0334 [get_ports {sram_din0[18]}]
+set_load -pin_load 0.0334 [get_ports {sram_din0[17]}]
+set_load -pin_load 0.0334 [get_ports {sram_din0[16]}]
+set_load -pin_load 0.0334 [get_ports {sram_din0[15]}]
+set_load -pin_load 0.0334 [get_ports {sram_din0[14]}]
+set_load -pin_load 0.0334 [get_ports {sram_din0[13]}]
+set_load -pin_load 0.0334 [get_ports {sram_din0[12]}]
+set_load -pin_load 0.0334 [get_ports {sram_din0[11]}]
+set_load -pin_load 0.0334 [get_ports {sram_din0[10]}]
+set_load -pin_load 0.0334 [get_ports {sram_din0[9]}]
+set_load -pin_load 0.0334 [get_ports {sram_din0[8]}]
+set_load -pin_load 0.0334 [get_ports {sram_din0[7]}]
+set_load -pin_load 0.0334 [get_ports {sram_din0[6]}]
+set_load -pin_load 0.0334 [get_ports {sram_din0[5]}]
+set_load -pin_load 0.0334 [get_ports {sram_din0[4]}]
+set_load -pin_load 0.0334 [get_ports {sram_din0[3]}]
+set_load -pin_load 0.0334 [get_ports {sram_din0[2]}]
+set_load -pin_load 0.0334 [get_ports {sram_din0[1]}]
+set_load -pin_load 0.0334 [get_ports {sram_din0[0]}]
+set_load -pin_load 0.0334 [get_ports {sram_wmask0[3]}]
+set_load -pin_load 0.0334 [get_ports {sram_wmask0[2]}]
+set_load -pin_load 0.0334 [get_ports {sram_wmask0[1]}]
+set_load -pin_load 0.0334 [get_ports {sram_wmask0[0]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[31]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[30]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[29]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[28]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[27]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[26]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[25]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[24]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[23]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[22]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[21]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[20]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[19]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[18]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[17]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[16]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[15]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[14]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[13]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[12]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[11]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[10]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[9]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[8]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[7]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[6]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[5]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[4]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[3]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[2]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[1]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[0]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[31]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[30]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[29]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[28]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[27]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[26]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[25]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[24]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[23]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[22]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[21]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[20]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[19]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[18]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[17]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[16]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[15]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[14]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[13]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[12]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[11]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[10]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[9]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[8]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[7]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[6]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[5]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[4]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[3]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[2]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[1]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[0]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_sel_o[3]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_sel_o[2]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_sel_o[1]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_sel_o[0]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[31]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[30]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[29]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[28]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[27]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[26]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[25]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[24]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[23]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[22]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[21]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[20]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[19]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[18]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[17]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[16]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[15]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[14]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[13]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[12]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[11]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[10]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[9]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[8]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[7]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[6]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[5]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[4]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[3]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[2]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[1]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[0]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[31]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[30]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[29]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[28]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[27]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[26]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[25]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[24]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[23]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[22]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[21]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[20]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[19]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[18]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[17]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[16]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[15]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[14]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[13]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[12]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[11]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[10]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[9]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[8]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[7]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[6]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[5]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[4]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[3]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[2]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[1]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[0]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_sel_o[3]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_sel_o[2]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_sel_o[1]}]
+set_load -pin_load 0.0334 [get_ports {wbd_imem_sel_o[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_clk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cpu_rst_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {pwrup_rst_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rst_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rtc_clk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {soft_irq}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_clk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_rst_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_ack_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_err_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_ack_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_err_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_lines[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_lines[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_lines[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_lines[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_lines[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_lines[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_lines[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_lines[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_lines[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_lines[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_lines[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_lines[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_lines[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_lines[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_lines[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_lines[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[0]}]
+###############################################################################
+# Design Rules
+###############################################################################
diff --git a/openlane/syntacore/config.tcl b/openlane/syntacore/config.tcl
index de826a4..b926472 100755
--- a/openlane/syntacore/config.tcl
+++ b/openlane/syntacore/config.tcl
@@ -35,6 +35,7 @@
 
 # Local sources + no2usb sources
 set ::env(VERILOG_FILES) "\
+        $script_dir/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \
 	$script_dir/../../verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_top.sv  \
 	$script_dir/../../verilog/rtl/syntacore/scr1/src/core/scr1_core_top.sv  \
 	$script_dir/../../verilog/rtl/syntacore/scr1/src/core/scr1_dm.sv  \
@@ -68,6 +69,7 @@
 	$script_dir/../../verilog/rtl/lib/async_fifo.sv "
 
 set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/syntacore/scr1/src/includes ]
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
 
 set ::env(SDC_FILE) "$script_dir/base.sdc"
 set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
diff --git a/openlane/syntacore/pin_order.cfg b/openlane/syntacore/pin_order.cfg
index 2fe39f5..119fd44 100644
--- a/openlane/syntacore/pin_order.cfg
+++ b/openlane/syntacore/pin_order.cfg
@@ -3,7 +3,8 @@
 #MANUAL_PLACE
 
 #E
-core_clk            0000 0
+
+core_clk            1000 0
 rtc_clk             
 cpu_rst_n           
 
@@ -57,132 +58,14 @@
 fuse_mhartid\[1\] 
 fuse_mhartid\[0\] 
 
-sram_dout0\[31\] 200 0  4
-sram_dout0\[30\]
-sram_dout0\[29\]
-sram_dout0\[28\]
-sram_dout0\[27\]
-sram_dout0\[26\]
-sram_dout0\[25\]
-sram_dout0\[24\]
-sram_dout0\[23\]
-sram_dout0\[22\]
-sram_dout0\[21\]
-sram_dout0\[20\]
-sram_dout0\[19\]
-sram_dout0\[18\]
-sram_dout0\[17\]
-sram_dout0\[16\]
-sram_dout0\[15\]
-sram_dout0\[14\]
-sram_dout0\[13\]
-sram_dout0\[12\]
-sram_dout0\[11\]
-sram_dout0\[10\]
-sram_dout0\[9\]
-sram_dout0\[8\]
-sram_dout0\[7\]
-sram_dout0\[6\]
-sram_dout0\[5\]
-sram_dout0\[4\]
-sram_dout0\[3\]
-sram_dout0\[2\]
-sram_dout0\[1\]
-sram_dout0\[0\]
-
-sram_din0\[31\] 300 0  4
-sram_din0\[30\]
-sram_din0\[29\]
-sram_din0\[28\]
-sram_din0\[27\]
-sram_din0\[26\]
-sram_din0\[25\]
-sram_din0\[24\]
-sram_din0\[23\]
-sram_din0\[22\]
-sram_din0\[21\]
-sram_din0\[20\]
-sram_din0\[19\]
-sram_din0\[18\]
-sram_din0\[17\]
-sram_din0\[16\]
-sram_din0\[15\]
-sram_din0\[14\]
-sram_din0\[13\]
-sram_din0\[12\]
-sram_din0\[11\]
-sram_din0\[10\]
-sram_din0\[9\]
-sram_din0\[8\]
-sram_din0\[7\]
-sram_din0\[6\]
-sram_din0\[5\]
-sram_din0\[4\]
-sram_din0\[3\]
-sram_din0\[2\]
-sram_din0\[1\]
-sram_din0\[0\]
-sram_wmask0\[3\]  
-sram_wmask0\[2\]
-sram_wmask0\[1\]
-sram_wmask0\[0\]
-sram_web0
-sram_csb0            
-sram_addr0\[8\]
-sram_addr0\[7\]
-sram_addr0\[6\]
-sram_addr0\[5\]
-sram_addr0\[4\]
-sram_addr0\[3\]
-sram_addr0\[2\]
-sram_addr0\[1\]
-sram_addr0\[0\]
-
-sram_csb1             0800 0 4
-sram_addr1\[8\]
-sram_addr1\[7\]
-sram_addr1\[6\]
-sram_addr1\[5\]
-sram_addr1\[4\]
-sram_addr1\[3\]
-sram_addr1\[2\]
-sram_addr1\[1\]
-sram_addr1\[0\]
-sram_dout1\[31\]
-sram_dout1\[30\]
-sram_dout1\[29\]
-sram_dout1\[28\]
-sram_dout1\[27\]
-sram_dout1\[26\]
-sram_dout1\[25\]
-sram_dout1\[24\]
-sram_dout1\[23\]
-sram_dout1\[22\]
-sram_dout1\[21\]
-sram_dout1\[20\]
-sram_dout1\[19\]
-sram_dout1\[18\]
-sram_dout1\[17\]
-sram_dout1\[16\]
-sram_dout1\[15\]
-sram_dout1\[14\]
-sram_dout1\[13\]
-sram_dout1\[12\]
-sram_dout1\[11\]
-sram_dout1\[10\]
-sram_dout1\[9\]
-sram_dout1\[8\]
-sram_dout1\[7\]
-sram_dout1\[6\]
-sram_dout1\[5\]
-sram_dout1\[4\]
-sram_dout1\[3\]
-sram_dout1\[2\]
-sram_dout1\[1\]
-sram_dout1\[0\]
-
 #W
-wb_clk            0000 0
+cfg_cska_riscv\[3\]    0000 0 4
+cfg_cska_riscv\[2\]
+cfg_cska_riscv\[1\]
+cfg_cska_riscv\[0\]
+wbd_clk_int
+wbd_clk_riscv
+wb_clk            
 wb_rst_n          
 pwrup_rst_n       
 rst_n        
@@ -401,7 +284,7 @@
 
 
 #S
-riscv_debug\[0\]   500  0 4
+riscv_debug\[0\]   300  0 4
 riscv_debug\[1\]
 riscv_debug\[2\]
 riscv_debug\[3\]
@@ -466,3 +349,126 @@
 riscv_debug\[62\]
 riscv_debug\[63\]
 
+sram_dout0\[31\] 500 0  4
+sram_dout0\[30\]
+sram_dout0\[29\]
+sram_dout0\[28\]
+sram_dout0\[27\]
+sram_dout0\[26\]
+sram_dout0\[25\]
+sram_dout0\[24\]
+sram_dout0\[23\]
+sram_dout0\[22\]
+sram_dout0\[21\]
+sram_dout0\[20\]
+sram_dout0\[19\]
+sram_dout0\[18\]
+sram_dout0\[17\]
+sram_dout0\[16\]
+sram_dout0\[15\]
+sram_dout0\[14\]
+sram_dout0\[13\]
+sram_dout0\[12\]
+sram_dout0\[11\]
+sram_dout0\[10\]
+sram_dout0\[9\]
+sram_dout0\[8\]
+sram_dout0\[7\]
+sram_dout0\[6\]
+sram_dout0\[5\]
+sram_dout0\[4\]
+sram_dout0\[3\]
+sram_dout0\[2\]
+sram_dout0\[1\]
+sram_dout0\[0\]
+
+sram_din0\[31\] 800 0  4
+sram_din0\[30\]
+sram_din0\[29\]
+sram_din0\[28\]
+sram_din0\[27\]
+sram_din0\[26\]
+sram_din0\[25\]
+sram_din0\[24\]
+sram_din0\[23\]
+sram_din0\[22\]
+sram_din0\[21\]
+sram_din0\[20\]
+sram_din0\[19\]
+sram_din0\[18\]
+sram_din0\[17\]
+sram_din0\[16\]
+sram_din0\[15\]
+sram_din0\[14\]
+sram_din0\[13\]
+sram_din0\[12\]
+sram_din0\[11\]
+sram_din0\[10\]
+sram_din0\[9\]
+sram_din0\[8\]
+sram_din0\[7\]
+sram_din0\[6\]
+sram_din0\[5\]
+sram_din0\[4\]
+sram_din0\[3\]
+sram_din0\[2\]
+sram_din0\[1\]
+sram_din0\[0\]
+sram_wmask0\[3\]  
+sram_wmask0\[2\]
+sram_wmask0\[1\]
+sram_wmask0\[0\]
+sram_web0
+sram_csb0            
+sram_addr0\[8\]
+sram_addr0\[7\]
+sram_addr0\[6\]
+sram_addr0\[5\]
+sram_addr0\[4\]
+sram_addr0\[3\]
+sram_addr0\[2\]
+sram_addr0\[1\]
+sram_addr0\[0\]
+
+sram_csb1             1000 0 4
+sram_addr1\[8\]
+sram_addr1\[7\]
+sram_addr1\[6\]
+sram_addr1\[5\]
+sram_addr1\[4\]
+sram_addr1\[3\]
+sram_addr1\[2\]
+sram_addr1\[1\]
+sram_addr1\[0\]
+sram_dout1\[0\]
+sram_dout1\[1\]
+sram_dout1\[2\]
+sram_dout1\[3\]
+sram_dout1\[4\]
+sram_dout1\[5\]
+sram_dout1\[6\]
+sram_dout1\[7\]
+sram_dout1\[8\]
+sram_dout1\[9\]
+sram_dout1\[10\]
+sram_dout1\[11\]
+sram_dout1\[12\]
+sram_dout1\[13\]
+sram_dout1\[14\]
+sram_dout1\[15\]
+sram_dout1\[16\]
+sram_dout1\[17\]
+sram_dout1\[18\]
+sram_dout1\[19\]
+sram_dout1\[20\]
+sram_dout1\[21\]
+sram_dout1\[22\]
+sram_dout1\[23\]
+sram_dout1\[24\]
+sram_dout1\[25\]
+sram_dout1\[26\]
+sram_dout1\[27\]
+sram_dout1\[28\]
+sram_dout1\[29\]
+sram_dout1\[30\]
+sram_dout1\[31\]
diff --git a/openlane/uart/base.sdc b/openlane/uart/base.sdc
deleted file mode 100644
index b64ad61..0000000
--- a/openlane/uart/base.sdc
+++ /dev/null
@@ -1,72 +0,0 @@
-# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
-
-
-set_units -time ns
-set ::env(CORE_CLOCK_PERIOD) "10"
-set ::env(CORE_CLOCK_PORT)   "app_clk"
-set ::env(CORE_CLOCK_NAME)   "app_clk"
-
-set ::env(LINE_CLOCK_PERIOD) "100"
-set ::env(LINE_CLOCK_PORT)   "u_lineclk_buf/X"
-set ::env(LINE_CLOCK_NAME)   "line_clk"
-
-######################################
-# WB Clock domain input output
-######################################
-create_clock [get_ports $::env(CORE_CLOCK_PORT)]  -name $::env(CORE_CLOCK_NAME)  -period $::env(CORE_CLOCK_PERIOD)
-create_clock [get_pins  $::env(LINE_CLOCK_PORT)]  -name $::env(LINE_CLOCK_NAME)  -period $::env(LINE_CLOCK_PERIOD)
-
-set core_input_delay_value [expr $::env(CORE_CLOCK_PERIOD) * 0.6]
-set core_output_delay_value [expr $::env(CORE_CLOCK_PERIOD) * 0.6]
-
-set line_input_delay_value  [expr $::env(LINE_CLOCK_PERIOD) * 0.6]
-set line_output_delay_value [expr $::env(LINE_CLOCK_PERIOD) * 0.6]
-puts "\[INFO\]: Setting wb output delay to:$core_output_delay_value"
-puts "\[INFO\]: Setting wb input delay to: $core_input_delay_value"
-
-
-set_input_delay 2.0 -clock [get_clocks $::env(CORE_CLOCK_NAME)] {arst_n}
-
-set_input_delay  $core_input_delay_value   -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_cs*]
-set_input_delay  $core_input_delay_value   -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_addr*]
-set_input_delay  $core_input_delay_value   -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_wr*]
-set_input_delay  $core_input_delay_value   -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_be*]
-set_input_delay  $core_input_delay_value   -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_wdata*]
-
-
-set_output_delay $core_output_delay_value  -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_rdata*]
-set_output_delay $core_output_delay_value  -clock [get_clocks $::env(CORE_CLOCK_NAME)] [get_port reg_ack*]
-
-set_input_delay  $line_input_delay_value   -clock [get_clocks $::env(LINE_CLOCK_NAME)] [get_port io_in*]
-set_output_delay $line_input_delay_value   -clock [get_clocks $::env(LINE_CLOCK_NAME)] [get_port io_oeb*]
-set_output_delay $line_output_delay_value  -clock [get_clocks $::env(LINE_CLOCK_NAME)] [get_port io_out*]
-
-
-set_clock_groups -name async_clock -asynchronous -comment "Async Clock group" -group [get_clocks $::env(CORE_CLOCK_NAME)] -group [get_clocks $::env(LINE_CLOCK_NAME)] 
-
-set_clock_uncertainty -from $::env(CORE_CLOCK_NAME)   -to $::env(CORE_CLOCK_NAME)  -setup 0.400
-set_clock_uncertainty -from $::env(LINE_CLOCK_NAME)   -to $::env(LINE_CLOCK_NAME) -setup 0.400
-
-set_clock_uncertainty -from $::env(CORE_CLOCK_NAME)   -to $::env(CORE_CLOCK_NAME)  -hold 0.050
-set_clock_uncertainty -from $::env(LINE_CLOCK_NAME)   -to $::env(LINE_CLOCK_NAME) -hold 0.050
-
-# TODO set this as parameter
-set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
-set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
-puts "\[INFO\]: Setting load to: $cap_load"
-set_load  $cap_load [all_outputs]
-
diff --git a/openlane/uart/config.tcl b/openlane/uart/config.tcl
deleted file mode 100644
index b1eadeb..0000000
--- a/openlane/uart/config.tcl
+++ /dev/null
@@ -1,91 +0,0 @@
-# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
-
-# Global
-# ------
-
-set script_dir [file dirname [file normalize [info script]]]
-# Name
-set ::env(DESIGN_NAME) uart_core
-
-
-set ::env(DESIGN_IS_CORE) "0"
-set ::env(FP_PDN_CORE_RING) "0"
-
-# Timing configuration
-set ::env(CLOCK_PERIOD) "10"
-set ::env(CLOCK_PORT) "app_clk"
-
-set ::env(SYNTH_MAX_FANOUT) 4
-
-# Sources
-# -------
-
-# Local sources + no2usb sources
-set ::env(VERILOG_FILES) "\
-    $script_dir/../../verilog/rtl/uart/src/uart_core.sv  \
-    $script_dir/../../verilog/rtl/uart/src/uart_cfg.sv   \
-    $script_dir/../../verilog/rtl/uart/src/uart_rxfsm.sv \
-    $script_dir/../../verilog/rtl/uart/src/uart_txfsm.sv \
-    $script_dir/../../verilog/rtl/lib/async_fifo_th.sv   \
-    $script_dir/../../verilog/rtl/lib/reset_sync.sv      \
-    $script_dir/../../verilog/rtl/lib/double_sync_low.v  \
-    $script_dir/../../verilog/rtl/lib/clk_ctl.v          \
-    $script_dir/../../verilog/rtl/lib/registers.v        \
-    "
-
-set ::env(SYNTH_READ_BLACKBOX_LIB) 1
-#set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/sdram_ctrl/src/defs ]
-
-set ::env(SDC_FILE) "$script_dir/base.sdc"
-set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
-
-set ::env(LEC_ENABLE) 0
-
-set ::env(VDD_PIN) [list {vccd1}]
-set ::env(GND_PIN) [list {vssd1}]
-
-
-# Floorplanning
-# -------------
-
-set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
-set ::env(FP_SIZING) "absolute"
-set ::env(DIE_AREA) [list 0.0 0.0 300.0 400.0]
-
-
-
-# If you're going to use multiple power domains, then keep this disabled.
-set ::env(RUN_CVC) 0
-
-#set ::env(PDN_CFG) $script_dir/pdn.tcl
-
-
-set ::env(PL_ROUTABILITY_DRIVEN) 1
-
-set ::env(FP_IO_VEXTEND) 4
-set ::env(FP_IO_HEXTEND) 4
-
-
-set ::env(GLB_RT_MAXLAYER) 4
-set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
-
-set ::env(DIODE_INSERTION_STRATEGY) 4
-
-set ::env(FP_PDN_VPITCH) 100
-set ::env(FP_PDN_HPITCH) 100
-set ::env(FP_PDN_VWIDTH) 5
-set ::env(FP_PDN_HWIDTH) 5
diff --git a/openlane/uart/pdn.tcl b/openlane/uart/pdn.tcl
deleted file mode 100644
index 1fe689b..0000000
--- a/openlane/uart/pdn.tcl
+++ /dev/null
@@ -1,49 +0,0 @@
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-
-# Power nets
-set ::power_nets $::env(VDD_PIN)
-set ::ground_nets $::env(GND_PIN)
-
-set ::macro_blockage_layer_list "li1 met1 met2 met3 met4 met5"
-
-pdngen::specify_grid stdcell {
-    name grid
-    rails {
-	    met1 {width 0.48 pitch $::env(PLACE_SITE_HEIGHT) offset 0}
-    }
-    straps {
-	    met4 {width 1.6 pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)}
-	    met5 {width 1.6 pitch $::env(FP_PDN_HPITCH) offset $::env(FP_PDN_HOFFSET)}
-    }
-    connect {{met1 met4} {met4 met5}}
-}
-
-pdngen::specify_grid macro {
-    power_pins "VPWR"
-    ground_pins "VGND"
-    blockages "li1 met1 met2 met3 met4"
-    straps { 
-    } 
-    connect {{met4_PIN_ver met5}}
-}
-
-set ::halo 5
-
-# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
-set ::rails_start_with "POWER" ;
-
-# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
-set ::stripes_start_with "POWER" ;
diff --git a/openlane/uart/pin_order.cfg b/openlane/uart/pin_order.cfg
deleted file mode 100644
index 248595c..0000000
--- a/openlane/uart/pin_order.cfg
+++ /dev/null
@@ -1,38 +0,0 @@
-#BUS_SORT
-#MANUAL_PLACE
-
-#S
-app_clk                0000 0
-arst_n                 
-io_in\[1\]             
-io_out\[1\]             
-io_oeb\[1\]             
-io_in\[0\]             
-io_out\[0\]             
-io_oeb\[0\]             
-
-#N
-reg_cs                 0000 0
-reg_wr                 0000 1
-reg_addr\[3\]          0000 4
-reg_addr\[2\]          0000 5
-reg_addr\[1\]          0000 6
-reg_addr\[0\]          0000 7
-reg_be                 0000 10
-reg_wdata\[7\]         0000 11
-reg_wdata\[6\]         0000 12
-reg_wdata\[5\]         0000 13
-reg_wdata\[4\]         0000 14
-reg_wdata\[3\]         0000 15
-reg_wdata\[2\]         0000 16
-reg_wdata\[1\]         0000 17
-reg_wdata\[0\]         0000 18
-reg_rdata\[7\]         0000 19
-reg_rdata\[6\]         0000 20
-reg_rdata\[5\]         0000 21
-reg_rdata\[4\]         0000 22
-reg_rdata\[3\]         0000 23
-reg_rdata\[2\]         0000 24
-reg_rdata\[1\]         0000 25
-reg_rdata\[0\]         0000 26
-reg_ack                0000 27
diff --git a/openlane/uart/sta.tcl b/openlane/uart/sta.tcl
deleted file mode 100644
index e9d4a77..0000000
--- a/openlane/uart/sta.tcl
+++ /dev/null
@@ -1,56 +0,0 @@
-# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
-
-set ::env(LIB_FASTEST) "/home/dinesha/workarea/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib"
-set ::env(LIB_SLOWEST) "/home/dinesha/workarea/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib"
-set ::env(CURRENT_NETLIST) /project/openlane/uart/runs/uart/results/lvs/uart_core.lvs.powered.v
-set ::env(DESIGN_NAME) "uart_core"
-set ::env(CURRENT_SPEF) /project/openlane/uart/runs/uart/results/routing/uart_core.spef
-set ::env(BASE_SDC_FILE) "/project/openlane/uart/base.sdc"
-set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_8"
-set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
-set ::env(SYNTH_CAP_LOAD) "17.65"
-set ::env(WIRE_RC_LAYER) "met1"
-
-
-set_cmd_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm -distance um
-read_liberty -min $::env(LIB_FASTEST)
-read_liberty -max $::env(LIB_SLOWEST)
-read_verilog $::env(CURRENT_NETLIST)
-link_design  $::env(DESIGN_NAME)
-
-read_spef  $::env(CURRENT_SPEF)
-
-read_sdc -echo $::env(BASE_SDC_FILE)
-
-# check for missing constraints
-#check_setup  -verbose > unconstraints.rpt
-
-set_operating_conditions -analysis_type bc_wc
-# Propgate the clock
-set_propagated_clock [all_clocks]
-
-report_tns
-report_wns
-report_power 
-report_checks -unique -slack_max -0.0 -group_count 100 
-report_checks -unique -slack_min -0.0 -group_count 100 
-report_checks -path_delay min_max 
-report_checks -group_count 100  -slack_max -0.01 
-
-
-
-
diff --git a/openlane/uart_i2cm_usb_spi/config.tcl b/openlane/uart_i2cm_usb_spi/config.tcl
index b0a8c3a..e9d2c1d 100644
--- a/openlane/uart_i2cm_usb_spi/config.tcl
+++ b/openlane/uart_i2cm_usb_spi/config.tcl
@@ -36,6 +36,7 @@
 
 # Local sources + no2usb sources
 set ::env(VERILOG_FILES) "\
+    $script_dir/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \
     $script_dir/../../verilog/rtl/uart/src/uart_core.sv  \
     $script_dir/../../verilog/rtl/uart/src/uart_cfg.sv   \
     $script_dir/../../verilog/rtl/uart/src/uart_rxfsm.sv \
@@ -101,12 +102,17 @@
 set ::env(FP_IO_VEXTEND) 4
 set ::env(FP_IO_HEXTEND) 4
 
+set ::env(FP_PDN_VPITCH) 100
+set ::env(FP_PDN_HPITCH) 100
+set ::env(FP_PDN_VWIDTH) 5
+set ::env(FP_PDN_HWIDTH) 5
 
 set ::env(GLB_RT_MAXLAYER) 5
 set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
 set ::env(DIODE_INSERTION_STRATEGY) 4
 
-set ::env(FP_PDN_VPITCH) 100
-set ::env(FP_PDN_HPITCH) 100
-set ::env(FP_PDN_VWIDTH) 5
-set ::env(FP_PDN_HWIDTH) 5
+
+set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
+set ::env(QUIT_ON_MAGIC_DRC) "1"
+set ::env(QUIT_ON_LVS_ERROR) "0"
+set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
diff --git a/openlane/uart_i2cm_usb_spi/pin_order.cfg b/openlane/uart_i2cm_usb_spi/pin_order.cfg
index 6f6eea7..07237d6 100644
--- a/openlane/uart_i2cm_usb_spi/pin_order.cfg
+++ b/openlane/uart_i2cm_usb_spi/pin_order.cfg
@@ -2,10 +2,7 @@
 #MANUAL_PLACE
 
 #S
-app_clk                0000 0
-usb_clk
-
-reg_cs                 
+reg_cs                 0000 0  2
 reg_wr                 
 reg_addr\[7\]          
 reg_addr\[6\]          
@@ -15,7 +12,10 @@
 reg_addr\[2\]          
 reg_addr\[1\]          
 reg_addr\[0\]          
-reg_be                 
+reg_be\[3\]                 
+reg_be\[2\]                 
+reg_be\[1\]                 
+reg_be\[0\]                 
 reg_wdata\[31\]         
 reg_wdata\[30\]         
 reg_wdata\[29\]         
@@ -83,7 +83,14 @@
 reg_rdata\[0\]         
 reg_ack                
 
-
+cfg_cska_uart\[3\]     0500 0  2
+cfg_cska_uart\[2\]
+cfg_cska_uart\[1\]
+cfg_cska_uart\[0\]
+wbd_clk_int
+wbd_clk_uart
+app_clk                
+usb_clk
 uart_rstn    
 i2c_rstn 
 usb_rstn 
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 99d6096..1455224 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -113,11 +113,12 @@
 set ::env(VDD_NETS) "vccd1 vccd2 vdda1 vdda2"
 set ::env(GND_NETS) "vssd1 vssd2 vssa1 vssa2"
 
-set ::env(GLB_RT_OBS) "li1 2200.00 1200.00 2883.10 1616.54,  \
-	               met1 2200.00 1200.00 2883.10 1616.54, \
-	               met2 2200.00 1200.00 2883.10 1616.54, \
-	               met3 2200.00 1200.00 2883.10 1616.54, \
-		       met5 0 0 2920 3520"
+set ::env(GLB_RT_OBS) " li1  1200 200  1883.1 616.54,\
+                        met1 1200 200  1883.1 616.54,\
+	                met2 1200 200  1883.1 616.54,\
+	                met3 1200 200  1883.1 616.54,\
+			met4 1200 200  1883.1 616.54,\
+	                met5 0 0 2920 3520"
 
 set ::env(FP_PDN_MACROS) "\
 	u_adc vccd1 vssd1 \
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index b628ffc..af6e802 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1,8 +1,8 @@
 u_qspi_master           300             2700            N
 u_uart_i2c_usb_spi      1000            2700            N
-u_adc                   2000            2600            N
-u_riscv_top	        300	        800	        N
-u_sram_2kb              2200            1200            N
-u_pinmux                2200            300             N
-u_intercon              300             2300            N
+u_adc                   2000            2700            N
+u_riscv_top	        400	        800	        N
+u_sram_2kb              1200            200             N
+u_pinmux                2200            1600            N
+u_intercon              300             2325            N
 u_wb_host               300             300             N
diff --git a/openlane/user_project_wrapper/sta.tcl b/openlane/user_project_wrapper/sta.tcl
index 5be0cbe..206f46f 100644
--- a/openlane/user_project_wrapper/sta.tcl
+++ b/openlane/user_project_wrapper/sta.tcl
@@ -16,6 +16,7 @@
 
 
 set ::env(LIB_FASTEST) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib"
+set ::env(LIB_TYPICAL) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib"
 set ::env(LIB_SLOWEST) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib"
 set ::env(DESIGN_NAME) "user_project_wrapper"
 set ::env(BASE_SDC_FILE) "base.sdc"
@@ -29,37 +30,30 @@
 
 
 set_cmd_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm -distance um
-define_corners wc bc
+define_corners wc bc tt
 read_liberty -corner bc $::env(LIB_FASTEST)
 read_liberty -corner wc $::env(LIB_SLOWEST)
-read_verilog netlist/clk_skew_adjust.v  
-read_verilog netlist/glbl_cfg.v  
-read_verilog netlist/sdram.v  
-read_verilog netlist/spi_master.v 
+read_liberty -corner tt $::env(LIB_TYPICAL)
+
+read_lib  -corner tt   ../../lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib
+
+read_verilog netlist/qspim.v
 read_verilog netlist/syntacore.v  
 read_verilog netlist/uart_i2cm_usb.v  
 read_verilog netlist/wb_host.v  
 read_verilog netlist/wb_interconnect.v
+read_verilog netlist/pinmux.v
+read_verilog netlist/sar_adc.v
 read_verilog netlist/user_project_wrapper.v  
+
 link_design  $::env(DESIGN_NAME)
 
 
-read_spef -path u_skew_wi    ../../spef/clk_skew_adjust.spef  
-read_spef -path u_skew_riscv ../../spef/clk_skew_adjust.spef  
-read_spef -path u_skew_uart  ../../spef/clk_skew_adjust.spef  
-read_spef -path u_skew_spi   ../../spef/clk_skew_adjust.spef  
-read_spef -path u_skew_sdram ../../spef/clk_skew_adjust.spef  
-read_spef -path u_skew_glbl  ../../spef/clk_skew_adjust.spef  
-read_spef -path u_skew_wh    ../../spef/clk_skew_adjust.spef  
-read_spef -path u_skew_sd_co ../../spef/clk_skew_adjust.spef  
-read_spef -path u_skew_sd_ci ../../spef/clk_skew_adjust.spef  
-read_spef -path u_skew_sp_co ../../spef/clk_skew_adjust.spef  
-read_spef -path u_glbl_cfg   ../../spef/glbl_cfg.spef  
-read_spef -path u_riscv_top  ../../spef/syntacore.spef
-read_spef -path u_sdram_ctrl ../../spef/sdram.spef
-read_spef -path u_spi_master ../../spef/spi_master.spef
-read_spef -path u_uart_i2c_usb  ../../spef/uart_i2cm_usb.spef  
-read_spef -path u_wb_host    ../../spef/wb_host.spef  
+read_spef -path u_riscv_top  ../../spef/scr1_top_wb.spef
+read_spef -path u_pinmux ../../spef/pinmux.spef
+read_spef -path u_qspi_master ../../spef/qspim_top.spef
+read_spef -path u_uart_i2c_usb_spi  ../../spef/uart_i2c_usb_spi_top.spef
+read_spef -path u_wb_host    ../../spef/wb_host.spef
 read_spef -path u_intercon   ../../spef/wb_interconnect.spef
 read_spef ../..//spef/user_project_wrapper.spef  
 
@@ -76,27 +70,38 @@
 report_tns
 report_wns
 #report_power 
-echo "################ CORNER : WC (SLOW) TIMING Report ###################" > timing_max.rpt
-report_checks -unique -path_delay max -slack_max -0.0 -group_count 100 -corner wc >> timing_max.rpt
-report_checks -group_count 100 -path_delay max  -path_group $::env(WBM_CLOCK_NAME)       -corner wc  >> timing_max.rpt
-report_checks -group_count 100 -path_delay max  -path_group $::env(WBS_CLOCK_NAME)       -corner wc  >> timing_max.rpt
-report_checks -group_count 100 -path_delay max  -path_group $::env(SDRAM_CLOCK_NAME)     -corner wc  >> timing_max.rpt
-report_checks -group_count 100 -path_delay max  -path_group $::env(PAD_SDRAM_CLOCK_NAME) -corner wc  >> timing_max.rpt
-report_checks -group_count 100 -path_delay max  -path_group $::env(CPU_CLOCK_NAME)       -corner wc  >> timing_max.rpt
-report_checks -group_count 100 -path_delay max  -path_group $::env(RTC_CLOCK_NAME)       -corner wc  >> timing_max.rpt
 
-report_checks -path_delay max   -corner wc >> timing_max.rpt
+echo "################ CORNER : WC (SLOW) TIMING Report ###################" > timing_ss_max.rpt
+report_checks -unique -path_delay max -slack_max -0.0 -group_count 100 -corner wc >> timing_ss_max.rpt
+report_checks -group_count 100 -path_delay max  -path_group $::env(WBM_CLOCK_NAME)  -corner wc  >> timing_ss_max.rpt
+report_checks -group_count 100 -path_delay max  -path_group $::env(WBS_CLOCK_NAME)  -corner wc  >> timing_ss_max.rpt
+report_checks -group_count 100 -path_delay max  -path_group $::env(BIST_CLOCK_NAME) -corner wc  >> timing_ss_max.rpt
+report_checks -path_delay max   -corner wc >> timing_ff_max.rpt
 
-echo "################ CORNER : BC (SLOW) TIMING Report ###################" > timing_min.rpt
-report_checks -unique -path_delay min -slack_min -0.0 -group_count 100 -corner bc >> timing_min.rpt
-report_checks -group_count 100  -path_delay min -path_group $::env(WBM_CLOCK_NAME)        -corner bc  >> timing_min.rpt
-report_checks -group_count 100  -path_delay min -path_group $::env(WBS_CLOCK_NAME)        -corner bc  >> timing_min.rpt
-report_checks -group_count 100  -path_delay min -path_group $::env(SDRAM_CLOCK_NAME)      -corner bc  >> timing_min.rpt
-report_checks -group_count 100  -path_delay min -path_group $::env(PAD_SDRAM_CLOCK_NAME)  -corner bc  >> timing_min.rpt
-report_checks -group_count 100  -path_delay min -path_group $::env(CPU_CLOCK_NAME)        -corner bc  >> timing_min.rpt
-report_checks -group_count 100  -path_delay min -path_group $::env(RTC_CLOCK_NAME)        -corner bc  >> timing_min.rpt
-
+echo "################ CORNER : BC (SLOW) TIMING Report ###################" > timing_ff_min.rpt
+report_checks -unique -path_delay min -slack_min -0.0 -group_count 100 -corner bc >> timing_ff_min.rpt
+report_checks -group_count 100  -path_delay min -path_group $::env(WBM_CLOCK_NAME)  -corner bc  >> timing_ff_min.rpt
+report_checks -group_count 100  -path_delay min -path_group $::env(WBS_CLOCK_NAME)  -corner bc  >> timing_ff_min.rpt
+report_checks -group_count 100  -path_delay min -path_group $::env(BIST_CLOCK_NAME) -corner bc  >> timing_ff_min.rpt
 report_checks -path_delay min  -corner bc >> timing_min.rpt
+
+echo "################ CORNER : TT (MAX) TIMING Report ###################" > timing_tt_max.rpt
+report_checks -unique -path_delay min -slack_min -0.0 -group_count 100 -corner tt >> timing_tt_max.rpt
+report_checks -group_count 100  -path_delay max -path_group $::env(WBM_CLOCK_NAME)  -corner tt  >> timing_tt_max.rpt
+report_checks -group_count 100  -path_delay max -path_group $::env(WBS_CLOCK_NAME)  -corner tt  >> timing_tt_max.rpt
+report_checks -group_count 100  -path_delay max -path_group $::env(BIST_CLOCK_NAME) -corner tt  >> timing_tt_max.rpt
+report_checks -path_delay min  -corner tt >> timing_min.rpt
+
+echo "################ CORNER : TT (MIN) TIMING Report ###################" > timing_tt_min.rpt
+report_checks -unique -path_delay min -slack_min -0.0 -group_count 100 -corner tt >> timing_tt_min.rpt
+report_checks -group_count 100  -path_delay min -path_group $::env(WBM_CLOCK_NAME)  -corner tt  >> timing_tt_min.rpt
+report_checks -group_count 100  -path_delay min -path_group $::env(WBS_CLOCK_NAME)  -corner tt  >> timing_tt_min.rpt
+report_checks -group_count 100  -path_delay min -path_group $::env(BIST_CLOCK_NAME) -corner tt  >> timing_tt_min.rpt
+report_checks -path_delay min  -corner tt >> timing_min.rpt
+
+
+
+
 report_checks -path_delay min_max 
 
 #exit
diff --git a/openlane/wb_host/config.tcl b/openlane/wb_host/config.tcl
index 47808f2..dfbb5a5 100755
--- a/openlane/wb_host/config.tcl
+++ b/openlane/wb_host/config.tcl
@@ -35,6 +35,7 @@
 
 # Local sources + no2usb sources
 set ::env(VERILOG_FILES) "\
+     $script_dir/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \
      $script_dir/../../verilog/rtl/wb_host/src/wb_host.sv \
      $script_dir/../../verilog/rtl/lib/async_fifo.sv      \
      $script_dir/../../verilog/rtl/lib/async_wb.sv        \
@@ -59,6 +60,7 @@
 set ::env(FP_SIZING) absolute
 set ::env(DIE_AREA) "0 0 500 200"
 
+set ::env(PL_TARGET_DENSITY) "0.40"
 
 # If you're going to use multiple power domains, then keep this disabled.
 set ::env(RUN_CVC) 1
@@ -80,7 +82,10 @@
 
 set ::env(GLB_RT_MAXLAYER) 5
 set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
-
 set ::env(DIODE_INSERTION_STRATEGY) 4
 
 
+set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
+set ::env(QUIT_ON_MAGIC_DRC) "1"
+set ::env(QUIT_ON_LVS_ERROR) "0"
+set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
diff --git a/openlane/wb_host/pin_order.cfg b/openlane/wb_host/pin_order.cfg
index 1b79571..bd6d303 100644
--- a/openlane/wb_host/pin_order.cfg
+++ b/openlane/wb_host/pin_order.cfg
@@ -137,7 +137,13 @@
 cfg_clk_ctrl1\[25\]
 cfg_clk_ctrl1\[24\]
 wbs_clk_i            400 0 4
+wbd_clk_wh
 wbs_clk_out   
+wbd_clk_int
+cfg_cska_wh\[3\]
+cfg_cska_wh\[2\]
+cfg_cska_wh\[1\]
+cfg_cska_wh\[0\]
 cpu_clk
 rtc_clk
 
diff --git a/openlane/wb_interconnect/config.tcl b/openlane/wb_interconnect/config.tcl
index 26b93c7..6f10112 100755
--- a/openlane/wb_interconnect/config.tcl
+++ b/openlane/wb_interconnect/config.tcl
@@ -36,6 +36,7 @@
 
 # Local sources + no2usb sources
 set ::env(VERILOG_FILES) "\
+        $script_dir/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \
         $script_dir/../../verilog/rtl/lib/wb_stagging.sv                \
         $script_dir/../../verilog/rtl/wb_interconnect/src/wb_arb.sv     \
         $script_dir/../../verilog/rtl/wb_interconnect/src/wb_interconnect.sv  \
@@ -43,6 +44,7 @@
 
 set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/syntacore/scr1/src/includes $script_dir/../../verilog/rtl/sdram_ctrl/src/defs ]
 
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
 set ::env(SDC_FILE) "$script_dir/base.sdc"
 set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
 
@@ -77,13 +79,17 @@
 set ::env(FP_IO_VEXTEND) 4
 set ::env(FP_IO_HEXTEND) 4
 
-set ::env(FP_PDN_VPITCH) 180
-set ::env(FP_PDN_HPITCH) 180
-set ::env(FP_PDN_VWIDTH) 3
-set ::env(FP_PDN_HWIDTH) 3
+set ::env(FP_PDN_VPITCH) 100
+set ::env(FP_PDN_HPITCH) 100
+set ::env(FP_PDN_VWIDTH) 5
+set ::env(FP_PDN_HWIDTH) 5
 
-
-set ::env(GLB_RT_MAXLAYER) 4
+set ::env(GLB_RT_MAXLAYER) 5
 set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
 set ::env(DIODE_INSERTION_STRATEGY) 4
 
+
+set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
+set ::env(QUIT_ON_MAGIC_DRC) "1"
+set ::env(QUIT_ON_LVS_ERROR) "0"
+set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
diff --git a/openlane/wb_interconnect/pin_order.cfg b/openlane/wb_interconnect/pin_order.cfg
index fe8cc0a..fdc7903 100644
--- a/openlane/wb_interconnect/pin_order.cfg
+++ b/openlane/wb_interconnect/pin_order.cfg
@@ -3,8 +3,14 @@
 #MANUAL_PLACE
 
 #E
-clk_i               0000 0 2
-rst_n               0000 1 2
+cfg_cska_wi\[3\]     000  0
+cfg_cska_wi\[2\]     
+cfg_cska_wi\[1\]     
+cfg_cska_wi\[0\] 
+wbd_clk_int
+wbd_clk_wi    
+clk_i               
+rst_n               
 
 
 #S
diff --git a/signoff/pinmux/OPENLANE_VERSION b/signoff/pinmux/OPENLANE_VERSION
index bb2743d..80c7664 100644
--- a/signoff/pinmux/OPENLANE_VERSION
+++ b/signoff/pinmux/OPENLANE_VERSION
@@ -1 +1 @@
-openlane 2021.10.08_02.00.18-4-gd052a91
+openlane N/A
diff --git a/signoff/pinmux/PDK_SOURCES b/signoff/pinmux/PDK_SOURCES
index 1bf005a..ca3684a 100644
--- a/signoff/pinmux/PDK_SOURCES
+++ b/signoff/pinmux/PDK_SOURCES
@@ -1,6 +1,6 @@
 -ne openlane 
-d052a918f4a46ddbae0ad09812f6cd0b8eb4a1e5
+8d686c081c2c9aefa16dbbd8ccf5bc8f4dcabc4b
 -ne skywater-pdk 
 c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
 -ne open_pdks 
-5cad4f87435ae7f4e17e50d9c66cd79ecc14e663
+14db32aa8ba330e88632ff3ad2ff52f4f4dae1ad
diff --git a/signoff/pinmux/final_summary_report.csv b/signoff/pinmux/final_summary_report.csv
index 2244e63..11b7043 100644
--- a/signoff/pinmux/final_summary_report.csv
+++ b/signoff/pinmux/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/pinmux,pinmux,pinmux,flow_completed,0h13m6s,0h10m18s,41992.0,0.25,20996.0,24.54,687.96,5249,0,0,0,0,0,0,0,1,0,-1,-1,359665,53587,-1.51,-3.72,-0.77,-2.06,-3.83,-707.01,-3465.58,-26.11,-112.5,-256.78,281861115.0,1.92,35.04,30.5,5.79,0.83,-1,3127,7858,443,5174,0,0,0,3793,0,0,0,0,0,0,0,4,1147,1169,11,350,3274,0,3624,72.30657989877079,13.83,10,AREA 0,4,50,1,100,100,0.35,0.0,sky130_fd_sc_hd,4,4
+0,/project/openlane/pinmux,pinmux,pinmux,flow_completed,0h11m11s,-1,41056.0,0.25,20528.0,24.46,661.43,5132,0,0,0,0,0,0,0,1,0,-1,-1,325714,52551,-23.34,-24.15,-1,0.0,-1,-23658.53,-385.38,-1,0.0,-1,235745445.0,1.01,32.62,27.47,4.25,0.84,-1,3179,7916,495,5232,0,0,0,3823,0,0,0,0,0,0,0,4,1147,1169,12,350,3274,0,3624,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.35,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/qspim/OPENLANE_VERSION b/signoff/qspim/OPENLANE_VERSION
index bb2743d..80c7664 100644
--- a/signoff/qspim/OPENLANE_VERSION
+++ b/signoff/qspim/OPENLANE_VERSION
@@ -1 +1 @@
-openlane 2021.10.08_02.00.18-4-gd052a91
+openlane N/A
diff --git a/signoff/qspim/PDK_SOURCES b/signoff/qspim/PDK_SOURCES
index 1bf005a..ca3684a 100644
--- a/signoff/qspim/PDK_SOURCES
+++ b/signoff/qspim/PDK_SOURCES
@@ -1,6 +1,6 @@
 -ne openlane 
-d052a918f4a46ddbae0ad09812f6cd0b8eb4a1e5
+8d686c081c2c9aefa16dbbd8ccf5bc8f4dcabc4b
 -ne skywater-pdk 
 c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
 -ne open_pdks 
-5cad4f87435ae7f4e17e50d9c66cd79ecc14e663
+14db32aa8ba330e88632ff3ad2ff52f4f4dae1ad
diff --git a/signoff/qspim/final_summary_report.csv b/signoff/qspim/final_summary_report.csv
index 806f445..2d056a1 100644
--- a/signoff/qspim/final_summary_report.csv
+++ b/signoff/qspim/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/qspim,qspim_top,qspim,flow_completed,0h19m11s,0h15m54s,54669.23076923077,0.26,27334.615384615387,31.48,711.84,7107,0,0,0,0,0,0,0,1,0,-1,-1,341039,66217,-8.22,-8.65,-5.57,-7.03,-9.22,-379.27,-712.99,-470.98,-807.92,-1999.86,231043777.0,8.61,28.55,33.92,0.78,-1,23.3,5724,8664,385,3324,0,0,0,6822,0,0,0,0,0,0,0,4,1765,2184,20,460,3480,0,3940,52.02913631633715,19.22,10,AREA 0,4,50,1,100,100,0.4,0.0,sky130_fd_sc_hd,4,4
+0,/project/openlane/qspim,qspim_top,qspim,flow_completed,0h14m9s,-1,54792.30769230769,0.26,27396.153846153844,31.72,686.07,7123,0,0,0,0,0,0,0,1,0,-1,-1,340985,65638,-1.48,-4.83,-1,-1.39,-1,-21.2,-106.68,-1,-19.05,-1,231953260.0,15.19,28.66,33.67,0.77,0.54,-1,5828,8780,488,3439,0,0,0,6883,0,0,0,0,0,0,0,4,1765,2184,20,460,3480,0,3940,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.4,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/uart_i2cm_usb_spi/OPENLANE_VERSION b/signoff/uart_i2cm_usb_spi/OPENLANE_VERSION
index ba96224..80c7664 100644
--- a/signoff/uart_i2cm_usb_spi/OPENLANE_VERSION
+++ b/signoff/uart_i2cm_usb_spi/OPENLANE_VERSION
@@ -1 +1 @@
-openlane 2021.09.19_20.25.16
+openlane N/A
diff --git a/signoff/uart_i2cm_usb_spi/PDK_SOURCES b/signoff/uart_i2cm_usb_spi/PDK_SOURCES
index 4c20ce4..ca3684a 100644
--- a/signoff/uart_i2cm_usb_spi/PDK_SOURCES
+++ b/signoff/uart_i2cm_usb_spi/PDK_SOURCES
@@ -1,6 +1,6 @@
 -ne openlane 
-27752ec11a12afa3214f64401662683f081e2644
+8d686c081c2c9aefa16dbbd8ccf5bc8f4dcabc4b
 -ne skywater-pdk 
 c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
 -ne open_pdks 
-6c05bc48dc88784f9d98b89d6791cdfd91526676
+14db32aa8ba330e88632ff3ad2ff52f4f4dae1ad
diff --git a/signoff/uart_i2cm_usb_spi/final_summary_report.csv b/signoff/uart_i2cm_usb_spi/final_summary_report.csv
index 424576b..ff7d862 100644
--- a/signoff/uart_i2cm_usb_spi/final_summary_report.csv
+++ b/signoff/uart_i2cm_usb_spi/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/uart_i2cm_usb_spi,uart_i2c_usb_spi_top,uart_i2cm_usb_spi,flow_completed,0h18m54s,0h13m36s,52214.285714285725,0.42,26107.142857142862,29.25,869.61,10965,0,0,0,0,0,0,0,1,0,-1,-1,453057,94827,-6.6,-7.12,-6.33,-8.81,-11.23,-694.83,-825.18,-485.91,-1894.31,-4979.38,307076382.0,0.55,25.76,25.22,1.89,0.63,-1,8086,12517,1449,5823,0,0,0,9108,0,0,0,0,0,0,0,4,2535,2532,26,498,5647,0,6145,47.103155911446066,21.23,10,AREA 0,4,50,1,100,100,0.45,0.0,sky130_fd_sc_hd,4,4
+0,/project/openlane/uart_i2cm_usb_spi,uart_i2c_usb_spi_top,uart_i2cm_usb_spi,flow_completed,0h19m9s,-1,53419.04761904762,0.42,26709.52380952381,31.16,829.2,11218,0,0,0,0,0,0,0,1,0,-1,-1,419277,95582,-4.6,-9.16,-1,-5.04,-1,-3610.82,-5705.49,-1,-876.3,-1,263299489.0,0.0,25.63,22.82,0.71,0.04,-1,8572,12977,1537,5885,0,0,0,9748,0,0,0,0,0,0,0,4,2727,2691,24,498,5647,0,6145,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.45,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index 94dcd17..751751d 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h17m9s,-1,1.5566625155666252,10.2784,0.7783312577833126,-1,515.2,8,0,0,0,0,0,0,-1,0,2,-1,-1,1370232,5772,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,40150.48,1.9,5.04,1.03,2.01,-1,173,1812,172,1809,0,0,0,8,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,90.9090909090909,11,10,AREA 0,5,50,1,180,180,0.55,0.0,sky130_fd_sc_hd,4,0
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h17m41s,-1,1.5566625155666252,10.2784,0.7783312577833126,-1,513.77,8,0,0,0,0,0,0,-1,0,0,-1,-1,1245606,5189,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,40141.04,1.68,5.02,0.96,1.17,-1,166,1800,166,1800,0,0,0,8,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,90.9090909090909,11,10,AREA 0,5,50,1,180,180,0.55,0.0,sky130_fd_sc_hd,4,0
diff --git a/signoff/wb_host/OPENLANE_VERSION b/signoff/wb_host/OPENLANE_VERSION
index ba96224..80c7664 100644
--- a/signoff/wb_host/OPENLANE_VERSION
+++ b/signoff/wb_host/OPENLANE_VERSION
@@ -1 +1 @@
-openlane 2021.09.19_20.25.16
+openlane N/A
diff --git a/signoff/wb_host/PDK_SOURCES b/signoff/wb_host/PDK_SOURCES
index 4c20ce4..ca3684a 100644
--- a/signoff/wb_host/PDK_SOURCES
+++ b/signoff/wb_host/PDK_SOURCES
@@ -1,6 +1,6 @@
 -ne openlane 
-27752ec11a12afa3214f64401662683f081e2644
+8d686c081c2c9aefa16dbbd8ccf5bc8f4dcabc4b
 -ne skywater-pdk 
 c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
 -ne open_pdks 
-6c05bc48dc88784f9d98b89d6791cdfd91526676
+14db32aa8ba330e88632ff3ad2ff52f4f4dae1ad
diff --git a/signoff/wb_host/final_summary_report.csv b/signoff/wb_host/final_summary_report.csv
index fd1628d..c88fd76 100644
--- a/signoff/wb_host/final_summary_report.csv
+++ b/signoff/wb_host/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/wb_host,wb_host,wb_host,flow_completed,0h14m35s,0h13m13s,42500.0,0.1,21250.0,29.07,662.71,2125,0,0,0,0,0,0,0,41,0,0,-1,215024,28645,-1.52,-2.66,-1.41,-3.67,-4.33,-13.89,-136.29,-231.55,-927.15,-1231.73,108251432.0,0.0,47.2,37.88,24.92,1.26,-1,1166,2758,638,2228,0,0,0,1210,0,0,0,0,0,0,0,4,706,785,13,130,1239,0,1369,69.78367062107466,14.33,10,AREA 0,4,50,1,100,100,0.55,0.0,sky130_fd_sc_hd,4,4
+0,/project/openlane/wb_host,wb_host,wb_host,flow_completed,0h5m56s,-1,47800.0,0.1,23900.0,30.89,590.66,2390,0,0,0,0,0,0,0,1,0,0,-1,162389,25999,0.0,-0.76,-1,-1.06,-1,0.0,-20.47,-1,-196.0,-1,112356791.0,0.0,42.86,27.55,11.35,0.36,-1,1225,2833,697,2303,0,0,0,1250,0,0,0,0,0,0,0,4,724,811,13,130,1239,0,1369,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.4,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/wb_interconnect/OPENLANE_VERSION b/signoff/wb_interconnect/OPENLANE_VERSION
index bab6e84..80c7664 100644
--- a/signoff/wb_interconnect/OPENLANE_VERSION
+++ b/signoff/wb_interconnect/OPENLANE_VERSION
@@ -1 +1 @@
-openlane v0.21-9-g94fe743
+openlane N/A
diff --git a/signoff/wb_interconnect/PDK_SOURCES b/signoff/wb_interconnect/PDK_SOURCES
index 8b58bd5..ca3684a 100644
--- a/signoff/wb_interconnect/PDK_SOURCES
+++ b/signoff/wb_interconnect/PDK_SOURCES
@@ -1,6 +1,6 @@
 -ne openlane 
-a68c95289612a361870acedb7f6478fcfae32e49
+8d686c081c2c9aefa16dbbd8ccf5bc8f4dcabc4b
 -ne skywater-pdk 
-f6f76f3dc99526c6fc2cfede19b5b1227d4ebde7
+c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
 -ne open_pdks 
-522a373441a865fee9d6e3783015b4445f11afe6
+14db32aa8ba330e88632ff3ad2ff52f4f4dae1ad
diff --git a/signoff/wb_interconnect/final_summary_report.csv b/signoff/wb_interconnect/final_summary_report.csv
index 897ae64..823e5a5 100644
--- a/signoff/wb_interconnect/final_summary_report.csv
+++ b/signoff/wb_interconnect/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,Flow_completed,0h28m1s,0h5m22s,8218.181818181818,0.33,4109.090909090909,7,563.42,1356,0,0,0,0,0,0,0,0,0,-1,0,423449,18327,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,378093628,0.0,39.98,7.52,21.72,-1,-1,1079,1703,202,826,0,0,0,1356,240,0,73,15,135,0,0,176,447,431,11,94,3794,0,3888,100.0,10.0,10,AREA 0,4,50,1,180,180,0.5,0,sky130_fd_sc_hd,4,5
+0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,flow_completed,0h16m9s,-1,7460.606060606059,0.33,3730.3030303030296,3.76,628.56,1231,0,0,0,0,0,0,0,1,0,-1,-1,443240,22718,-4.39,-2.06,-1,-3.53,-1,-4.39,-2.06,-1,-58.37,-1,382865332.0,2.62,41.22,9.42,21.22,0.01,-1,848,2750,173,2075,0,0,0,1169,0,0,0,0,0,0,0,4,435,509,7,94,4140,0,4234,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.5,0.0,sky130_fd_sc_hd,4,4
diff --git a/verilog/dv/risc_boot/risc_boot_tb.v b/verilog/dv/risc_boot/risc_boot_tb.v
index 0d59657..fc50752 100644
--- a/verilog/dv/risc_boot/risc_boot_tb.v
+++ b/verilog/dv/risc_boot/risc_boot_tb.v
@@ -340,63 +340,63 @@
 `ifndef GL // Drive Power for Hold Fix Buf
     // All standard cell need power hook-up for functionality work
     initial begin
-	force uut.mprj.u_spi_master.u_delay1_sdio0.VPWR =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_delay1_sdio0.VPB  =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_delay1_sdio0.VGND =VSS;
-	force uut.mprj.u_spi_master.u_delay1_sdio0.VNB  = VSS;
-	force uut.mprj.u_spi_master.u_delay2_sdio0.VPWR =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_delay2_sdio0.VPB  =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_delay2_sdio0.VGND =VSS;
-	force uut.mprj.u_spi_master.u_delay2_sdio0.VNB  = VSS;
-	force uut.mprj.u_spi_master.u_buf_sdio0.VPWR    =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_buf_sdio0.VPB     =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_buf_sdio0.VGND    =VSS;
-	force uut.mprj.u_spi_master.u_buf_sdio0.VNB     =VSS;
+	force uut.mprj.u_qspi_master.u_delay1_sdio0.VPWR =USER_VDD1V8;
+	force uut.mprj.u_qspi_master.u_delay1_sdio0.VPB  =USER_VDD1V8;
+	force uut.mprj.u_qspi_master.u_delay1_sdio0.VGND =VSS;
+	force uut.mprj.u_qspi_master.u_delay1_sdio0.VNB  = VSS;
+	force uut.mprj.u_qspi_master.u_delay2_sdio0.VPWR =USER_VDD1V8;
+	force uut.mprj.u_qspi_master.u_delay2_sdio0.VPB  =USER_VDD1V8;
+	force uut.mprj.u_qspi_master.u_delay2_sdio0.VGND =VSS;
+	force uut.mprj.u_qspi_master.u_delay2_sdio0.VNB  = VSS;
+	force uut.mprj.u_qspi_master.u_buf_sdio0.VPWR    =USER_VDD1V8;
+	force uut.mprj.u_qspi_master.u_buf_sdio0.VPB     =USER_VDD1V8;
+	force uut.mprj.u_qspi_master.u_buf_sdio0.VGND    =VSS;
+	force uut.mprj.u_qspi_master.u_buf_sdio0.VNB     =VSS;
 
 
-	force uut.mprj.u_spi_master.u_delay1_sdio1.VPWR =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_delay1_sdio1.VPB  =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_delay1_sdio1.VGND =VSS;
-	force uut.mprj.u_spi_master.u_delay1_sdio1.VNB = VSS;
-	force uut.mprj.u_spi_master.u_delay2_sdio1.VPWR =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_delay2_sdio1.VPB  =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_delay2_sdio1.VGND =VSS;
-	force uut.mprj.u_spi_master.u_delay2_sdio1.VNB = VSS;
-	force uut.mprj.u_spi_master.u_buf_sdio1.VPWR    =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_buf_sdio1.VPB     =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_buf_sdio1.VGND    =VSS;
-	force uut.mprj.u_spi_master.u_buf_sdio1.VNB     =VSS;
+	force uut.mprj.u_qspi_master.u_delay1_sdio1.VPWR =USER_VDD1V8;
+	force uut.mprj.u_qspi_master.u_delay1_sdio1.VPB  =USER_VDD1V8;
+	force uut.mprj.u_qspi_master.u_delay1_sdio1.VGND =VSS;
+	force uut.mprj.u_qspi_master.u_delay1_sdio1.VNB = VSS;
+	force uut.mprj.u_qspi_master.u_delay2_sdio1.VPWR =USER_VDD1V8;
+	force uut.mprj.u_qspi_master.u_delay2_sdio1.VPB  =USER_VDD1V8;
+	force uut.mprj.u_qspi_master.u_delay2_sdio1.VGND =VSS;
+	force uut.mprj.u_qspi_master.u_delay2_sdio1.VNB = VSS;
+	force uut.mprj.u_qspi_master.u_buf_sdio1.VPWR    =USER_VDD1V8;
+	force uut.mprj.u_qspi_master.u_buf_sdio1.VPB     =USER_VDD1V8;
+	force uut.mprj.u_qspi_master.u_buf_sdio1.VGND    =VSS;
+	force uut.mprj.u_qspi_master.u_buf_sdio1.VNB     =VSS;
 
-	force uut.mprj.u_spi_master.u_delay1_sdio2.VPWR =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_delay1_sdio2.VPB  =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_delay1_sdio2.VGND =VSS;
-	force uut.mprj.u_spi_master.u_delay1_sdio2.VNB = VSS;
-	force uut.mprj.u_spi_master.u_delay2_sdio2.VPWR =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_delay2_sdio2.VPB  =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_delay2_sdio2.VGND =VSS;
-	force uut.mprj.u_spi_master.u_delay2_sdio2.VNB = VSS;
-	force uut.mprj.u_spi_master.u_buf_sdio2.VPWR    =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_buf_sdio2.VPB     =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_buf_sdio2.VGND    =VSS;
-	force uut.mprj.u_spi_master.u_buf_sdio2.VNB     =VSS;
+	force uut.mprj.u_qspi_master.u_delay1_sdio2.VPWR =USER_VDD1V8;
+	force uut.mprj.u_qspi_master.u_delay1_sdio2.VPB  =USER_VDD1V8;
+	force uut.mprj.u_qspi_master.u_delay1_sdio2.VGND =VSS;
+	force uut.mprj.u_qspi_master.u_delay1_sdio2.VNB = VSS;
+	force uut.mprj.u_qspi_master.u_delay2_sdio2.VPWR =USER_VDD1V8;
+	force uut.mprj.u_qspi_master.u_delay2_sdio2.VPB  =USER_VDD1V8;
+	force uut.mprj.u_qspi_master.u_delay2_sdio2.VGND =VSS;
+	force uut.mprj.u_qspi_master.u_delay2_sdio2.VNB = VSS;
+	force uut.mprj.u_qspi_master.u_buf_sdio2.VPWR    =USER_VDD1V8;
+	force uut.mprj.u_qspi_master.u_buf_sdio2.VPB     =USER_VDD1V8;
+	force uut.mprj.u_qspi_master.u_buf_sdio2.VGND    =VSS;
+	force uut.mprj.u_qspi_master.u_buf_sdio2.VNB     =VSS;
 
-	force uut.mprj.u_spi_master.u_delay1_sdio3.VPWR =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_delay1_sdio3.VPB  =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_delay1_sdio3.VGND =VSS;
-	force uut.mprj.u_spi_master.u_delay1_sdio3.VNB = VSS;
-	force uut.mprj.u_spi_master.u_delay2_sdio3.VPWR =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_delay2_sdio3.VPB  =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_delay2_sdio3.VGND =VSS;
-	force uut.mprj.u_spi_master.u_delay2_sdio3.VNB = VSS;
-	force uut.mprj.u_spi_master.u_buf_sdio3.VPWR    =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_buf_sdio3.VPB     =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_buf_sdio3.VGND    =VSS;
-	force uut.mprj.u_spi_master.u_buf_sdio3.VNB     =VSS;
+	force uut.mprj.u_qspi_master.u_delay1_sdio3.VPWR =USER_VDD1V8;
+	force uut.mprj.u_qspi_master.u_delay1_sdio3.VPB  =USER_VDD1V8;
+	force uut.mprj.u_qspi_master.u_delay1_sdio3.VGND =VSS;
+	force uut.mprj.u_qspi_master.u_delay1_sdio3.VNB = VSS;
+	force uut.mprj.u_qspi_master.u_delay2_sdio3.VPWR =USER_VDD1V8;
+	force uut.mprj.u_qspi_master.u_delay2_sdio3.VPB  =USER_VDD1V8;
+	force uut.mprj.u_qspi_master.u_delay2_sdio3.VGND =VSS;
+	force uut.mprj.u_qspi_master.u_delay2_sdio3.VNB = VSS;
+	force uut.mprj.u_qspi_master.u_buf_sdio3.VPWR    =USER_VDD1V8;
+	force uut.mprj.u_qspi_master.u_buf_sdio3.VPB     =USER_VDD1V8;
+	force uut.mprj.u_qspi_master.u_buf_sdio3.VGND    =VSS;
+	force uut.mprj.u_qspi_master.u_buf_sdio3.VNB     =VSS;
           
-	force uut.mprj.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VPWR =USER_VDD1V8;
-	force uut.mprj.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VPB  =USER_VDD1V8;
-	force uut.mprj.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VGND =VSS;
-	force uut.mprj.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VNB = VSS;
+	force uut.mprj.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VPWR =USER_VDD1V8;
+	force uut.mprj.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VPB  =USER_VDD1V8;
+	force uut.mprj.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VGND =VSS;
+	force uut.mprj.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VNB = VSS;
 
 	force uut.mprj.u_wb_host.u_buf_wb_rst.VPWR =USER_VDD1V8;
 	force uut.mprj.u_wb_host.u_buf_wb_rst.VPB  =USER_VDD1V8;
@@ -408,15 +408,15 @@
 	force uut.mprj.u_wb_host.u_buf_cpu_rst.VGND =VSS;
 	force uut.mprj.u_wb_host.u_buf_cpu_rst.VNB = VSS;
 
-	force uut.mprj.u_wb_host.u_buf_spi_rst.VPWR =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_buf_spi_rst.VPB  =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_buf_spi_rst.VGND =VSS;
-	force uut.mprj.u_wb_host.u_buf_spi_rst.VNB = VSS;
+	force uut.mprj.u_wb_host.u_buf_qspim_rst.VPWR =USER_VDD1V8;
+	force uut.mprj.u_wb_host.u_buf_qspim_rst.VPB  =USER_VDD1V8;
+	force uut.mprj.u_wb_host.u_buf_qspim_rst.VGND =VSS;
+	force uut.mprj.u_wb_host.u_buf_qspim_rst.VNB = VSS;
 
-	force uut.mprj.u_wb_host.u_buf_sdram_rst.VPWR =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_buf_sdram_rst.VPB  =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_buf_sdram_rst.VGND =VSS;
-	force uut.mprj.u_wb_host.u_buf_sdram_rst.VNB = VSS;
+	force uut.mprj.u_wb_host.u_buf_sspim_rst.VPWR =USER_VDD1V8;
+	force uut.mprj.u_wb_host.u_buf_sspim_rst.VPB  =USER_VDD1V8;
+	force uut.mprj.u_wb_host.u_buf_sspim_rst.VGND =VSS;
+	force uut.mprj.u_wb_host.u_buf_sspim_rst.VNB = VSS;
 
 	force uut.mprj.u_wb_host.u_buf_uart_rst.VPWR =USER_VDD1V8;
 	force uut.mprj.u_wb_host.u_buf_uart_rst.VPB  =USER_VDD1V8;
diff --git a/verilog/dv/user_i2cm/uprj_netlists.v b/verilog/dv/user_i2cm/uprj_netlists.v
deleted file mode 100644
index 0c7d867..0000000
--- a/verilog/dv/user_i2cm/uprj_netlists.v
+++ /dev/null
@@ -1,144 +0,0 @@
-// SPDX-FileCopyrightText: 2020 Efabless Corporation
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//      http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-
-// Include caravel global defines for the number of the user project IO pads 
-`include "defines.v"
-       `define USE_POWER_PINS
-       `define UNIT_DELAY #0.1
-
-`ifdef GL
-       `include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
-       `include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
-       `include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
-       `include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
-       `include "libs.ref//sky130_fd_sc_hd/verilog/sky130_ef_sc_hd__fakediode_2.v"
-
-        `include "glbl_cfg.v"
-        `include "sdram.v"
-        `include "spi_master.v"
-        `include "uart_i2cm_usb.v"
-        `include "wb_interconnect.v"
-        `include "user_project_wrapper.v"
-        `include "syntacore.v"
-        `include "wb_host.v"
-	`include "clk_skew_adjust.v"
-	`include "clk_buf.v"
-
-`else
-     `include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
-     `include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
-     `include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
-     `include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
-
-     `include"sar_adc/SAR.sv"
-     `include"sar_adc/ACMP.sv"
-     `include"sar_adc/sar_adc.sv"
-     `include"sar_adc/adc_reg.sv"
-     `include"sar_adc/DAC_8BIT.v"
-
-     `include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
-     `include "pinmux/src/pinmux.sv"
-     `include "pinmux/src/pinmux_reg.sv"
-     `include "pinmux/src/gpio_intr.sv"
-     `include "pinmux/src/pwm.sv"
-     `include "lib/pulse_gen_type1.sv"
-     `include "lib/pulse_gen_type2.sv"
-
-     `include "spi_master/src/spim_top.sv"
-     `include "spi_master/src/spim_if.sv"
-     `include "spi_master/src/spim_fifo.sv"
-     `include "spi_master/src/spim_regs.sv"
-     `include "spi_master/src/spim_clkgen.sv"
-     `include "spi_master/src/spim_ctrl.sv"
-     `include "spi_master/src/spim_rx.sv"
-     `include "spi_master/src/spim_tx.sv"
-
-     `include "uart/src/uart_core.sv"
-     `include "uart/src/uart_cfg.sv"
-     `include "uart/src/uart_rxfsm.sv"
-     `include "uart/src/uart_txfsm.sv"
-     `include "lib/async_fifo_th.sv"  
-     `include "lib/reset_sync.sv"  
-     `include "lib/double_sync_low.v"  
-     `include "lib/clk_buf.v"  
-
-     `include "i2cm/src/core/i2cm_bit_ctrl.v"
-     `include "i2cm/src/core/i2cm_byte_ctrl.v"
-     `include "i2cm/src/core/i2cm_top.v"
-
-     `include "usb1_host/src/core/usbh_core.sv"
-     `include "usb1_host/src/core/usbh_crc16.sv"
-     `include "usb1_host/src/core/usbh_crc5.sv"
-     `include "usb1_host/src/core/usbh_fifo.sv"
-     `include "usb1_host/src/core/usbh_sie.sv"
-     `include "usb1_host/src/phy/usb_fs_phy.v"
-     `include "usb1_host/src/phy/usb_transceiver.v"
-     `include "usb1_host/src/top/usb1_host.sv"
-
-     `include "uart_i2c_usb/src/uart_i2c_usb.sv"
-
-     `include "lib/registers.v"
-     `include "lib/clk_ctl.v"
-     `include "lib/async_fifo.sv"  
-     `include "digital_core/src/glbl_cfg.sv"
-
-     `include "wb_host/src/wb_host.sv"
-     `include "lib/async_wb.sv"
-
-     `include "lib/wb_stagging.sv"
-     `include "wb_interconnect/src/wb_arb.sv"
-     `include "wb_interconnect/src/wb_interconnect.sv"
-
-
-     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_hdu.sv"
-     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_tdu.sv"
-     `include "syntacore/scr1/src/core/pipeline/scr1_ipic.sv"
-     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_csr.sv"
-     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_exu.sv"
-     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv"
-     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_idu.sv"
-     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_ifu.sv"
-     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_lsu.sv"
-     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_mprf.sv"
-     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_mul.sv"
-     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_div.sv"
-     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_top.sv"
-     `include "syntacore/scr1/src/core/primitives/scr1_reset_cells.sv"
-     `include "syntacore/scr1/src/core/primitives/scr1_cg.sv"
-     `include "syntacore/scr1/src/core/scr1_clk_ctrl.sv"
-     `include "syntacore/scr1/src/core/scr1_tapc_shift_reg.sv"
-     `include "syntacore/scr1/src/core/scr1_tapc.sv"
-     `include "syntacore/scr1/src/core/scr1_tapc_synchronizer.sv"
-     `include "syntacore/scr1/src/core/scr1_core_top.sv"
-     `include "syntacore/scr1/src/core/scr1_dm.sv"
-     `include "syntacore/scr1/src/core/scr1_dmi.sv"
-     `include "syntacore/scr1/src/core/scr1_scu.sv"
-      
-     `include "syntacore/scr1/src/top/scr1_imem_router.sv"
-     `include "syntacore/scr1/src/top/scr1_dmem_router.sv"
-     `include "syntacore/scr1/src/top/scr1_dp_memory.sv"
-     `include "syntacore/scr1/src/top/scr1_tcm.sv"
-     `include "syntacore/scr1/src/top/scr1_timer.sv"
-     `include "syntacore/scr1/src/top/scr1_dmem_wb.sv"
-     `include "syntacore/scr1/src/top/scr1_imem_wb.sv"
-     `include "syntacore/scr1/src/top/scr1_intf.sv"
-     `include "syntacore/scr1/src/top/scr1_top_wb.sv"
-     `include "lib/sync_fifo.sv"
-
-     `include "user_project_wrapper.v"
-     // we are using netlist file for clk_skew_adjust as it has 
-     // standard cell + power pin
-     `include "gl/clk_skew_adjust.v"
-`endif
diff --git a/verilog/dv/user_i2cm/user_i2cm_tb.v b/verilog/dv/user_i2cm/user_i2cm_tb.v
index 825dfc2..d746df2 100644
--- a/verilog/dv/user_i2cm/user_i2cm_tb.v
+++ b/verilog/dv/user_i2cm/user_i2cm_tb.v
@@ -345,62 +345,62 @@
 `ifndef GL // Drive Power for Hold Fix Buf
     // All standard cell need power hook-up for functionality work
     initial begin
-	force u_top.u_spi_master.u_delay1_sdio0.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio0.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio0.VGND =VSS;
-	force u_top.u_spi_master.u_delay1_sdio0.VNB = VSS;
-	force u_top.u_spi_master.u_delay2_sdio0.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio0.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio0.VGND =VSS;
-	force u_top.u_spi_master.u_delay2_sdio0.VNB = VSS;
-	force u_top.u_spi_master.u_buf_sdio0.VPWR   =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio0.VPB    =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio0.VGND   =VSS;
-	force u_top.u_spi_master.u_buf_sdio0.VNB    =VSS;
+	force u_top.u_qspi_master.u_delay1_sdio0.VPWR =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay1_sdio0.VPB  =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay1_sdio0.VGND =VSS;
+	force u_top.u_qspi_master.u_delay1_sdio0.VNB = VSS;
+	force u_top.u_qspi_master.u_delay2_sdio0.VPWR =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay2_sdio0.VPB  =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay2_sdio0.VGND =VSS;
+	force u_top.u_qspi_master.u_delay2_sdio0.VNB = VSS;
+	force u_top.u_qspi_master.u_buf_sdio0.VPWR   =USER_VDD1V8;
+	force u_top.u_qspi_master.u_buf_sdio0.VPB    =USER_VDD1V8;
+	force u_top.u_qspi_master.u_buf_sdio0.VGND   =VSS;
+	force u_top.u_qspi_master.u_buf_sdio0.VNB    =VSS;
 
-	force u_top.u_spi_master.u_delay1_sdio1.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio1.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio1.VGND =VSS;
-	force u_top.u_spi_master.u_delay1_sdio1.VNB = VSS;
-	force u_top.u_spi_master.u_delay2_sdio1.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio1.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio1.VGND =VSS;
-	force u_top.u_spi_master.u_delay2_sdio1.VNB = VSS;
-	force u_top.u_spi_master.u_buf_sdio1.VPWR   =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio1.VPB    =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio1.VGND   =VSS;
-	force u_top.u_spi_master.u_buf_sdio1.VNB    =VSS;
+	force u_top.u_qspi_master.u_delay1_sdio1.VPWR =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay1_sdio1.VPB  =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay1_sdio1.VGND =VSS;
+	force u_top.u_qspi_master.u_delay1_sdio1.VNB = VSS;
+	force u_top.u_qspi_master.u_delay2_sdio1.VPWR =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay2_sdio1.VPB  =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay2_sdio1.VGND =VSS;
+	force u_top.u_qspi_master.u_delay2_sdio1.VNB = VSS;
+	force u_top.u_qspi_master.u_buf_sdio1.VPWR   =USER_VDD1V8;
+	force u_top.u_qspi_master.u_buf_sdio1.VPB    =USER_VDD1V8;
+	force u_top.u_qspi_master.u_buf_sdio1.VGND   =VSS;
+	force u_top.u_qspi_master.u_buf_sdio1.VNB    =VSS;
 
-	force u_top.u_spi_master.u_delay1_sdio2.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio2.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio2.VGND =VSS;
-	force u_top.u_spi_master.u_delay1_sdio2.VNB = VSS;
-	force u_top.u_spi_master.u_delay2_sdio2.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio2.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio2.VGND =VSS;
-	force u_top.u_spi_master.u_delay2_sdio2.VNB = VSS;
-	force u_top.u_spi_master.u_buf_sdio2.VPWR   =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio2.VPB    =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio2.VGND   =VSS;
-	force u_top.u_spi_master.u_buf_sdio2.VNB    =VSS;
+	force u_top.u_qspi_master.u_delay1_sdio2.VPWR =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay1_sdio2.VPB  =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay1_sdio2.VGND =VSS;
+	force u_top.u_qspi_master.u_delay1_sdio2.VNB = VSS;
+	force u_top.u_qspi_master.u_delay2_sdio2.VPWR =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay2_sdio2.VPB  =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay2_sdio2.VGND =VSS;
+	force u_top.u_qspi_master.u_delay2_sdio2.VNB = VSS;
+	force u_top.u_qspi_master.u_buf_sdio2.VPWR   =USER_VDD1V8;
+	force u_top.u_qspi_master.u_buf_sdio2.VPB    =USER_VDD1V8;
+	force u_top.u_qspi_master.u_buf_sdio2.VGND   =VSS;
+	force u_top.u_qspi_master.u_buf_sdio2.VNB    =VSS;
 
-	force u_top.u_spi_master.u_delay1_sdio3.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio3.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio3.VGND =VSS;
-	force u_top.u_spi_master.u_delay1_sdio3.VNB = VSS;
-	force u_top.u_spi_master.u_delay2_sdio3.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio3.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio3.VGND =VSS;
-	force u_top.u_spi_master.u_delay2_sdio3.VNB = VSS;
-	force u_top.u_spi_master.u_buf_sdio3.VPWR   =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio3.VPB    =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio3.VGND   =VSS;
-	force u_top.u_spi_master.u_buf_sdio3.VNB    =VSS;
+	force u_top.u_qspi_master.u_delay1_sdio3.VPWR =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay1_sdio3.VPB  =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay1_sdio3.VGND =VSS;
+	force u_top.u_qspi_master.u_delay1_sdio3.VNB = VSS;
+	force u_top.u_qspi_master.u_delay2_sdio3.VPWR =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay2_sdio3.VPB  =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay2_sdio3.VGND =VSS;
+	force u_top.u_qspi_master.u_delay2_sdio3.VNB = VSS;
+	force u_top.u_qspi_master.u_buf_sdio3.VPWR   =USER_VDD1V8;
+	force u_top.u_qspi_master.u_buf_sdio3.VPB    =USER_VDD1V8;
+	force u_top.u_qspi_master.u_buf_sdio3.VGND   =VSS;
+	force u_top.u_qspi_master.u_buf_sdio3.VNB    =VSS;
           
-	force u_top.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VPWR =USER_VDD1V8;
-	force u_top.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VPB  =USER_VDD1V8;
-	force u_top.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VGND =VSS;
-	force u_top.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VNB = VSS;
+	force u_top.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VPWR =USER_VDD1V8;
+	force u_top.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VPB  =USER_VDD1V8;
+	force u_top.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VGND =VSS;
+	force u_top.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VNB = VSS;
 
 	force u_top.u_wb_host.u_buf_wb_rst.VPWR =USER_VDD1V8;
 	force u_top.u_wb_host.u_buf_wb_rst.VPB  =USER_VDD1V8;
@@ -412,15 +412,15 @@
 	force u_top.u_wb_host.u_buf_cpu_rst.VGND =VSS;
 	force u_top.u_wb_host.u_buf_cpu_rst.VNB = VSS;
 
-	force u_top.u_wb_host.u_buf_spi_rst.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_spi_rst.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_spi_rst.VGND =VSS;
-	force u_top.u_wb_host.u_buf_spi_rst.VNB = VSS;
+	force u_top.u_wb_host.u_buf_qspim_rst.VPWR =USER_VDD1V8;
+	force u_top.u_wb_host.u_buf_qspim_rst.VPB  =USER_VDD1V8;
+	force u_top.u_wb_host.u_buf_qspim_rst.VGND =VSS;
+	force u_top.u_wb_host.u_buf_qspim_rst.VNB = VSS;
 
-	force u_top.u_wb_host.u_buf_sdram_rst.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_sdram_rst.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_sdram_rst.VGND =VSS;
-	force u_top.u_wb_host.u_buf_sdram_rst.VNB = VSS;
+	force u_top.u_wb_host.u_buf_sspim_rst.VPWR =USER_VDD1V8;
+	force u_top.u_wb_host.u_buf_sspim_rst.VPB  =USER_VDD1V8;
+	force u_top.u_wb_host.u_buf_sspim_rst.VGND =VSS;
+	force u_top.u_wb_host.u_buf_sspim_rst.VNB = VSS;
 
 	force u_top.u_wb_host.u_buf_uart_rst.VPWR =USER_VDD1V8;
 	force u_top.u_wb_host.u_buf_uart_rst.VPB  =USER_VDD1V8;
diff --git a/verilog/dv/user_risc_boot/uprj_netlists.v b/verilog/dv/user_risc_boot/uprj_netlists.v
deleted file mode 100644
index 0c7d867..0000000
--- a/verilog/dv/user_risc_boot/uprj_netlists.v
+++ /dev/null
@@ -1,144 +0,0 @@
-// SPDX-FileCopyrightText: 2020 Efabless Corporation
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//      http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-
-// Include caravel global defines for the number of the user project IO pads 
-`include "defines.v"
-       `define USE_POWER_PINS
-       `define UNIT_DELAY #0.1
-
-`ifdef GL
-       `include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
-       `include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
-       `include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
-       `include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
-       `include "libs.ref//sky130_fd_sc_hd/verilog/sky130_ef_sc_hd__fakediode_2.v"
-
-        `include "glbl_cfg.v"
-        `include "sdram.v"
-        `include "spi_master.v"
-        `include "uart_i2cm_usb.v"
-        `include "wb_interconnect.v"
-        `include "user_project_wrapper.v"
-        `include "syntacore.v"
-        `include "wb_host.v"
-	`include "clk_skew_adjust.v"
-	`include "clk_buf.v"
-
-`else
-     `include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
-     `include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
-     `include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
-     `include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
-
-     `include"sar_adc/SAR.sv"
-     `include"sar_adc/ACMP.sv"
-     `include"sar_adc/sar_adc.sv"
-     `include"sar_adc/adc_reg.sv"
-     `include"sar_adc/DAC_8BIT.v"
-
-     `include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
-     `include "pinmux/src/pinmux.sv"
-     `include "pinmux/src/pinmux_reg.sv"
-     `include "pinmux/src/gpio_intr.sv"
-     `include "pinmux/src/pwm.sv"
-     `include "lib/pulse_gen_type1.sv"
-     `include "lib/pulse_gen_type2.sv"
-
-     `include "spi_master/src/spim_top.sv"
-     `include "spi_master/src/spim_if.sv"
-     `include "spi_master/src/spim_fifo.sv"
-     `include "spi_master/src/spim_regs.sv"
-     `include "spi_master/src/spim_clkgen.sv"
-     `include "spi_master/src/spim_ctrl.sv"
-     `include "spi_master/src/spim_rx.sv"
-     `include "spi_master/src/spim_tx.sv"
-
-     `include "uart/src/uart_core.sv"
-     `include "uart/src/uart_cfg.sv"
-     `include "uart/src/uart_rxfsm.sv"
-     `include "uart/src/uart_txfsm.sv"
-     `include "lib/async_fifo_th.sv"  
-     `include "lib/reset_sync.sv"  
-     `include "lib/double_sync_low.v"  
-     `include "lib/clk_buf.v"  
-
-     `include "i2cm/src/core/i2cm_bit_ctrl.v"
-     `include "i2cm/src/core/i2cm_byte_ctrl.v"
-     `include "i2cm/src/core/i2cm_top.v"
-
-     `include "usb1_host/src/core/usbh_core.sv"
-     `include "usb1_host/src/core/usbh_crc16.sv"
-     `include "usb1_host/src/core/usbh_crc5.sv"
-     `include "usb1_host/src/core/usbh_fifo.sv"
-     `include "usb1_host/src/core/usbh_sie.sv"
-     `include "usb1_host/src/phy/usb_fs_phy.v"
-     `include "usb1_host/src/phy/usb_transceiver.v"
-     `include "usb1_host/src/top/usb1_host.sv"
-
-     `include "uart_i2c_usb/src/uart_i2c_usb.sv"
-
-     `include "lib/registers.v"
-     `include "lib/clk_ctl.v"
-     `include "lib/async_fifo.sv"  
-     `include "digital_core/src/glbl_cfg.sv"
-
-     `include "wb_host/src/wb_host.sv"
-     `include "lib/async_wb.sv"
-
-     `include "lib/wb_stagging.sv"
-     `include "wb_interconnect/src/wb_arb.sv"
-     `include "wb_interconnect/src/wb_interconnect.sv"
-
-
-     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_hdu.sv"
-     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_tdu.sv"
-     `include "syntacore/scr1/src/core/pipeline/scr1_ipic.sv"
-     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_csr.sv"
-     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_exu.sv"
-     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv"
-     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_idu.sv"
-     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_ifu.sv"
-     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_lsu.sv"
-     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_mprf.sv"
-     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_mul.sv"
-     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_div.sv"
-     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_top.sv"
-     `include "syntacore/scr1/src/core/primitives/scr1_reset_cells.sv"
-     `include "syntacore/scr1/src/core/primitives/scr1_cg.sv"
-     `include "syntacore/scr1/src/core/scr1_clk_ctrl.sv"
-     `include "syntacore/scr1/src/core/scr1_tapc_shift_reg.sv"
-     `include "syntacore/scr1/src/core/scr1_tapc.sv"
-     `include "syntacore/scr1/src/core/scr1_tapc_synchronizer.sv"
-     `include "syntacore/scr1/src/core/scr1_core_top.sv"
-     `include "syntacore/scr1/src/core/scr1_dm.sv"
-     `include "syntacore/scr1/src/core/scr1_dmi.sv"
-     `include "syntacore/scr1/src/core/scr1_scu.sv"
-      
-     `include "syntacore/scr1/src/top/scr1_imem_router.sv"
-     `include "syntacore/scr1/src/top/scr1_dmem_router.sv"
-     `include "syntacore/scr1/src/top/scr1_dp_memory.sv"
-     `include "syntacore/scr1/src/top/scr1_tcm.sv"
-     `include "syntacore/scr1/src/top/scr1_timer.sv"
-     `include "syntacore/scr1/src/top/scr1_dmem_wb.sv"
-     `include "syntacore/scr1/src/top/scr1_imem_wb.sv"
-     `include "syntacore/scr1/src/top/scr1_intf.sv"
-     `include "syntacore/scr1/src/top/scr1_top_wb.sv"
-     `include "lib/sync_fifo.sv"
-
-     `include "user_project_wrapper.v"
-     // we are using netlist file for clk_skew_adjust as it has 
-     // standard cell + power pin
-     `include "gl/clk_skew_adjust.v"
-`endif
diff --git a/verilog/dv/user_risc_boot/user_risc_boot_tb.v b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
index aeb9867..a320ab7 100644
--- a/verilog/dv/user_risc_boot/user_risc_boot_tb.v
+++ b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
@@ -247,62 +247,62 @@
 `ifndef GL // Drive Power for Hold Fix Buf
     // All standard cell need power hook-up for functionality work
     initial begin
-	force u_top.u_spi_master.u_delay1_sdio0.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio0.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio0.VGND =VSS;
-	force u_top.u_spi_master.u_delay1_sdio0.VNB = VSS;
-	force u_top.u_spi_master.u_delay2_sdio0.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio0.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio0.VGND =VSS;
-	force u_top.u_spi_master.u_delay2_sdio0.VNB = VSS;
-	force u_top.u_spi_master.u_buf_sdio0.VPWR   =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio0.VPB    =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio0.VGND   =VSS;
-	force u_top.u_spi_master.u_buf_sdio0.VNB    =VSS;
+	force u_top.u_qspi_master.u_delay1_sdio0.VPWR =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay1_sdio0.VPB  =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay1_sdio0.VGND =VSS;
+	force u_top.u_qspi_master.u_delay1_sdio0.VNB = VSS;
+	force u_top.u_qspi_master.u_delay2_sdio0.VPWR =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay2_sdio0.VPB  =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay2_sdio0.VGND =VSS;
+	force u_top.u_qspi_master.u_delay2_sdio0.VNB = VSS;
+	force u_top.u_qspi_master.u_buf_sdio0.VPWR   =USER_VDD1V8;
+	force u_top.u_qspi_master.u_buf_sdio0.VPB    =USER_VDD1V8;
+	force u_top.u_qspi_master.u_buf_sdio0.VGND   =VSS;
+	force u_top.u_qspi_master.u_buf_sdio0.VNB    =VSS;
 
-	force u_top.u_spi_master.u_delay1_sdio1.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio1.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio1.VGND =VSS;
-	force u_top.u_spi_master.u_delay1_sdio1.VNB = VSS;
-	force u_top.u_spi_master.u_delay2_sdio1.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio1.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio1.VGND =VSS;
-	force u_top.u_spi_master.u_delay2_sdio1.VNB = VSS;
-	force u_top.u_spi_master.u_buf_sdio1.VPWR   =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio1.VPB    =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio1.VGND   =VSS;
-	force u_top.u_spi_master.u_buf_sdio1.VNB    =VSS;
+	force u_top.u_qspi_master.u_delay1_sdio1.VPWR =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay1_sdio1.VPB  =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay1_sdio1.VGND =VSS;
+	force u_top.u_qspi_master.u_delay1_sdio1.VNB = VSS;
+	force u_top.u_qspi_master.u_delay2_sdio1.VPWR =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay2_sdio1.VPB  =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay2_sdio1.VGND =VSS;
+	force u_top.u_qspi_master.u_delay2_sdio1.VNB = VSS;
+	force u_top.u_qspi_master.u_buf_sdio1.VPWR   =USER_VDD1V8;
+	force u_top.u_qspi_master.u_buf_sdio1.VPB    =USER_VDD1V8;
+	force u_top.u_qspi_master.u_buf_sdio1.VGND   =VSS;
+	force u_top.u_qspi_master.u_buf_sdio1.VNB    =VSS;
 
-	force u_top.u_spi_master.u_delay1_sdio2.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio2.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio2.VGND =VSS;
-	force u_top.u_spi_master.u_delay1_sdio2.VNB = VSS;
-	force u_top.u_spi_master.u_delay2_sdio2.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio2.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio2.VGND =VSS;
-	force u_top.u_spi_master.u_delay2_sdio2.VNB = VSS;
-	force u_top.u_spi_master.u_buf_sdio2.VPWR   =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio2.VPB    =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio2.VGND   =VSS;
-	force u_top.u_spi_master.u_buf_sdio2.VNB    =VSS;
+	force u_top.u_qspi_master.u_delay1_sdio2.VPWR =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay1_sdio2.VPB  =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay1_sdio2.VGND =VSS;
+	force u_top.u_qspi_master.u_delay1_sdio2.VNB = VSS;
+	force u_top.u_qspi_master.u_delay2_sdio2.VPWR =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay2_sdio2.VPB  =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay2_sdio2.VGND =VSS;
+	force u_top.u_qspi_master.u_delay2_sdio2.VNB = VSS;
+	force u_top.u_qspi_master.u_buf_sdio2.VPWR   =USER_VDD1V8;
+	force u_top.u_qspi_master.u_buf_sdio2.VPB    =USER_VDD1V8;
+	force u_top.u_qspi_master.u_buf_sdio2.VGND   =VSS;
+	force u_top.u_qspi_master.u_buf_sdio2.VNB    =VSS;
 
-	force u_top.u_spi_master.u_delay1_sdio3.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio3.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio3.VGND =VSS;
-	force u_top.u_spi_master.u_delay1_sdio3.VNB = VSS;
-	force u_top.u_spi_master.u_delay2_sdio3.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio3.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio3.VGND =VSS;
-	force u_top.u_spi_master.u_delay2_sdio3.VNB = VSS;
-	force u_top.u_spi_master.u_buf_sdio3.VPWR   =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio3.VPB    =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio3.VGND   =VSS;
-	force u_top.u_spi_master.u_buf_sdio3.VNB    =VSS;
+	force u_top.u_qspi_master.u_delay1_sdio3.VPWR =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay1_sdio3.VPB  =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay1_sdio3.VGND =VSS;
+	force u_top.u_qspi_master.u_delay1_sdio3.VNB = VSS;
+	force u_top.u_qspi_master.u_delay2_sdio3.VPWR =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay2_sdio3.VPB  =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay2_sdio3.VGND =VSS;
+	force u_top.u_qspi_master.u_delay2_sdio3.VNB = VSS;
+	force u_top.u_qspi_master.u_buf_sdio3.VPWR   =USER_VDD1V8;
+	force u_top.u_qspi_master.u_buf_sdio3.VPB    =USER_VDD1V8;
+	force u_top.u_qspi_master.u_buf_sdio3.VGND   =VSS;
+	force u_top.u_qspi_master.u_buf_sdio3.VNB    =VSS;
           
-	force u_top.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VPWR =USER_VDD1V8;
-	force u_top.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VPB  =USER_VDD1V8;
-	force u_top.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VGND =VSS;
-	force u_top.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VNB = VSS;
+	force u_top.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VPWR =USER_VDD1V8;
+	force u_top.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VPB  =USER_VDD1V8;
+	force u_top.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VGND =VSS;
+	force u_top.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VNB = VSS;
 
 	force u_top.u_wb_host.u_buf_wb_rst.VPWR =USER_VDD1V8;
 	force u_top.u_wb_host.u_buf_wb_rst.VPB  =USER_VDD1V8;
@@ -314,15 +314,15 @@
 	force u_top.u_wb_host.u_buf_cpu_rst.VGND =VSS;
 	force u_top.u_wb_host.u_buf_cpu_rst.VNB = VSS;
 
-	force u_top.u_wb_host.u_buf_spi_rst.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_spi_rst.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_spi_rst.VGND =VSS;
-	force u_top.u_wb_host.u_buf_spi_rst.VNB = VSS;
+	force u_top.u_wb_host.u_buf_qspim_rst.VPWR =USER_VDD1V8;
+	force u_top.u_wb_host.u_buf_qspim_rst.VPB  =USER_VDD1V8;
+	force u_top.u_wb_host.u_buf_qspim_rst.VGND =VSS;
+	force u_top.u_wb_host.u_buf_qspim_rst.VNB = VSS;
 
-	force u_top.u_wb_host.u_buf_sdram_rst.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_sdram_rst.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_sdram_rst.VGND =VSS;
-	force u_top.u_wb_host.u_buf_sdram_rst.VNB = VSS;
+	force u_top.u_wb_host.u_buf_sspim_rst.VPWR =USER_VDD1V8;
+	force u_top.u_wb_host.u_buf_sspim_rst.VPB  =USER_VDD1V8;
+	force u_top.u_wb_host.u_buf_sspim_rst.VGND =VSS;
+	force u_top.u_wb_host.u_buf_sspim_rst.VNB = VSS;
 
 	force u_top.u_wb_host.u_buf_uart_rst.VPWR =USER_VDD1V8;
 	force u_top.u_wb_host.u_buf_uart_rst.VPB  =USER_VDD1V8;
diff --git a/verilog/dv/user_spi/uprj_netlists.v b/verilog/dv/user_spi/uprj_netlists.v
deleted file mode 100644
index 0c7d867..0000000
--- a/verilog/dv/user_spi/uprj_netlists.v
+++ /dev/null
@@ -1,144 +0,0 @@
-// SPDX-FileCopyrightText: 2020 Efabless Corporation
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//      http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-
-// Include caravel global defines for the number of the user project IO pads 
-`include "defines.v"
-       `define USE_POWER_PINS
-       `define UNIT_DELAY #0.1
-
-`ifdef GL
-       `include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
-       `include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
-       `include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
-       `include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
-       `include "libs.ref//sky130_fd_sc_hd/verilog/sky130_ef_sc_hd__fakediode_2.v"
-
-        `include "glbl_cfg.v"
-        `include "sdram.v"
-        `include "spi_master.v"
-        `include "uart_i2cm_usb.v"
-        `include "wb_interconnect.v"
-        `include "user_project_wrapper.v"
-        `include "syntacore.v"
-        `include "wb_host.v"
-	`include "clk_skew_adjust.v"
-	`include "clk_buf.v"
-
-`else
-     `include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
-     `include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
-     `include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
-     `include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
-
-     `include"sar_adc/SAR.sv"
-     `include"sar_adc/ACMP.sv"
-     `include"sar_adc/sar_adc.sv"
-     `include"sar_adc/adc_reg.sv"
-     `include"sar_adc/DAC_8BIT.v"
-
-     `include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
-     `include "pinmux/src/pinmux.sv"
-     `include "pinmux/src/pinmux_reg.sv"
-     `include "pinmux/src/gpio_intr.sv"
-     `include "pinmux/src/pwm.sv"
-     `include "lib/pulse_gen_type1.sv"
-     `include "lib/pulse_gen_type2.sv"
-
-     `include "spi_master/src/spim_top.sv"
-     `include "spi_master/src/spim_if.sv"
-     `include "spi_master/src/spim_fifo.sv"
-     `include "spi_master/src/spim_regs.sv"
-     `include "spi_master/src/spim_clkgen.sv"
-     `include "spi_master/src/spim_ctrl.sv"
-     `include "spi_master/src/spim_rx.sv"
-     `include "spi_master/src/spim_tx.sv"
-
-     `include "uart/src/uart_core.sv"
-     `include "uart/src/uart_cfg.sv"
-     `include "uart/src/uart_rxfsm.sv"
-     `include "uart/src/uart_txfsm.sv"
-     `include "lib/async_fifo_th.sv"  
-     `include "lib/reset_sync.sv"  
-     `include "lib/double_sync_low.v"  
-     `include "lib/clk_buf.v"  
-
-     `include "i2cm/src/core/i2cm_bit_ctrl.v"
-     `include "i2cm/src/core/i2cm_byte_ctrl.v"
-     `include "i2cm/src/core/i2cm_top.v"
-
-     `include "usb1_host/src/core/usbh_core.sv"
-     `include "usb1_host/src/core/usbh_crc16.sv"
-     `include "usb1_host/src/core/usbh_crc5.sv"
-     `include "usb1_host/src/core/usbh_fifo.sv"
-     `include "usb1_host/src/core/usbh_sie.sv"
-     `include "usb1_host/src/phy/usb_fs_phy.v"
-     `include "usb1_host/src/phy/usb_transceiver.v"
-     `include "usb1_host/src/top/usb1_host.sv"
-
-     `include "uart_i2c_usb/src/uart_i2c_usb.sv"
-
-     `include "lib/registers.v"
-     `include "lib/clk_ctl.v"
-     `include "lib/async_fifo.sv"  
-     `include "digital_core/src/glbl_cfg.sv"
-
-     `include "wb_host/src/wb_host.sv"
-     `include "lib/async_wb.sv"
-
-     `include "lib/wb_stagging.sv"
-     `include "wb_interconnect/src/wb_arb.sv"
-     `include "wb_interconnect/src/wb_interconnect.sv"
-
-
-     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_hdu.sv"
-     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_tdu.sv"
-     `include "syntacore/scr1/src/core/pipeline/scr1_ipic.sv"
-     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_csr.sv"
-     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_exu.sv"
-     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv"
-     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_idu.sv"
-     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_ifu.sv"
-     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_lsu.sv"
-     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_mprf.sv"
-     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_mul.sv"
-     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_div.sv"
-     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_top.sv"
-     `include "syntacore/scr1/src/core/primitives/scr1_reset_cells.sv"
-     `include "syntacore/scr1/src/core/primitives/scr1_cg.sv"
-     `include "syntacore/scr1/src/core/scr1_clk_ctrl.sv"
-     `include "syntacore/scr1/src/core/scr1_tapc_shift_reg.sv"
-     `include "syntacore/scr1/src/core/scr1_tapc.sv"
-     `include "syntacore/scr1/src/core/scr1_tapc_synchronizer.sv"
-     `include "syntacore/scr1/src/core/scr1_core_top.sv"
-     `include "syntacore/scr1/src/core/scr1_dm.sv"
-     `include "syntacore/scr1/src/core/scr1_dmi.sv"
-     `include "syntacore/scr1/src/core/scr1_scu.sv"
-      
-     `include "syntacore/scr1/src/top/scr1_imem_router.sv"
-     `include "syntacore/scr1/src/top/scr1_dmem_router.sv"
-     `include "syntacore/scr1/src/top/scr1_dp_memory.sv"
-     `include "syntacore/scr1/src/top/scr1_tcm.sv"
-     `include "syntacore/scr1/src/top/scr1_timer.sv"
-     `include "syntacore/scr1/src/top/scr1_dmem_wb.sv"
-     `include "syntacore/scr1/src/top/scr1_imem_wb.sv"
-     `include "syntacore/scr1/src/top/scr1_intf.sv"
-     `include "syntacore/scr1/src/top/scr1_top_wb.sv"
-     `include "lib/sync_fifo.sv"
-
-     `include "user_project_wrapper.v"
-     // we are using netlist file for clk_skew_adjust as it has 
-     // standard cell + power pin
-     `include "gl/clk_skew_adjust.v"
-`endif
diff --git a/verilog/dv/user_spi/user_spi_tb.v b/verilog/dv/user_spi/user_spi_tb.v
index 53b793f..f92c27a 100644
--- a/verilog/dv/user_spi/user_spi_tb.v
+++ b/verilog/dv/user_spi/user_spi_tb.v
@@ -1124,62 +1124,62 @@
 `ifndef GL // Drive Power for Hold Fix Buf
     // All standard cell need power hook-up for functionality work
     initial begin
-	force u_top.u_spi_master.u_delay1_sdio0.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio0.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio0.VGND =VSS;
-	force u_top.u_spi_master.u_delay1_sdio0.VNB = VSS;
-	force u_top.u_spi_master.u_delay2_sdio0.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio0.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio0.VGND =VSS;
-	force u_top.u_spi_master.u_delay2_sdio0.VNB = VSS;
-	force u_top.u_spi_master.u_buf_sdio0.VPWR   =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio0.VPB    =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio0.VGND   =VSS;
-	force u_top.u_spi_master.u_buf_sdio0.VNB    =VSS;
+	force u_top.u_qspi_master.u_delay1_sdio0.VPWR =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay1_sdio0.VPB  =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay1_sdio0.VGND =VSS;
+	force u_top.u_qspi_master.u_delay1_sdio0.VNB = VSS;
+	force u_top.u_qspi_master.u_delay2_sdio0.VPWR =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay2_sdio0.VPB  =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay2_sdio0.VGND =VSS;
+	force u_top.u_qspi_master.u_delay2_sdio0.VNB = VSS;
+	force u_top.u_qspi_master.u_buf_sdio0.VPWR   =USER_VDD1V8;
+	force u_top.u_qspi_master.u_buf_sdio0.VPB    =USER_VDD1V8;
+	force u_top.u_qspi_master.u_buf_sdio0.VGND   =VSS;
+	force u_top.u_qspi_master.u_buf_sdio0.VNB    =VSS;
 
-	force u_top.u_spi_master.u_delay1_sdio1.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio1.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio1.VGND =VSS;
-	force u_top.u_spi_master.u_delay1_sdio1.VNB = VSS;
-	force u_top.u_spi_master.u_delay2_sdio1.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio1.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio1.VGND =VSS;
-	force u_top.u_spi_master.u_delay2_sdio1.VNB = VSS;
-	force u_top.u_spi_master.u_buf_sdio1.VPWR   =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio1.VPB    =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio1.VGND   =VSS;
-	force u_top.u_spi_master.u_buf_sdio1.VNB    =VSS;
+	force u_top.u_qspi_master.u_delay1_sdio1.VPWR =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay1_sdio1.VPB  =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay1_sdio1.VGND =VSS;
+	force u_top.u_qspi_master.u_delay1_sdio1.VNB = VSS;
+	force u_top.u_qspi_master.u_delay2_sdio1.VPWR =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay2_sdio1.VPB  =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay2_sdio1.VGND =VSS;
+	force u_top.u_qspi_master.u_delay2_sdio1.VNB = VSS;
+	force u_top.u_qspi_master.u_buf_sdio1.VPWR   =USER_VDD1V8;
+	force u_top.u_qspi_master.u_buf_sdio1.VPB    =USER_VDD1V8;
+	force u_top.u_qspi_master.u_buf_sdio1.VGND   =VSS;
+	force u_top.u_qspi_master.u_buf_sdio1.VNB    =VSS;
 
-	force u_top.u_spi_master.u_delay1_sdio2.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio2.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio2.VGND =VSS;
-	force u_top.u_spi_master.u_delay1_sdio2.VNB = VSS;
-	force u_top.u_spi_master.u_delay2_sdio2.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio2.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio2.VGND =VSS;
-	force u_top.u_spi_master.u_delay2_sdio2.VNB = VSS;
-	force u_top.u_spi_master.u_buf_sdio2.VPWR   =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio2.VPB    =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio2.VGND   =VSS;
-	force u_top.u_spi_master.u_buf_sdio2.VNB    =VSS;
+	force u_top.u_qspi_master.u_delay1_sdio2.VPWR =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay1_sdio2.VPB  =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay1_sdio2.VGND =VSS;
+	force u_top.u_qspi_master.u_delay1_sdio2.VNB = VSS;
+	force u_top.u_qspi_master.u_delay2_sdio2.VPWR =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay2_sdio2.VPB  =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay2_sdio2.VGND =VSS;
+	force u_top.u_qspi_master.u_delay2_sdio2.VNB = VSS;
+	force u_top.u_qspi_master.u_buf_sdio2.VPWR   =USER_VDD1V8;
+	force u_top.u_qspi_master.u_buf_sdio2.VPB    =USER_VDD1V8;
+	force u_top.u_qspi_master.u_buf_sdio2.VGND   =VSS;
+	force u_top.u_qspi_master.u_buf_sdio2.VNB    =VSS;
 
-	force u_top.u_spi_master.u_delay1_sdio3.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio3.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio3.VGND =VSS;
-	force u_top.u_spi_master.u_delay1_sdio3.VNB = VSS;
-	force u_top.u_spi_master.u_delay2_sdio3.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio3.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio3.VGND =VSS;
-	force u_top.u_spi_master.u_delay2_sdio3.VNB = VSS;
-	force u_top.u_spi_master.u_buf_sdio3.VPWR   =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio3.VPB    =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio3.VGND   =VSS;
-	force u_top.u_spi_master.u_buf_sdio3.VNB    =VSS;
+	force u_top.u_qspi_master.u_delay1_sdio3.VPWR =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay1_sdio3.VPB  =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay1_sdio3.VGND =VSS;
+	force u_top.u_qspi_master.u_delay1_sdio3.VNB = VSS;
+	force u_top.u_qspi_master.u_delay2_sdio3.VPWR =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay2_sdio3.VPB  =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay2_sdio3.VGND =VSS;
+	force u_top.u_qspi_master.u_delay2_sdio3.VNB = VSS;
+	force u_top.u_qspi_master.u_buf_sdio3.VPWR   =USER_VDD1V8;
+	force u_top.u_qspi_master.u_buf_sdio3.VPB    =USER_VDD1V8;
+	force u_top.u_qspi_master.u_buf_sdio3.VGND   =VSS;
+	force u_top.u_qspi_master.u_buf_sdio3.VNB    =VSS;
           
-	force u_top.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VPWR =USER_VDD1V8;
-	force u_top.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VPB  =USER_VDD1V8;
-	force u_top.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VGND =VSS;
-	force u_top.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VNB = VSS;
+	force u_top.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VPWR =USER_VDD1V8;
+	force u_top.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VPB  =USER_VDD1V8;
+	force u_top.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VGND =VSS;
+	force u_top.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VNB = VSS;
 
 	force u_top.u_wb_host.u_buf_wb_rst.VPWR =USER_VDD1V8;
 	force u_top.u_wb_host.u_buf_wb_rst.VPB  =USER_VDD1V8;
@@ -1191,15 +1191,15 @@
 	force u_top.u_wb_host.u_buf_cpu_rst.VGND =VSS;
 	force u_top.u_wb_host.u_buf_cpu_rst.VNB = VSS;
 
-	force u_top.u_wb_host.u_buf_spi_rst.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_spi_rst.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_spi_rst.VGND =VSS;
-	force u_top.u_wb_host.u_buf_spi_rst.VNB = VSS;
+	force u_top.u_wb_host.u_buf_qspim_rst.VPWR =USER_VDD1V8;
+	force u_top.u_wb_host.u_buf_qspim_rst.VPB  =USER_VDD1V8;
+	force u_top.u_wb_host.u_buf_qspim_rst.VGND =VSS;
+	force u_top.u_wb_host.u_buf_qspim_rst.VNB = VSS;
 
-	force u_top.u_wb_host.u_buf_sdram_rst.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_sdram_rst.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_sdram_rst.VGND =VSS;
-	force u_top.u_wb_host.u_buf_sdram_rst.VNB = VSS;
+	force u_top.u_wb_host.u_buf_sspim_rst.VPWR =USER_VDD1V8;
+	force u_top.u_wb_host.u_buf_sspim_rst.VPB  =USER_VDD1V8;
+	force u_top.u_wb_host.u_buf_sspim_rst.VGND =VSS;
+	force u_top.u_wb_host.u_buf_sspim_rst.VNB = VSS;
 
 	force u_top.u_wb_host.u_buf_uart_rst.VPWR =USER_VDD1V8;
 	force u_top.u_wb_host.u_buf_uart_rst.VPB  =USER_VDD1V8;
diff --git a/verilog/dv/user_uart/uprj_netlists.v b/verilog/dv/user_uart/uprj_netlists.v
deleted file mode 100644
index 0c7d867..0000000
--- a/verilog/dv/user_uart/uprj_netlists.v
+++ /dev/null
@@ -1,144 +0,0 @@
-// SPDX-FileCopyrightText: 2020 Efabless Corporation
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//      http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-
-// Include caravel global defines for the number of the user project IO pads 
-`include "defines.v"
-       `define USE_POWER_PINS
-       `define UNIT_DELAY #0.1
-
-`ifdef GL
-       `include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
-       `include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
-       `include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
-       `include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
-       `include "libs.ref//sky130_fd_sc_hd/verilog/sky130_ef_sc_hd__fakediode_2.v"
-
-        `include "glbl_cfg.v"
-        `include "sdram.v"
-        `include "spi_master.v"
-        `include "uart_i2cm_usb.v"
-        `include "wb_interconnect.v"
-        `include "user_project_wrapper.v"
-        `include "syntacore.v"
-        `include "wb_host.v"
-	`include "clk_skew_adjust.v"
-	`include "clk_buf.v"
-
-`else
-     `include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
-     `include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
-     `include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
-     `include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
-
-     `include"sar_adc/SAR.sv"
-     `include"sar_adc/ACMP.sv"
-     `include"sar_adc/sar_adc.sv"
-     `include"sar_adc/adc_reg.sv"
-     `include"sar_adc/DAC_8BIT.v"
-
-     `include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
-     `include "pinmux/src/pinmux.sv"
-     `include "pinmux/src/pinmux_reg.sv"
-     `include "pinmux/src/gpio_intr.sv"
-     `include "pinmux/src/pwm.sv"
-     `include "lib/pulse_gen_type1.sv"
-     `include "lib/pulse_gen_type2.sv"
-
-     `include "spi_master/src/spim_top.sv"
-     `include "spi_master/src/spim_if.sv"
-     `include "spi_master/src/spim_fifo.sv"
-     `include "spi_master/src/spim_regs.sv"
-     `include "spi_master/src/spim_clkgen.sv"
-     `include "spi_master/src/spim_ctrl.sv"
-     `include "spi_master/src/spim_rx.sv"
-     `include "spi_master/src/spim_tx.sv"
-
-     `include "uart/src/uart_core.sv"
-     `include "uart/src/uart_cfg.sv"
-     `include "uart/src/uart_rxfsm.sv"
-     `include "uart/src/uart_txfsm.sv"
-     `include "lib/async_fifo_th.sv"  
-     `include "lib/reset_sync.sv"  
-     `include "lib/double_sync_low.v"  
-     `include "lib/clk_buf.v"  
-
-     `include "i2cm/src/core/i2cm_bit_ctrl.v"
-     `include "i2cm/src/core/i2cm_byte_ctrl.v"
-     `include "i2cm/src/core/i2cm_top.v"
-
-     `include "usb1_host/src/core/usbh_core.sv"
-     `include "usb1_host/src/core/usbh_crc16.sv"
-     `include "usb1_host/src/core/usbh_crc5.sv"
-     `include "usb1_host/src/core/usbh_fifo.sv"
-     `include "usb1_host/src/core/usbh_sie.sv"
-     `include "usb1_host/src/phy/usb_fs_phy.v"
-     `include "usb1_host/src/phy/usb_transceiver.v"
-     `include "usb1_host/src/top/usb1_host.sv"
-
-     `include "uart_i2c_usb/src/uart_i2c_usb.sv"
-
-     `include "lib/registers.v"
-     `include "lib/clk_ctl.v"
-     `include "lib/async_fifo.sv"  
-     `include "digital_core/src/glbl_cfg.sv"
-
-     `include "wb_host/src/wb_host.sv"
-     `include "lib/async_wb.sv"
-
-     `include "lib/wb_stagging.sv"
-     `include "wb_interconnect/src/wb_arb.sv"
-     `include "wb_interconnect/src/wb_interconnect.sv"
-
-
-     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_hdu.sv"
-     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_tdu.sv"
-     `include "syntacore/scr1/src/core/pipeline/scr1_ipic.sv"
-     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_csr.sv"
-     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_exu.sv"
-     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv"
-     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_idu.sv"
-     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_ifu.sv"
-     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_lsu.sv"
-     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_mprf.sv"
-     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_mul.sv"
-     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_div.sv"
-     `include "syntacore/scr1/src/core/pipeline/scr1_pipe_top.sv"
-     `include "syntacore/scr1/src/core/primitives/scr1_reset_cells.sv"
-     `include "syntacore/scr1/src/core/primitives/scr1_cg.sv"
-     `include "syntacore/scr1/src/core/scr1_clk_ctrl.sv"
-     `include "syntacore/scr1/src/core/scr1_tapc_shift_reg.sv"
-     `include "syntacore/scr1/src/core/scr1_tapc.sv"
-     `include "syntacore/scr1/src/core/scr1_tapc_synchronizer.sv"
-     `include "syntacore/scr1/src/core/scr1_core_top.sv"
-     `include "syntacore/scr1/src/core/scr1_dm.sv"
-     `include "syntacore/scr1/src/core/scr1_dmi.sv"
-     `include "syntacore/scr1/src/core/scr1_scu.sv"
-      
-     `include "syntacore/scr1/src/top/scr1_imem_router.sv"
-     `include "syntacore/scr1/src/top/scr1_dmem_router.sv"
-     `include "syntacore/scr1/src/top/scr1_dp_memory.sv"
-     `include "syntacore/scr1/src/top/scr1_tcm.sv"
-     `include "syntacore/scr1/src/top/scr1_timer.sv"
-     `include "syntacore/scr1/src/top/scr1_dmem_wb.sv"
-     `include "syntacore/scr1/src/top/scr1_imem_wb.sv"
-     `include "syntacore/scr1/src/top/scr1_intf.sv"
-     `include "syntacore/scr1/src/top/scr1_top_wb.sv"
-     `include "lib/sync_fifo.sv"
-
-     `include "user_project_wrapper.v"
-     // we are using netlist file for clk_skew_adjust as it has 
-     // standard cell + power pin
-     `include "gl/clk_skew_adjust.v"
-`endif
diff --git a/verilog/dv/user_uart/user_uart_tb.v b/verilog/dv/user_uart/user_uart_tb.v
index 0a0b207..b4020c8 100644
--- a/verilog/dv/user_uart/user_uart_tb.v
+++ b/verilog/dv/user_uart/user_uart_tb.v
@@ -289,62 +289,62 @@
 `ifndef GL // Drive Power for Hold Fix Buf
     // All standard cell need power hook-up for functionality work
     initial begin
-	force u_top.u_spi_master.u_delay1_sdio0.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio0.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio0.VGND =VSS;
-	force u_top.u_spi_master.u_delay1_sdio0.VNB = VSS;
-	force u_top.u_spi_master.u_delay2_sdio0.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio0.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio0.VGND =VSS;
-	force u_top.u_spi_master.u_delay2_sdio0.VNB = VSS;
-	force u_top.u_spi_master.u_buf_sdio0.VPWR   =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio0.VPB    =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio0.VGND   =VSS;
-	force u_top.u_spi_master.u_buf_sdio0.VNB    =VSS;
+	force u_top.u_qspi_master.u_delay1_sdio0.VPWR =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay1_sdio0.VPB  =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay1_sdio0.VGND =VSS;
+	force u_top.u_qspi_master.u_delay1_sdio0.VNB = VSS;
+	force u_top.u_qspi_master.u_delay2_sdio0.VPWR =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay2_sdio0.VPB  =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay2_sdio0.VGND =VSS;
+	force u_top.u_qspi_master.u_delay2_sdio0.VNB = VSS;
+	force u_top.u_qspi_master.u_buf_sdio0.VPWR   =USER_VDD1V8;
+	force u_top.u_qspi_master.u_buf_sdio0.VPB    =USER_VDD1V8;
+	force u_top.u_qspi_master.u_buf_sdio0.VGND   =VSS;
+	force u_top.u_qspi_master.u_buf_sdio0.VNB    =VSS;
 
-	force u_top.u_spi_master.u_delay1_sdio1.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio1.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio1.VGND =VSS;
-	force u_top.u_spi_master.u_delay1_sdio1.VNB = VSS;
-	force u_top.u_spi_master.u_delay2_sdio1.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio1.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio1.VGND =VSS;
-	force u_top.u_spi_master.u_delay2_sdio1.VNB = VSS;
-	force u_top.u_spi_master.u_buf_sdio1.VPWR   =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio1.VPB    =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio1.VGND   =VSS;
-	force u_top.u_spi_master.u_buf_sdio1.VNB    =VSS;
+	force u_top.u_qspi_master.u_delay1_sdio1.VPWR =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay1_sdio1.VPB  =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay1_sdio1.VGND =VSS;
+	force u_top.u_qspi_master.u_delay1_sdio1.VNB = VSS;
+	force u_top.u_qspi_master.u_delay2_sdio1.VPWR =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay2_sdio1.VPB  =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay2_sdio1.VGND =VSS;
+	force u_top.u_qspi_master.u_delay2_sdio1.VNB = VSS;
+	force u_top.u_qspi_master.u_buf_sdio1.VPWR   =USER_VDD1V8;
+	force u_top.u_qspi_master.u_buf_sdio1.VPB    =USER_VDD1V8;
+	force u_top.u_qspi_master.u_buf_sdio1.VGND   =VSS;
+	force u_top.u_qspi_master.u_buf_sdio1.VNB    =VSS;
 
-	force u_top.u_spi_master.u_delay1_sdio2.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio2.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio2.VGND =VSS;
-	force u_top.u_spi_master.u_delay1_sdio2.VNB = VSS;
-	force u_top.u_spi_master.u_delay2_sdio2.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio2.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio2.VGND =VSS;
-	force u_top.u_spi_master.u_delay2_sdio2.VNB = VSS;
-	force u_top.u_spi_master.u_buf_sdio2.VPWR   =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio2.VPB    =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio2.VGND   =VSS;
-	force u_top.u_spi_master.u_buf_sdio2.VNB    =VSS;
+	force u_top.u_qspi_master.u_delay1_sdio2.VPWR =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay1_sdio2.VPB  =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay1_sdio2.VGND =VSS;
+	force u_top.u_qspi_master.u_delay1_sdio2.VNB = VSS;
+	force u_top.u_qspi_master.u_delay2_sdio2.VPWR =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay2_sdio2.VPB  =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay2_sdio2.VGND =VSS;
+	force u_top.u_qspi_master.u_delay2_sdio2.VNB = VSS;
+	force u_top.u_qspi_master.u_buf_sdio2.VPWR   =USER_VDD1V8;
+	force u_top.u_qspi_master.u_buf_sdio2.VPB    =USER_VDD1V8;
+	force u_top.u_qspi_master.u_buf_sdio2.VGND   =VSS;
+	force u_top.u_qspi_master.u_buf_sdio2.VNB    =VSS;
 
-	force u_top.u_spi_master.u_delay1_sdio3.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio3.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio3.VGND =VSS;
-	force u_top.u_spi_master.u_delay1_sdio3.VNB = VSS;
-	force u_top.u_spi_master.u_delay2_sdio3.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio3.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio3.VGND =VSS;
-	force u_top.u_spi_master.u_delay2_sdio3.VNB = VSS;
-	force u_top.u_spi_master.u_buf_sdio3.VPWR   =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio3.VPB    =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio3.VGND   =VSS;
-	force u_top.u_spi_master.u_buf_sdio3.VNB    =VSS;
+	force u_top.u_qspi_master.u_delay1_sdio3.VPWR =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay1_sdio3.VPB  =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay1_sdio3.VGND =VSS;
+	force u_top.u_qspi_master.u_delay1_sdio3.VNB = VSS;
+	force u_top.u_qspi_master.u_delay2_sdio3.VPWR =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay2_sdio3.VPB  =USER_VDD1V8;
+	force u_top.u_qspi_master.u_delay2_sdio3.VGND =VSS;
+	force u_top.u_qspi_master.u_delay2_sdio3.VNB = VSS;
+	force u_top.u_qspi_master.u_buf_sdio3.VPWR   =USER_VDD1V8;
+	force u_top.u_qspi_master.u_buf_sdio3.VPB    =USER_VDD1V8;
+	force u_top.u_qspi_master.u_buf_sdio3.VGND   =VSS;
+	force u_top.u_qspi_master.u_buf_sdio3.VNB    =VSS;
           
-	force u_top.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VPWR =USER_VDD1V8;
-	force u_top.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VPB  =USER_VDD1V8;
-	force u_top.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VGND =VSS;
-	force u_top.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VNB = VSS;
+	force u_top.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VPWR =USER_VDD1V8;
+	force u_top.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VPB  =USER_VDD1V8;
+	force u_top.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VGND =VSS;
+	force u_top.u_uart_i2c_usb_spi.u_uart_core.u_lineclk_buf.VNB = VSS;
 
 	force u_top.u_wb_host.u_buf_wb_rst.VPWR =USER_VDD1V8;
 	force u_top.u_wb_host.u_buf_wb_rst.VPB  =USER_VDD1V8;
@@ -356,15 +356,15 @@
 	force u_top.u_wb_host.u_buf_cpu_rst.VGND =VSS;
 	force u_top.u_wb_host.u_buf_cpu_rst.VNB = VSS;
 
-	force u_top.u_wb_host.u_buf_spi_rst.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_spi_rst.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_spi_rst.VGND =VSS;
-	force u_top.u_wb_host.u_buf_spi_rst.VNB = VSS;
+	force u_top.u_wb_host.u_buf_qspim_rst.VPWR =USER_VDD1V8;
+	force u_top.u_wb_host.u_buf_qspim_rst.VPB  =USER_VDD1V8;
+	force u_top.u_wb_host.u_buf_qspim_rst.VGND =VSS;
+	force u_top.u_wb_host.u_buf_qspim_rst.VNB = VSS;
 
-	force u_top.u_wb_host.u_buf_sdram_rst.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_sdram_rst.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_sdram_rst.VGND =VSS;
-	force u_top.u_wb_host.u_buf_sdram_rst.VNB = VSS;
+	force u_top.u_wb_host.u_buf_sspim_rst.VPWR =USER_VDD1V8;
+	force u_top.u_wb_host.u_buf_sspim_rst.VPB  =USER_VDD1V8;
+	force u_top.u_wb_host.u_buf_sspim_rst.VGND =VSS;
+	force u_top.u_wb_host.u_buf_sspim_rst.VNB = VSS;
 
 	force u_top.u_wb_host.u_buf_uart_rst.VPWR =USER_VDD1V8;
 	force u_top.u_wb_host.u_buf_uart_rst.VPB  =USER_VDD1V8;
diff --git a/verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv b/verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv
index b826235..26f3fc6 100644
--- a/verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv
+++ b/verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv
@@ -75,7 +75,18 @@
 // Clock-in is east pad direction
 // clock out give in other three direction for better placement
 /////////////////////////////////////////////////////////////////////
-module clk_skew_adjust(clk_in, sel, clk_out);
+module clk_skew_adjust(
+`ifdef USE_POWER_PINS
+     vccd1,// User area 1 1.8V supply
+     vssd1,// User area 1 digital ground
+`endif
+clk_in, sel, clk_out);
+
+
+`ifdef USE_POWER_PINS
+     input vccd1;// User area 1 1.8V supply
+     input vssd1;// User area 1 digital ground
+`endif
   input  clk_in;
   output clk_out;
   input [3:0] sel;
diff --git a/verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.v b/verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.v
new file mode 100644
index 0000000..a961a50
--- /dev/null
+++ b/verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.v
@@ -0,0 +1,2898 @@
+module clk_skew_adjust (clk_in,
+    clk_out,
+    vccd1,
+    vssd1,
+    sel);
+ input clk_in;
+ output clk_out;
+ input vccd1;
+ input vssd1;
+ input [3:0] sel;
+
+ sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_1 (.A(clk_in),
+    .X(clk_d1),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_10 (.A(clk_d9),
+    .X(clk_d10),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_11 (.A(clk_d10),
+    .X(clk_d11),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_12 (.A(clk_d11),
+    .X(clk_d12),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_13 (.A(clk_d12),
+    .X(clk_d13),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_14 (.A(clk_d13),
+    .X(clk_d14),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_15 (.A(clk_d14),
+    .X(clk_d15),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_2 (.A(clk_d1),
+    .X(clk_d2),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_3 (.A(clk_d2),
+    .X(clk_d3),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_4 (.A(clk_d3),
+    .X(clk_d4),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_5 (.A(clk_d4),
+    .X(clk_d5),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_6 (.A(clk_d5),
+    .X(clk_d6),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_7 (.A(clk_d6),
+    .X(clk_d7),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_8 (.A(clk_d7),
+    .X(clk_d8),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__clkdlybuf4s15_2 clkbuf_9 (.A(clk_d8),
+    .X(clk_d9),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__mux2_1 u_mux_level_00 (.A0(clk_in),
+    .A1(clk_d1),
+    .S(sel[0]),
+    .X(d00),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__mux2_1 u_mux_level_01 (.A0(clk_d2),
+    .A1(clk_d3),
+    .S(sel[0]),
+    .X(d01),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__mux2_1 u_mux_level_02 (.A0(clk_d4),
+    .A1(clk_d5),
+    .S(sel[0]),
+    .X(d02),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__mux2_1 u_mux_level_03 (.A0(clk_d6),
+    .A1(clk_d7),
+    .S(sel[0]),
+    .X(d03),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__mux2_1 u_mux_level_04 (.A0(clk_d8),
+    .A1(clk_d9),
+    .S(sel[0]),
+    .X(d04),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__mux2_1 u_mux_level_05 (.A0(clk_d10),
+    .A1(clk_d11),
+    .S(sel[0]),
+    .X(d05),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__mux2_1 u_mux_level_06 (.A0(clk_d12),
+    .A1(clk_d13),
+    .S(sel[0]),
+    .X(d06),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__mux2_1 u_mux_level_07 (.A0(clk_d14),
+    .A1(clk_d15),
+    .S(sel[0]),
+    .X(d07),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__mux2_1 u_mux_level_10 (.A0(d00),
+    .A1(d01),
+    .S(sel[1]),
+    .X(d10),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__mux2_1 u_mux_level_11 (.A0(d02),
+    .A1(d03),
+    .S(sel[1]),
+    .X(d11),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__mux2_1 u_mux_level_12 (.A0(d04),
+    .A1(d05),
+    .S(sel[1]),
+    .X(d12),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__mux2_1 u_mux_level_13 (.A0(d06),
+    .A1(d07),
+    .S(sel[1]),
+    .X(d13),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__mux2_1 u_mux_level_20 (.A0(d10),
+    .A1(d11),
+    .S(sel[2]),
+    .X(d20),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__mux2_1 u_mux_level_21 (.A0(d12),
+    .A1(d13),
+    .S(sel[2]),
+    .X(d21),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__mux2_4 u_mux_level_30 (.A0(d20),
+    .A1(d21),
+    .S(sel[3]),
+    .X(clk_out),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_0 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_1 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_2 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_3 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_4 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_5 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_6 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_7 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_8 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_9 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_10 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_11 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_12 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_13 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_14 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_15 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_16 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_17 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_18 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_19 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_20 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_21 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_22 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_23 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_24 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_25 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_26 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_27 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_28 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_29 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_30 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_31 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_32 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_33 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_34 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_35 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_36 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_37 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_38 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_39 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_40 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_41 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_42 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_43 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_44 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_45 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_46 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_47 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_48 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_49 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_50 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_51 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_52 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_53 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_54 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_55 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_56 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_57 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_58 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_59 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_60 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_61 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_62 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 PHY_63 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_64 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_65 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_66 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_67 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_68 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_69 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_70 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_71 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_72 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_73 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_74 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_75 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_76 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_77 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_78 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_79 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_80 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_81 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_82 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_83 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_84 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_85 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_86 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_87 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_88 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_89 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_90 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_91 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_92 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_93 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_94 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_95 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_96 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_97 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_98 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_99 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_100 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_101 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_102 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_103 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_104 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_105 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_106 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_107 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_108 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_109 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_110 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_111 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_112 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_113 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_114 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_115 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_116 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_117 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_118 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_119 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_120 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_121 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_122 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_123 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_124 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_125 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_126 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_127 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_128 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_129 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_130 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_131 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_132 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_133 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_134 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_135 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_136 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_137 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_138 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_139 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_140 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_141 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_142 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_143 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_144 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_145 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_146 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_147 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_148 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_149 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_150 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_151 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_152 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_153 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_154 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_155 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_156 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_157 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_158 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_159 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_160 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_161 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_162 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_163 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_164 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__tapvpwrvgnd_1 PHY_165 (.VGND(vssd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_0_3 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_0_15 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_0_27 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_0_32 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_0_44 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_0_56 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_0_63 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_0_75 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_0_87 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_0_94 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_0_106 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_0_118 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_0_125 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_0_137 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_0_149 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_0_156 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_0_168 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_0_180 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 FILLER_0_187 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_3 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_15 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_1_27 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_32 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_44 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_56 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_68 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_80 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_93 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_105 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_117 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_129 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_141 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_154 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_166 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_1_178 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_3 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_15 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_27 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_39 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_2_51 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_2_59 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_62 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_74 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_86 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_98 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_110 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_123 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_135 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_147 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_159 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_2_171 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_2_184 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_3_3 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_3_15 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_3_27 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_3_32 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_3_44 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_3_56 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_3_68 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_3_80 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_3_93 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_3_105 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_3_117 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_3_129 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_3_141 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_3_154 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_3_166 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_3_178 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_4_3 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_4_15 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 FILLER_4_23 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_4_35 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_4_47 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_4_59 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_4_62 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_4_74 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_4_86 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_4_98 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_4_110 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_4_123 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_4_135 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_4_147 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_4_159 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_4_171 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_4_184 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_5_3 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_5_15 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_5_27 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_5_32 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_5_44 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_5_56 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_5_68 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_5_80 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_5_93 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_5_114 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_5_126 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 FILLER_5_134 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_5_146 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_5_152 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_5_154 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_5_166 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_5_178 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_6_3 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_6_15 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_6_27 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_6_39 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_6_51 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_6_59 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_6_62 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_6_74 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_6_86 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_6_98 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_6_110 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_6_123 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_6_135 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_6_147 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_6_159 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_6_171 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_6_184 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_7_3 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_7_15 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_7_27 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_7_32 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_7_44 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_7_56 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_7_68 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_7_80 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_7_102 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_7_114 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_7_126 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_7_138 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 FILLER_7_150 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_7_154 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_7_166 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_7_178 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_8_3 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_8_15 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_8_27 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_8_39 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_8_51 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_8_59 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_8_62 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_8_74 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_8_86 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_8_98 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_8_110 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_8_123 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_8_135 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_8_147 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_8_159 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_8_171 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_8_184 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_9_3 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_9_15 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_9_27 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_9_32 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_9_44 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_9_56 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 FILLER_9_64 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_9_76 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_9_88 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_9_93 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_9_105 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_9_117 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_9_129 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_9_141 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_9_154 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_9_166 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_9_183 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_9_189 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_10_3 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_10_15 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_10_27 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_10_39 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_10_51 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_10_59 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_10_62 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_10_74 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_10_86 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_10_98 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_10_110 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_10_123 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_10_135 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_10_147 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_10_159 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_10_171 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_10_184 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_11_3 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 FILLER_11_15 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_11_27 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_11_32 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_11_44 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_11_56 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_11_68 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_11_80 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_11_93 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_11_105 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_11_117 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_11_129 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_11_141 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_11_154 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_11_166 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 FILLER_11_174 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_11_186 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_12_3 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_12_15 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_12_27 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_12_39 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_12_51 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_12_59 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_12_62 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_12_74 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_12_86 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_12_98 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 FILLER_12_106 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_12_118 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_12_123 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_12_135 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_12_147 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_12_159 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_12_171 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_12_184 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_13_3 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_13_15 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_13_27 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_13_32 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_13_44 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_13_56 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_13_68 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_13_80 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_13_93 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_13_105 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_13_117 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_13_129 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_13_141 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_13_154 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_13_166 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_13_178 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_14_3 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_14_15 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_14_27 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_14_39 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_14_51 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_14_59 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_14_62 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_14_74 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_14_86 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_14_98 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_14_110 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_14_123 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_14_135 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_14_146 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_14_158 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_14_164 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_14_174 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_14_182 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_14_184 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_15_3 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_15_15 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_15_27 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_15_32 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_15_44 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_15_56 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_15_68 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_15_80 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_15_93 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_15_105 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_15_117 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_15_129 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_15_141 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_15_154 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_15_166 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_15_178 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_16_3 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_16_15 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_16_27 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_16_39 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_16_51 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_16_59 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_16_62 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_16_74 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_16_86 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_16_98 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_16_110 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_16_123 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_16_135 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_16_147 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_16_159 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_16_171 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_16_184 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_17_3 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_17_15 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_17_27 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_17_32 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_17_44 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_17_56 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_17_60 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_17_73 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_17_85 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_17_91 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_17_93 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_17_105 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_17_117 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_17_129 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_17_141 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_17_154 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_17_166 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 FILLER_17_174 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_17_186 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_18_3 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_18_15 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_18_27 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_18_40 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_18_52 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_18_60 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_18_62 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_18_74 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_18_86 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_18_98 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_18_110 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_18_123 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_18_135 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_18_147 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_18_159 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_18_171 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_18_184 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_19_3 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_19_15 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_19_27 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_19_32 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_19_44 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_19_56 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_19_68 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_19_80 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_19_93 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_19_105 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_19_117 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_19_129 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_19_141 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_19_154 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_19_166 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_19_178 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_20_3 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_20_15 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_20_27 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_20_39 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_20_51 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_20_59 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_20_62 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_20_74 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_20_86 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_20_98 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_20_110 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_20_123 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_20_135 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_20_147 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_20_159 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_20_171 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_20_184 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_21_12 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_21_24 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_21_30 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_21_32 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_21_44 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_21_56 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_21_68 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_21_80 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_21_93 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_21_105 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_21_117 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_21_129 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_21_141 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_21_154 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_21_166 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_21_179 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 FILLER_21_187 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_22_3 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_22_15 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_22_27 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_22_39 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_22_51 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_22_59 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_22_71 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_22_83 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_22_95 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_22_107 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 FILLER_22_119 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_22_132 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_22_144 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_22_156 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_22_168 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 FILLER_22_180 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_22_184 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_23_3 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_23_15 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_23_27 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_23_32 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_23_44 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_23_56 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_23_68 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_23_80 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_23_93 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_23_105 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_23_117 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_23_123 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_23_133 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_23_145 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_23_154 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_23_167 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_23_179 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 FILLER_23_187 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_24_3 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_24_15 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_24_27 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_24_39 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_24_51 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_24_59 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_24_62 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_24_74 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_24_86 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_24_98 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_24_110 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_24_123 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_24_135 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_24_147 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_24_159 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_24_171 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_24_184 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_25_12 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_25_24 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_25_30 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_25_32 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_25_44 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 FILLER_25_56 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_25_68 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_25_80 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_25_93 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_25_105 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_25_117 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_25_129 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_25_141 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_25_154 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_25_166 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 FILLER_25_174 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_25_186 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_26_3 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_26_15 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_26_27 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_26_39 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_26_51 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_26_59 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_26_62 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_26_74 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_26_86 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_26_98 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_26_110 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_26_123 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_26_135 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_26_147 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_26_159 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 FILLER_26_167 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_26_179 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_26_184 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_27_3 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_27_15 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_27_27 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_27_32 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_27_44 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_27_56 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_27_68 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_27_80 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_27_93 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_27_105 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_27_117 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_27_129 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_27_141 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_27_154 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_27_166 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_27_178 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_28_3 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_28_15 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_28_27 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_28_39 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_28_51 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_28_59 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_28_62 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_28_74 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_28_86 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_28_98 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_28_110 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_28_123 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_28_135 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_28_147 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_28_159 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_28_171 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_28_184 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_29_3 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_29_15 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_29_27 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_29_32 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_29_44 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_29_56 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_29_68 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 FILLER_29_76 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_29_88 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_29_93 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_29_105 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_29_117 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_29_129 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_29_141 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_29_154 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_29_166 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_29_181 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_29_189 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_30_3 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_30_15 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_30_27 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_30_39 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_30_51 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_30_59 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_30_62 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_30_74 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_30_86 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_30_98 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_2 FILLER_30_106 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_30_117 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_30_121 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_30_123 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_30_135 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_30_139 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_30_149 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_30_161 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_30_169 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_30_179 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_30_184 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_31_3 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_31_15 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_4 FILLER_31_27 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_31_32 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_31_44 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_31_56 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_31_63 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_31_75 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_31_87 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_31_94 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_31_106 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_31_118 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_31_125 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__fill_1 FILLER_31_137 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_8 FILLER_31_147 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_31_156 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_12 FILLER_31_168 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_6 FILLER_31_180 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__decap_3 FILLER_31_187 (.VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+endmodule
diff --git a/verilog/rtl/pinmux/src/pinmux.sv b/verilog/rtl/pinmux/src/pinmux.sv
index 09832ee..a64c442 100755
--- a/verilog/rtl/pinmux/src/pinmux.sv
+++ b/verilog/rtl/pinmux/src/pinmux.sv
@@ -1,4 +1,12 @@
 module pinmux (
+                    `ifdef USE_POWER_PINS
+                       input logic         vccd1,// User area 1 1.8V supply
+                       input logic         vssd1,// User area 1 digital ground
+                    `endif
+                        // clock skew adjust
+                       input logic [3:0]        cfg_cska_pinmux,
+                       input logic	        wbd_clk_int,
+                       output logic	        wbd_clk_pinmux,
                        // System Signals
                        // Inputs
 		       input logic             mclk,
@@ -35,12 +43,12 @@
 		       input  logic [3:0]      sflash_do,
 		       output logic [3:0]      sflash_di,
 
-		       // SSRAM I/F
-		       input  logic            ssram_sck,
-		       input  logic            ssram_ss,
-		       input  logic [3:0]      ssram_oen,
-		       input  logic [3:0]      ssram_do,
-		       output logic [3:0]      ssram_di,
+		       // SSRAM I/F - Temp Masked
+		       //input  logic            ssram_sck,
+		       //input  logic            ssram_ss,
+		       //input  logic [3:0]      ssram_oen,
+		       //input  logic [3:0]      ssram_do,
+		       //output logic [3:0]      ssram_di,
 
 		       // USB I/F
 		       input   logic           usb_dp_o,
@@ -137,6 +145,30 @@
 
 assign      pinmux_debug = '0; // Todo: Need to fix
 
+// SSRAM I/F - Temp masked
+//input  logic            ssram_sck,
+//input  logic            ssram_ss,
+//input  logic [3:0]      ssram_oen,
+//input  logic [3:0]      ssram_do,
+//output logic [3:0]      ssram_di,
+wire         ssram_sck = 1'b0;
+wire         ssram_ss = 1'b0;
+wire [3:0]   ssram_oen = 1'b0;
+wire [3:0]   ssram_do  = 4'b0;
+wire [3:0]   ssram_di;
+
+// pinmux clock skew control
+clk_skew_adjust u_skew_pinmux
+       (
+`ifdef USE_POWER_PINS
+               .vccd1      (vccd1                      ),// User area 1 1.8V supply
+               .vssd1      (vssd1                      ),// User area 1 digital ground
+`endif
+	       .clk_in     (wbd_clk_int                 ), 
+	       .sel        (cfg_cska_pinmux             ), 
+	       .clk_out    (wbd_clk_pinmux              ) 
+       );
+
 gpio_intr u_gpio_intr (
    // System Signals
    // Inputs
diff --git a/verilog/rtl/qspim/src/qspim_top.sv b/verilog/rtl/qspim/src/qspim_top.sv
index 036e8c8..d1b5823 100644
--- a/verilog/rtl/qspim/src/qspim_top.sv
+++ b/verilog/rtl/qspim/src/qspim_top.sv
@@ -68,6 +68,8 @@
 ////            to partial reading of data                        ////
 ////     V.4  -  July 26, 2021                                    ////
 ////             QDDR (0xED) supported is added                   ////
+////     V.5  -  Nov 6, 2021                                      ////
+////             Clock Skew Moves inside the block                ////
 ////                                                              ////
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
@@ -101,9 +103,17 @@
 module qspim_top
 #( parameter WB_WIDTH = 32)
 (
+`ifdef USE_POWER_PINS
+         input logic            vccd1,    // User area 1 1.8V supply
+         input logic            vssd1,    // User area 1 digital ground
+`endif
     input  logic                          mclk,
     input  logic                          rst_n,
 
+    input  logic   [3:0]                 cfg_cska_sp_co, // spi clock skew adjust
+    input  logic   [3:0]                 cfg_cska_spi,
+    input  logic                         wbd_clk_int,
+    output logic                         wbd_clk_spi,
 
     input  logic                         wbd_stb_i, // strobe/request
     input  logic   [WB_WIDTH-1:0]        wbd_adr_i, // address
@@ -216,7 +226,7 @@
 logic                          spi_en_tx;
 logic                          spi_init_done;
 logic  [3:0]                   spi_sdo_int;
-
+logic                          spi_clk_int;
 logic                          spi_sdo0_dl;
 logic                          spi_sdo1_dl;
 logic                          spi_sdo2_dl;
@@ -247,7 +257,29 @@
 assign   #1 spi_oen[2] =  (spi_mode == 0) ? 1 'b0 : !spi_en_tx;   // HOLD
 assign   #1 spi_oen[3] =  (spi_mode == 0) ? 1 'b0 : !spi_en_tx;   // 
 
+// spi clock skew control
+clk_skew_adjust u_skew_spi
+       (
+`ifdef USE_POWER_PINS
+               .vccd1      (vccd1                      ),// User area 1 1.8V supply
+               .vssd1      (vssd1                      ),// User area 1 digital ground
+`endif
+	       .clk_in     (wbd_clk_int                ), 
+	       .sel        (cfg_cska_spi               ), 
+	       .clk_out    (wbd_clk_spi                ) 
+       );
 
+// Clock Skey for SPI clock out
+clk_skew_adjust u_skew_sp_co
+       (
+`ifdef USE_POWER_PINS
+               .vccd1      (vccd1                      ),// User area 1 1.8V supply
+               .vssd1      (vssd1                      ),// User area 1 digital ground
+`endif
+	       .clk_in     (spi_clk_int                ), 
+	       .sel        (cfg_cska_sp_co             ), 
+	       .clk_out    (spi_clk                    ) 
+       );
 qspim_if #( .WB_WIDTH(WB_WIDTH)) u_wb_if(
         .mclk                           (mclk                         ),
         .rst_n                          (rst_n                        ),
@@ -455,7 +487,7 @@
 
 	.ctrl_state                     (ctrl_state                   ),
 
-        .spi_clk                        (spi_clk                      ),
+        .spi_clk                        (spi_clk_int                  ),
         .spi_csn0                       (spi_csn0                     ),
         .spi_csn1                       (spi_csn1                     ),
         .spi_csn2                       (spi_csn2                     ),
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv
index 5c5a927..913dd2c 100644
--- a/verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv
+++ b/verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv
@@ -88,6 +88,15 @@
 `endif // SCR1_TCM_EN
 
 module scr1_top_wb (
+
+`ifdef USE_POWER_PINS
+         input logic            vccd1,    // User area 1 1.8V supply
+         input logic            vssd1,    // User area 1 digital ground
+`endif
+    input  logic   [3:0]                 cfg_cska_riscv,
+    input  logic                         wbd_clk_int,
+    output logic                         wbd_clk_riscv,
+
     // Control
     input   logic                                   pwrup_rst_n,            // Power-Up Reset
     input   logic                                   rst_n,                  // Regular Reset signal
@@ -257,6 +266,17 @@
 logic [63:0]                                        timer_val;
 logic [48:0]                                        core_debug;
 
+// spi clock skew control
+clk_skew_adjust u_skew_riscv
+       (
+`ifdef USE_POWER_PINS
+               .vccd1      (vccd1                      ),// User area 1 1.8V supply
+               .vssd1      (vssd1                      ),// User area 1 digital ground
+`endif
+	       .clk_in     (wbd_clk_int                ), 
+	       .sel        (cfg_cska_riscv             ), 
+	       .clk_out    (wbd_clk_riscv              ) 
+       );
 //-------------------------------------------------------------------------------
 // SCR1 Intf instance
 //-------------------------------------------------------------------------------
diff --git a/verilog/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv b/verilog/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv
index 13555ae..d3378e0 100644
--- a/verilog/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv
+++ b/verilog/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv
@@ -66,6 +66,14 @@
 module uart_i2c_usb_spi_top 
 
      (  
+`ifdef USE_POWER_PINS
+   input logic         vccd1,// User area 1 1.8V supply
+   input logic         vssd1,// User area 1 digital ground
+`endif
+    // clock skew adjust
+   input logic [3:0]   cfg_cska_uart,
+   input logic	       wbd_clk_int,
+   output logic	       wbd_clk_uart,
 
    input logic         uart_rstn  , // async reset
    input logic         i2c_rstn  ,  // async reset
@@ -79,7 +87,7 @@
    input logic         reg_wr,
    input logic [7:0]   reg_addr,
    input logic [31:0]  reg_wdata,
-   input logic         reg_be,
+   input logic [3:0]   reg_be,
 
         // Outputs
    output logic [31:0] reg_rdata,
@@ -119,6 +127,17 @@
 
      );
 
+// uart clock skew control
+clk_skew_adjust u_skew_uart
+       (
+`ifdef USE_POWER_PINS
+               .vccd1      (vccd1                      ),// User area 1 1.8V supply
+               .vssd1      (vssd1                      ),// User area 1 digital ground
+`endif
+	       .clk_in     (wbd_clk_int                 ), 
+	       .sel        (cfg_cska_uart               ), 
+	       .clk_out    (wbd_clk_uart                ) 
+       );
 
 `define SEL_UART 2'b00
 `define SEL_I2C  2'b01
@@ -162,7 +181,7 @@
         .reg_wr      (reg_wr           ),
         .reg_addr    (reg_addr[5:2]    ),
         .reg_wdata   (reg_wdata[7:0]   ),
-        .reg_be      (reg_be           ),
+        .reg_be      (reg_be[0]        ),
 
         // Outputs
         .reg_rdata   (reg_uart_rdata[7:0]),
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index 3dc1964..2923dc3 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -146,5 +146,5 @@
      `include "user_project_wrapper.v"
      // we are using netlist file for clk_skew_adjust as it has 
      // standard cell + power pin
-     `include "gl/clk_skew_adjust.v"
+     `include "clk_skew_adjust/src/clk_skew_adjust.v"
 `endif
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 856c053..3e347ae 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -112,9 +112,11 @@
 ////          4. Added SAR ADC for 6 channel                      ////
 ////    1.3 - 30th Sept 2021, Dinesh.A                            ////
 ////          2KB SRAM Interface added to RISC Core               ////
-////                                                              ////
 ////    1.4 - 13th Oct 2021, Dinesh A                             ////
 ////          Basic verification and Synthesis cleanup            ////
+////    1.5 - 6th Nov 2021, Dinesh A                              ////
+////          Clock Skew block moved inside respective block due  ////
+//            to top-level power hook-up challenges for small IP  ////
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
 //// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
@@ -278,7 +280,7 @@
 wire   [31:0]                  wbd_uart_adr_o; // address
 wire                           wbd_uart_we_o;  // write
 wire   [31:0]                  wbd_uart_dat_o; // data output
-wire                           wbd_uart_sel_o; // byte enable
+wire   [3:0]                   wbd_uart_sel_o; // byte enable
 wire                           wbd_uart_cyc_o ;
 wire   [31:0]                  wbd_uart_dat_i; // data input
 wire                           wbd_uart_ack_i; // acknowlegement
@@ -299,6 +301,7 @@
 wire                              rtc_clk       ;
 wire                              usb_clk       ;
 wire                              wbd_clk_int   ;
+wire                              wbd_clk_pinmux   ;
 //wire                              wbd_clk_int1  ;
 //wire                              wbd_clk_int2  ;
 wire                              wbd_int_rst_n ;
@@ -316,11 +319,12 @@
 wire [3:0]                        cfg_cska_riscv; // clock skew adjust for riscv
 wire [3:0]                        cfg_cska_uart ; // clock skew adjust for uart
 wire [3:0]                        cfg_cska_spi  ; // clock skew adjust for spi
-wire [3:0]                        cfg_cska_sdram; // clock skew adjust for sdram
-wire [3:0]                        cfg_cska_glbl ; // clock skew adjust for global reg
+wire [3:0]                        cfg_cska_pinmux; // clock skew adjust for pinmux
+wire [3:0]                        cfg_cska_sp_co ; // clock skew adjust for global reg
 wire [3:0]                        cfg_cska_wh   ; // clock skew adjust for web host
 
 
+wire                              wbd_clk_wi    ; // clock for wishbone interconnect
 wire                              wbd_clk_riscv ; // clock for riscv
 wire                              wbd_clk_uart  ; // clock for uart
 wire                              wbd_clk_spi   ; // clock for spi
@@ -342,11 +346,11 @@
 wire [3:0]                       sflash_di           ;
 
 // SSRAM I/F
-wire                             ssram_sck           ;
-wire                             ssram_ss            ;
-wire                             ssram_oen           ;
-wire [3:0]                       ssram_do            ;
-wire [3:0]                       ssram_di            ;
+//wire                             ssram_sck           ;
+//wire                             ssram_ss            ;
+//wire                             ssram_oen           ;
+//wire [3:0]                       ssram_do            ;
+//wire [3:0]                       ssram_di            ;
 
 // USB I/F
 wire                             usb_dp_o            ;
@@ -406,17 +410,14 @@
 // Clock Skew Ctrl
 ////////////////////////////////////////////////////////
 
-assign cfg_cska_wi    = cfg_clk_ctrl1[3:0];
-assign cfg_cska_riscv = cfg_clk_ctrl1[7:4];
-assign cfg_cska_uart  = cfg_clk_ctrl1[11:8];
-assign cfg_cska_spi   = cfg_clk_ctrl1[15:12];
-assign cfg_cska_sdram = cfg_clk_ctrl1[19:16];
-assign cfg_cska_glbl  = cfg_clk_ctrl1[23:20];
-assign cfg_cska_wh    = cfg_clk_ctrl1[27:24];
+assign cfg_cska_wi     = cfg_clk_ctrl1[3:0];
+assign cfg_cska_riscv  = cfg_clk_ctrl1[7:4];
+assign cfg_cska_uart   = cfg_clk_ctrl1[11:8];
+assign cfg_cska_spi    = cfg_clk_ctrl1[15:12];
+assign cfg_cska_pinmux = cfg_clk_ctrl1[19:16];
+assign cfg_cska_wh     = cfg_clk_ctrl1[23:20];
+assign cfg_cska_sp_co  = cfg_clk_ctrl1[27:24];
 
-assign cfg_cska_sd_co = cfg_clk_ctrl2[3:0]; // SDRAM clock out control
-assign cfg_cska_sd_ci = cfg_clk_ctrl2[7:4]; // SDRAM clock in control
-assign cfg_cska_sp_co = cfg_clk_ctrl2[11:8];// SPI clock out control
 
 //assign la_data_out    = {riscv_debug,spi_debug,sdram_debug};
 assign la_data_out[127:0]    = {pinmux_debug,spi_debug,riscv_debug};
@@ -428,6 +429,10 @@
 //clk_buf u_buf2_wbclk    (.clk_i(wbd_clk_int1),.clk_o(wbd_clk_int2));
 
 wb_host u_wb_host(
+`ifdef USE_POWER_PINS
+    .vccd1                 (vccd1                    ),// User area 1 1.8V supply
+    .vssd1                 (vssd1                    ),// User area 1 digital ground
+`endif
        .user_clock1      (wb_clk_i             ),
        .user_clock2      (user_clock2          ),
 
@@ -458,9 +463,14 @@
        .wbm_ack_o        (wbs_ack_o            ),  
        .wbm_err_o        (                     ),  
 
+    // Clock Skeq Adjust
+       .wbd_clk_int      (wbd_clk_int          ),
+       .wbd_clk_wh       (wbd_clk_wh           ),  
+       .cfg_cska_wh      (cfg_cska_wh          ),
+
     // Slave Port
-       .wbs_clk_out      (wbd_clk_int          ),  
-       .wbs_clk_i        (wbd_clk_int           ),  
+       .wbs_clk_out      (wbd_clk_int          ),
+       .wbs_clk_i        (wbd_clk_wh           ),  
        .wbs_cyc_o        (wbd_int_cyc_i        ),  
        .wbs_stb_o        (wbd_int_stb_i        ),  
        .wbs_adr_o        (wbd_int_adr_i        ),  
@@ -483,6 +493,14 @@
 // RISC V Core instance
 //------------------------------------------------------------------------------
 scr1_top_wb u_riscv_top (
+`ifdef USE_POWER_PINS
+    .vccd1                 (vccd1                    ),// User area 1 1.8V supply
+    .vssd1                 (vssd1                    ),// User area 1 digital ground
+`endif
+    .wbd_clk_int           (wbd_clk_int               ), 
+    .cfg_cska_riscv        (cfg_cska_riscv            ), 
+    .wbd_clk_riscv         (wbd_clk_riscv             ),
+
     // Reset
     .pwrup_rst_n            (wbd_int_rst_n             ),
     .rst_n                  (wbd_int_rst_n             ),
@@ -520,7 +538,7 @@
 `endif
     
     .wb_rst_n               (wbd_int_rst_n             ),
-    .wb_clk                 (wbd_clk_int               ),
+    .wb_clk                 (wbd_clk_riscv             ),
     // Instruction memory interface
     .wbd_imem_stb_o         (wbd_riscv_imem_stb_i      ),
     .wbd_imem_adr_o         (wbd_riscv_imem_adr_i      ),
@@ -580,8 +598,18 @@
 `endif
 ) u_qspi_master
 (
-    .mclk                   (wbd_clk_int               ),
-    .rst_n                  (qspim_rst_n                 ),
+`ifdef USE_POWER_PINS
+         .vccd1         (vccd1                 ),// User area 1 1.8V supply
+         .vssd1         (vssd1                 ),// User area 1 digital ground
+`endif
+    .mclk                   (wbd_clk_spi               ),
+    .rst_n                  (qspim_rst_n               ),
+
+    // Clock Skew Adjust
+    .cfg_cska_sp_co         (cfg_cska_sp_co            ),
+    .cfg_cska_spi           (cfg_cska_spi              ),
+    .wbd_clk_int            (wbd_clk_int               ),
+    .wbd_clk_spi            (wbd_clk_spi               ),
 
     .wbd_stb_i              (wbd_spim_stb_o            ),
     .wbd_adr_i              (wbd_spim_adr_o            ),
@@ -606,7 +634,16 @@
 
 
 wb_interconnect  u_intercon (
-         .clk_i         (wbd_clk_int            ), 
+`ifdef USE_POWER_PINS
+         .vccd1         (vccd1                 ),// User area 1 1.8V supply
+         .vssd1         (vssd1                 ),// User area 1 digital ground
+`endif
+     // Clock Skew adjust
+	 .wbd_clk_int   (wbd_clk_int           ), 
+	 .cfg_cska_wi   (cfg_cska_wi           ), 
+	 .wbd_clk_wi    (wbd_clk_wi            ),
+
+         .clk_i         (wbd_clk_wi            ), 
          .rst_n         (wbd_int_rst_n         ),
 
          // Master 0 Interface
@@ -690,11 +727,19 @@
 
 
 uart_i2c_usb_spi_top   u_uart_i2c_usb_spi (
+`ifdef USE_POWER_PINS
+         .vccd1                 (vccd1                    ),// User area 1 1.8V supply
+         .vssd1                 (vssd1                    ),// User area 1 digital ground
+`endif
+	.wbd_clk_int            (wbd_clk_int              ), 
+	.cfg_cska_uart          (cfg_cska_uart            ), 
+	.wbd_clk_uart           (wbd_clk_uart             ),
+
         .uart_rstn              (uart_rst_n               ), // uart reset
         .i2c_rstn               (i2c_rst_n                ), // i2c reset
         .usb_rstn               (usb_rst_n                ), // USB reset
         .spi_rstn               (sspim_rst_n              ), // SPI reset
-        .app_clk                (wbd_clk_int              ),
+        .app_clk                (wbd_clk_uart             ),
 	.usb_clk                (usb_clk                  ),
 
         // Reg Bus Interface Signal
@@ -741,9 +786,18 @@
 
 
 pinmux u_pinmux(
+`ifdef USE_POWER_PINS
+         .vccd1         (vccd1                 ),// User area 1 1.8V supply
+         .vssd1         (vssd1                 ),// User area 1 digital ground
+`endif
+        //clk skew adjust
+        .cfg_cska_pinmux        (cfg_cska_pinmux           ),
+        .wbd_clk_int            (wbd_clk_int               ),
+        .wbd_clk_pinmux         (wbd_clk_pinmux            ),
+
         // System Signals
         // Inputs
-	.mclk                   (wbd_clk_int               ),
+	.mclk                   (wbd_clk_pinmux            ),
         .h_reset_n              (wbd_int_rst_n             ),
 
         // Reg Bus Interface Signal
@@ -778,12 +832,6 @@
         .sflash_do              (sflash_do                 ),
         .sflash_di              (sflash_di                 ),
 
-       // SSRAM I/F
-        .ssram_sck              (sflash_sck                ),
-        .ssram_ss               (sflash_ss                 ),
-        .ssram_oen              (sflash_oen                ),
-        .ssram_do               (sflash_do                 ),
-        .ssram_di               (                          ),
 
        // USB I/F
         .usb_dp_o               (usb_dp_o                  ),
@@ -819,8 +867,8 @@
 `ifdef USE_POWER_PINS
         .vccd1 (vccd1),// User area 1 1.8V supply
         .vssd1 (vssd1),// User area 1 digital ground
-        .vccd2 (vccd2),// User area 2 1.8V supply (analog)
-        .vssd2 (vssd2),// User area 2 ground      (analog)
+        .vccd2 (vccd1), // (vccd2),// User area 2 1.8V supply (analog) - DOTO: Need Fix
+        .vssd2 (vssd1), // (vssd2),// User area 2 ground      (analog) - DOTO: Need Fix
 `endif
 
     
diff --git a/verilog/rtl/wb_host/src/wb_host.sv b/verilog/rtl/wb_host/src/wb_host.sv
index 114ef20..2feeecb 100644
--- a/verilog/rtl/wb_host/src/wb_host.sv
+++ b/verilog/rtl/wb_host/src/wb_host.sv
@@ -99,6 +99,11 @@
        output  logic               wbm_ack_o        ,  // acknowlegement
        output  logic               wbm_err_o        ,  // error
 
+    // Clock Skew Adjust
+       input   logic               wbd_clk_int      , 
+       output  logic               wbd_clk_wh       ,
+       input   logic [3:0]         cfg_cska_wh      , // clock skew adjust for web host
+
     // Slave Port
        output  logic               wbs_clk_out      ,  // System clock
        input   logic               wbs_clk_i        ,  // System clock
@@ -166,6 +171,18 @@
 sky130_fd_sc_hd__bufbuf_16 u_buf_i2cm_rst      (.A(cfg_glb_ctrl[5]),.X(i2cm_rst_n));
 sky130_fd_sc_hd__bufbuf_16 u_buf_usb_rst       (.A(cfg_glb_ctrl[6]),.X(usb_rst_n));
 
+// wb_host clock skew control
+clk_skew_adjust u_skew_wh
+       (
+`ifdef USE_POWER_PINS
+               .vccd1      (vccd1                      ),// User area 1 1.8V supply
+               .vssd1      (vssd1                      ),// User area 1 digital ground
+`endif
+	       .clk_in     (wbd_clk_int               ), 
+	       .sel        (cfg_cska_wh               ), 
+	       .clk_out    (wbd_clk_wh                ) 
+       );
+
 
 // To reduce the load/Timing Wishbone I/F, Strobe is register to create
 // multi-cycle
@@ -255,8 +272,8 @@
 
 
 generic_register #(32,0  ) u_glb_ctrl (
-	      .we            ({24{sw_wr_en_0}}   ),		 
-	      .data_in       (wbm_dat_i[23:0]    ),
+	      .we            ({32{sw_wr_en_0}}   ),		 
+	      .data_in       (wbm_dat_i[31:0]    ),
 	      .reset_n       (wbm_rst_n         ),
 	      .clk           (wbm_clk_i         ),
 	      
diff --git a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
index c0e9bd7..ae60de7 100644
--- a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
+++ b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
@@ -52,6 +52,10 @@
 ////          m0: external host                                   ////
 ////          m1: risc imem                                       ////
 ////          m2: risc dmem                                       ////
+////   0.6 - 06 Nov 2021, Dinesh A                                ////
+////          Push the clock skew logic inside the block due to   ////
+////          global power hooking challanges for small block at  ////
+////          top level                                           ////
 ////                                                              ////
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
@@ -83,6 +87,16 @@
 
 
 module wb_interconnect(
+`ifdef USE_POWER_PINS
+         input logic            vccd1,    // User area 1 1.8V supply
+         input logic            vssd1,    // User area 1 digital ground
+`endif
+         // Clock Skew Adjust
+         input logic [3:0]      cfg_cska_wi,
+         input logic            wbd_clk_int,
+	 output logic           wbd_clk_wi,
+
+
          input logic		clk_i, 
          input logic            rst_n,
          
@@ -220,6 +234,17 @@
 type_wb_wr_intf  s_bus_wr;  // Multiplexed Master I/F
 type_wb_rd_intf  s_bus_rd;  // Multiplexed Slave I/F
 
+// Wishbone interconnect clock skew control
+clk_skew_adjust u_skew_wi
+       (
+`ifdef USE_POWER_PINS
+               .vccd1      (vccd1                      ),// User area 1 1.8V supply
+               .vssd1      (vssd1                      ),// User area 1 digital ground
+`endif
+	       .clk_in     (wbd_clk_int                 ), 
+	       .sel        (cfg_cska_wi                 ), 
+	       .clk_out    (wbd_clk_wi                  ) 
+       );
 
 //-------------------------------------------------------------------
 // EXTERNAL MEMORY MAP