[submodule "verilog/rtl/qspim"]
	path = verilog/rtl/qspim
	url = https://github.com/dineshannayya/qspim.git
[submodule "verilog/rtl/yifive/ycr1c"]
	path = verilog/rtl/yifive/ycr1c
	url = https://github.com/dineshannayya/ycr1cr.git
[submodule "verilog/dv/common/riscduino_board1"]
	path = verilog/dv/common/riscduino_board
	url = https://github.com/dineshannayya/riscduino_board.git