diff --git a/openlane/clk_buf/config.tcl b/openlane/clk_buf/config.tcl
index a4e28ab..bf8136d 100644
--- a/openlane/clk_buf/config.tcl
+++ b/openlane/clk_buf/config.tcl
@@ -45,7 +45,7 @@
 set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
 
 set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 30 30"
+set ::env(DIE_AREA) "0 0 60 100"
 
 
 
@@ -66,3 +66,8 @@
 set ::env(BOTTOM_MARGIN_MULT) 2
 set ::env(TOP_MARGIN_MULT) 2
 set ::env(GLB_RT_MAXLAYER) 4
+
+set ::env(FP_PDN_VPITCH) 30
+set ::env(FP_PDN_HPITCH) 30
+set ::env(FP_PDN_VWIDTH) 3
+set ::env(FP_PDN_HWIDTH) 3
diff --git a/openlane/clk_skew_adjust/config.tcl b/openlane/clk_skew_adjust/config.tcl
index df2b534..8ca04ee 100644
--- a/openlane/clk_skew_adjust/config.tcl
+++ b/openlane/clk_skew_adjust/config.tcl
@@ -44,8 +44,8 @@
 ### Macro Placement
 set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
 
-#set ::env(FP_SIZING) absolute
-#set ::env(DIE_AREA) "0 0 50 50"
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 100 100"
 
 
 
@@ -66,3 +66,8 @@
 set ::env(BOTTOM_MARGIN_MULT) 2
 set ::env(TOP_MARGIN_MULT) 2
 set ::env(GLB_RT_MAXLAYER) 4
+
+set ::env(FP_PDN_VPITCH) 30
+set ::env(FP_PDN_HPITCH) 30
+set ::env(FP_PDN_VWIDTH) 3
+set ::env(FP_PDN_HWIDTH) 3
diff --git a/openlane/glbl_cfg/config.tcl b/openlane/glbl_cfg/config.tcl
index 4848c00..0c4cbcf 100755
--- a/openlane/glbl_cfg/config.tcl
+++ b/openlane/glbl_cfg/config.tcl
@@ -76,3 +76,7 @@
 
 set ::env(DIODE_INSERTION_STRATEGY) 4
 
+set ::env(FP_PDN_VPITCH) 100
+set ::env(FP_PDN_HPITCH) 100
+set ::env(FP_PDN_VWIDTH) 3
+set ::env(FP_PDN_HWIDTH) 3
diff --git a/openlane/sdram/config.tcl b/openlane/sdram/config.tcl
index 230d1e6..9e75517 100755
--- a/openlane/sdram/config.tcl
+++ b/openlane/sdram/config.tcl
@@ -82,3 +82,7 @@
 set ::env(GLB_RT_MAXLAYER) 4
 set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
 
+set ::env(FP_PDN_VPITCH) 100
+set ::env(FP_PDN_HPITCH) 100
+set ::env(FP_PDN_VWIDTH) 3
+set ::env(FP_PDN_HWIDTH) 3
diff --git a/openlane/spi_master/base.sdc b/openlane/spi_master/base.sdc
index 129b737..10ad658 100644
--- a/openlane/spi_master/base.sdc
+++ b/openlane/spi_master/base.sdc
@@ -92,8 +92,8 @@
 set_output_delay 0   -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_oeb[2]]
 set_output_delay 0   -min -clock [get_clocks $::env(SPI_CLOCK_PORT)] [get_port io_oeb[1]]
 
-set_clock_uncertainty -from $::env(SPI_CLOCK_PORT)   -to $::env(SPI_CLOCK_PORT)   -setup 0.400
-set_clock_uncertainty -from $::env(WB_CLOCK_PERIOD)  -to $::env(WB_CLOCK_PERIOD)  -setup 0.400
+set_clock_uncertainty -from $::env(SPI_CLOCK_PORT)   -to $::env(SPI_CLOCK_PORT)   -setup 0.800
+set_clock_uncertainty -from $::env(WB_CLOCK_PERIOD)  -to $::env(WB_CLOCK_PERIOD)  -setup 0.800
 set_clock_uncertainty -from $::env(SPI_CLOCK_PORT)   -to $::env(SPI_CLOCK_PORT)   -hold 0.050
 set_clock_uncertainty -from $::env(WB_CLOCK_PERIOD)  -to $::env(WB_CLOCK_PERIOD)  -hold 0.050
 
diff --git a/openlane/spi_master/config.tcl b/openlane/spi_master/config.tcl
index ade6318..ec8bb96 100755
--- a/openlane/spi_master/config.tcl
+++ b/openlane/spi_master/config.tcl
@@ -79,3 +79,7 @@
 set ::env(GLB_RT_MAXLAYER) 4
 set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
 
+set ::env(FP_PDN_VPITCH) 100
+set ::env(FP_PDN_HPITCH) 100
+set ::env(FP_PDN_VWIDTH) 3
+set ::env(FP_PDN_HWIDTH) 3
diff --git a/openlane/syntacore/config.tcl b/openlane/syntacore/config.tcl
index ad5d9bb..9e01803 100755
--- a/openlane/syntacore/config.tcl
+++ b/openlane/syntacore/config.tcl
@@ -103,3 +103,7 @@
 
 #set ::env(LVS_CONNECT_BY_LABEL) 1
 
+set ::env(FP_PDN_VPITCH) 100
+set ::env(FP_PDN_HPITCH) 100
+set ::env(FP_PDN_VWIDTH) 3
+set ::env(FP_PDN_HWIDTH) 3
diff --git a/openlane/uart/config.tcl b/openlane/uart/config.tcl
index 0a94c66..818dec9 100644
--- a/openlane/uart/config.tcl
+++ b/openlane/uart/config.tcl
@@ -85,3 +85,7 @@
 
 set ::env(DIODE_INSERTION_STRATEGY) 4
 
+set ::env(FP_PDN_VPITCH) 100
+set ::env(FP_PDN_HPITCH) 100
+set ::env(FP_PDN_VWIDTH) 3
+set ::env(FP_PDN_HWIDTH) 3
diff --git a/openlane/user_project_wrapper/base.sdc b/openlane/user_project_wrapper/base.sdc
index 509c8cb..a65ed4e 100644
--- a/openlane/user_project_wrapper/base.sdc
+++ b/openlane/user_project_wrapper/base.sdc
@@ -50,10 +50,10 @@
 set_case_analysis 0 [get_pins -hierarchical u_skew_wi*sel[1]] 
 set_case_analysis 0 [get_pins -hierarchical u_skew_wi*sel[0]] 
 
-set_case_analysis 1 [get_pins -hierarchical u_skew_riscv*sel[3]]
-set_case_analysis 0 [get_pins -hierarchical u_skew_riscv*sel[2]]
-set_case_analysis 0 [get_pins -hierarchical u_skew_riscv*sel[1]]
-set_case_analysis 0 [get_pins -hierarchical u_skew_riscv*sel[0]]
+set_case_analysis 0 [get_pins -hierarchical u_skew_riscv*sel[3]]
+set_case_analysis 1 [get_pins -hierarchical u_skew_riscv*sel[2]]
+set_case_analysis 1 [get_pins -hierarchical u_skew_riscv*sel[1]]
+set_case_analysis 1 [get_pins -hierarchical u_skew_riscv*sel[0]]
 
 set_case_analysis 1 [get_pins -hierarchical u_skew_uart*sel[3]]
 set_case_analysis 0 [get_pins -hierarchical u_skew_uart*sel[2]]
@@ -68,13 +68,18 @@
 set_case_analysis 0 [get_pins -hierarchical u_skew_glbl*sel[3]]
 set_case_analysis 1 [get_pins -hierarchical u_skew_glbl*sel[2]]
 set_case_analysis 1 [get_pins -hierarchical u_skew_glbl*sel[1]]
-set_case_analysis 1 [get_pins -hierarchical u_skew_glbl*sel[0]]
+set_case_analysis 0 [get_pins -hierarchical u_skew_glbl*sel[0]]
 
 set_case_analysis 1 [get_pins -hierarchical u_skew_wh*sel[3]]
 set_case_analysis 0 [get_pins -hierarchical u_skew_wh*sel[2]]
 set_case_analysis 0 [get_pins -hierarchical u_skew_wh*sel[1]]
 set_case_analysis 0 [get_pins -hierarchical u_skew_wh*sel[0]]
 
+set_case_analysis 1 [get_pins -hierarchical u_skew_sdram*sel[3]]
+set_case_analysis 0 [get_pins -hierarchical u_skew_sdram*sel[2]]
+set_case_analysis 0 [get_pins -hierarchical u_skew_sdram*sel[1]]
+set_case_analysis 0 [get_pins -hierarchical u_skew_sdram*sel[0]]
+
 # Set the interface logic to 0
 set_case_analysis 0 [get_pins -hierarchical u_skew_sd_co*sel[3]]
 set_case_analysis 0 [get_pins -hierarchical u_skew_sd_co*sel[2]]
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 66a7991..b63ffed 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -60,7 +60,6 @@
         $script_dir/../../verilog/gl/uart.v     \
 	$script_dir/../../verilog/gl/sdram.v \
 	$script_dir/../../verilog/gl/wb_host.v \
-	$script_dir/../../verilog/gl/clk_buf.v \
 	$script_dir/../../verilog/gl/clk_skew_adjust.v \
 	$script_dir/../../verilog/gl/syntacore.v \
 	"
@@ -72,7 +71,6 @@
 	$lef_root/sdram.lef \
 	$lef_root/uart.lef \
 	$lef_root/wb_host.lef \
-	$lef_root/clk_buf.lef \
 	$lef_root/clk_skew_adjust.lef \
 	$lef_root/syntacore.lef \
 	"
@@ -84,7 +82,6 @@
 	$gds_root/uart.gds \
 	$gds_root/sdram.gds \
 	$gds_root/wb_host.gds \
-	$gds_root/clk_buf.gds \
 	$gds_root/clk_skew_adjust.gds \
 	$gds_root/syntacore.gds \
 	"
@@ -102,6 +99,10 @@
 set ::env(VDD_PIN) [list {vccd1}]
 set ::env(GND_PIN) [list {vssd1}]
 
+set ::env(VDD_NETS) [list {vccd1}]
+set ::env(GND_NETS) [list {vssd1}]
+
+
 
 # The following is because there are no std cells in the example wrapper project.
 #set ::env(SYNTH_TOP_LEVEL) 1
@@ -123,3 +124,16 @@
 set ::env(PL_DIAMOND_SEARCH_HEIGHT) "250"
 
 
+set ::env(FP_PDN_HOFFSET) "5"
+set ::env(FP_PDN_HPITCH) "80"
+set ::env(FP_PDN_HSPACING) "15"
+set ::env(FP_PDN_HWIDTH) "3"
+set ::env(FP_PDN_LOWER_LAYER) "met4"
+set ::env(FP_PDN_RAILS_LAYER) "met1"
+set ::env(FP_PDN_RAIL_OFFSET) "0"
+set ::env(FP_PDN_RAIL_WIDTH) "0.48"
+set ::env(FP_PDN_UPPER_LAYER) "met5"
+set ::env(FP_PDN_VOFFSET) "5"
+set ::env(FP_PDN_VPITCH) "80"
+set ::env(FP_PDN_VSPACING) "15"
+set ::env(FP_PDN_VWIDTH) "3"
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index ca7a467..7a9c10f 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -6,16 +6,12 @@
 u_intercon              300             2300            N
 u_wb_host               300             300             N
 u_skew_wi               2600            2300            N
-u_skew_riscv            500             700             N
-u_skew_uart             2200            1500            N
-u_skew_spi              200             2700            E
-u_skew_sdram            900             2700            E
-u_skew_glbl             1900            2850            N
+u_skew_riscv            500             600             N
+u_skew_uart             2200            1400            N
+u_skew_spi              150             2700            N
+u_skew_sdram            800             2700            N
+u_skew_glbl             1850            2850            N
 u_skew_wh               800             600             N
 u_skew_sd_co            950             3300            N
 u_skew_sd_ci            1100            3300            N
 u_skew_sp_co            100             1800            N
-u_buf1_wb_rstn          2000            500             N
-u_buf2_wb_rstn          2600            1700            N
-u_buf1_wbclk            2100            700             N
-u_buf2_wbclk            1500            2100            N
diff --git a/openlane/user_project_wrapper/sta.tcl b/openlane/user_project_wrapper/sta.tcl
index ac444aa..3b72ab5 100644
--- a/openlane/user_project_wrapper/sta.tcl
+++ b/openlane/user_project_wrapper/sta.tcl
@@ -78,22 +78,25 @@
 #report_power 
 echo "################ CORNER : WC (SLOW) TIMING Report ###################" > timing_max.rpt
 report_checks -unique -path_delay max -slack_max -0.0 -group_count 100 -corner wc >> timing_max.rpt
-report_checks -group_count 100 -path_delay max  -slack_max -0.01 -path_group $::env(WBM_CLOCK_NAME)       -corner wc  > timing_max.rpt
-report_checks -group_count 100 -path_delay max  -slack_max -0.01 -path_group $::env(WBS_CLOCK_NAME)       -corner wc  > timing_max.rpt
-report_checks -group_count 100 -path_delay max  -slack_max -0.01 -path_group $::env(SDRAM_CLOCK_NAME)     -corner wc  > timing_max.rpt
-report_checks -group_count 100 -path_delay max  -slack_max -0.01 -path_group $::env(PAD_SDRAM_CLOCK_NAME) -corner wc  > timing_max.rpt
-report_checks -group_count 100 -path_delay max  -slack_max -0.01 -path_group $::env(CPU_CLOCK_NAME)       -corner wc  > timing_max.rpt
-report_checks -group_count 100 -path_delay max  -slack_max -0.01 -path_group $::env(RTC_CLOCK_NAME)       -corner wc  > timing_max.rpt
+report_checks -group_count 100 -path_delay max  -path_group $::env(WBM_CLOCK_NAME)       -corner wc  >> timing_max.rpt
+report_checks -group_count 100 -path_delay max  -path_group $::env(WBS_CLOCK_NAME)       -corner wc  >> timing_max.rpt
+report_checks -group_count 100 -path_delay max  -path_group $::env(SDRAM_CLOCK_NAME)     -corner wc  >> timing_max.rpt
+report_checks -group_count 100 -path_delay max  -path_group $::env(PAD_SDRAM_CLOCK_NAME) -corner wc  >> timing_max.rpt
+report_checks -group_count 100 -path_delay max  -path_group $::env(CPU_CLOCK_NAME)       -corner wc  >> timing_max.rpt
+report_checks -group_count 100 -path_delay max  -path_group $::env(RTC_CLOCK_NAME)       -corner wc  >> timing_max.rpt
+
+report_checks -path_delay max   -corner wc >> timing_max.rpt
 
 echo "################ CORNER : BC (SLOW) TIMING Report ###################" > timing_min.rpt
 report_checks -unique -path_delay min -slack_min -0.0 -group_count 100 -corner bc >> timing_min.rpt
-report_checks -group_count 100  -path_delay min -slack_min -0.01 -path_group $::env(WBM_CLOCK_NAME)        -corner bc  > timing_min.rpt
-report_checks -group_count 100  -path_delay min -slack_min -0.01 -path_group $::env(WBS_CLOCK_NAME)        -corner bc  > timing_min.rpt
-report_checks -group_count 100  -path_delay min -slack_min -0.01 -path_group $::env(SDRAM_CLOCK_NAME)      -corner bc  > timing_min.rpt
-report_checks -group_count 100  -path_delay min -slack_min -0.01 -path_group $::env(PAD_SDRAM_CLOCK_NAME)  -corner bc  > timing_min.rpt
-report_checks -group_count 100  -path_delay min -slack_min -0.01 -path_group $::env(CPU_CLOCK_NAME)        -corner bc  > timing_min.rpt
-report_checks -group_count 100  -path_delay min -slack_min -0.01 -path_group $::env(RTC_CLOCK_NAME)        -corner bc  > timing_min.rpt
+report_checks -group_count 100  -path_delay min -path_group $::env(WBM_CLOCK_NAME)        -corner bc  >> timing_min.rpt
+report_checks -group_count 100  -path_delay min -path_group $::env(WBS_CLOCK_NAME)        -corner bc  >> timing_min.rpt
+report_checks -group_count 100  -path_delay min -path_group $::env(SDRAM_CLOCK_NAME)      -corner bc  >> timing_min.rpt
+report_checks -group_count 100  -path_delay min -path_group $::env(PAD_SDRAM_CLOCK_NAME)  -corner bc  >> timing_min.rpt
+report_checks -group_count 100  -path_delay min -path_group $::env(CPU_CLOCK_NAME)        -corner bc  >> timing_min.rpt
+report_checks -group_count 100  -path_delay min -path_group $::env(RTC_CLOCK_NAME)        -corner bc  >> timing_min.rpt
 
+report_checks -path_delay min  -corner bc >> timing_min.rpt
 report_checks -path_delay min_max 
 
-exit
+#exit
diff --git a/openlane/wb_host/config.tcl b/openlane/wb_host/config.tcl
index 0c6de99..60375d1 100755
--- a/openlane/wb_host/config.tcl
+++ b/openlane/wb_host/config.tcl
@@ -78,3 +78,7 @@
 
 set ::env(DIODE_INSERTION_STRATEGY) 5
 
+set ::env(FP_PDN_VPITCH) 100
+set ::env(FP_PDN_HPITCH) 100
+set ::env(FP_PDN_VWIDTH) 3
+set ::env(FP_PDN_HWIDTH) 3
diff --git a/openlane/wb_interconnect/base.sdc b/openlane/wb_interconnect/base.sdc
index 9be4a55..e7a67d1 100644
--- a/openlane/wb_interconnect/base.sdc
+++ b/openlane/wb_interconnect/base.sdc
@@ -23,7 +23,7 @@
 create_clock [get_ports $::env(CLOCK_PORT)]  -name $::env(CLOCK_PORT)  -period $::env(CLOCK_PERIOD)
 
 set input_delay_value [expr $::env(CLOCK_PERIOD) * 0.6]
-set output_delay_value [expr $::env(CLOCK_PERIOD) * 0.6]
+set output_delay_value [expr $::env(CLOCK_PERIOD) * 0.4]
 puts "\[INFO\]: Setting output delay to: $output_delay_value"
 puts "\[INFO\]: Setting input delay to: $input_delay_value"
 
diff --git a/openlane/wb_interconnect/config.tcl b/openlane/wb_interconnect/config.tcl
index 6d95cff..4e6a946 100755
--- a/openlane/wb_interconnect/config.tcl
+++ b/openlane/wb_interconnect/config.tcl
@@ -72,6 +72,11 @@
 set ::env(FP_IO_VEXTEND) 4
 set ::env(FP_IO_HEXTEND) 4
 
+set ::env(FP_PDN_VPITCH) 100
+set ::env(FP_PDN_HPITCH) 100
+set ::env(FP_PDN_VWIDTH) 3
+set ::env(FP_PDN_HWIDTH) 3
+
 
 set ::env(GLB_RT_MAXLAYER) 4
 set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
diff --git a/openlane/wb_interconnect/sta.tcl b/openlane/wb_interconnect/sta.tcl
new file mode 100644
index 0000000..cb809a5
--- /dev/null
+++ b/openlane/wb_interconnect/sta.tcl
@@ -0,0 +1,57 @@
+# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+
+set ::env(LIB_FASTEST) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib"
+set ::env(LIB_SLOWEST) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib"
+set ::env(CURRENT_NETLIST) runs/wb_interconnect/results/synthesis/wb_interconnect.synthesis_preroute.v
+set ::env(DESIGN_NAME) "wb_interconnect"
+set ::env(CURRENT_SPEF) ../../spef/wb_interconnect.spef
+set ::env(BASE_SDC_FILE) "base.sdc"
+set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_8"
+set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
+set ::env(SYNTH_CAP_LOAD) "17.65"
+set ::env(WIRE_RC_LAYER) "met1"
+
+
+set_cmd_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm -distance um
+read_liberty -min $::env(LIB_FASTEST)
+read_liberty -max $::env(LIB_SLOWEST)
+read_verilog $::env(CURRENT_NETLIST)
+link_design  $::env(DESIGN_NAME)
+
+read_spef  $::env(CURRENT_SPEF)
+
+read_sdc -echo $::env(BASE_SDC_FILE)
+
+# check for missing constraints
+check_setup  -verbose > unconstraints.rpt
+
+set_operating_conditions -analysis_type single
+# Propgate the clock
+set_propagated_clock [all_clocks]
+
+report_tns
+report_wns
+report_power 
+report_checks -unique -slack_max -0.0 -group_count 100 
+report_checks -unique -slack_min -0.0 -group_count 100 
+report_checks -path_delay min_max 
+report_checks -group_count 100  -slack_max -0.01  > timing.rpt
+
+report_checks -group_count 100  -slack_min -0.01 >> timing.rpt
+
+
diff --git a/signoff/clk_buf/final_summary_report.csv b/signoff/clk_buf/final_summary_report.csv
index c4c7b1f..f6ee716 100644
--- a/signoff/clk_buf/final_summary_report.csv
+++ b/signoff/clk_buf/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/clk_buf,clk_buf,clk_buf,Flow_completed,0h1m1s,0h0m25s,1851.851851851852,0.0009,1111.111111111111,8,379.25,1,0,0,0,0,0,0,0,0,0,0,0,41,4,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,45365,0.0,0.93,0.53,0.0,-1,-1,2,2,2,2,0,0,0,1,0,0,0,0,0,0,0,0,-1,-1,-1,14,4,0,18,90.9090909090909,11,10,AREA 0,5,60,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,3
+0,/project/openlane/clk_buf,clk_buf,clk_buf,Flow_completed,0h1m2s,0h0m26s,925.925925925926,0.0018,555.5555555555555,3,382.24,1,0,0,0,0,0,0,0,0,0,0,0,45,4,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,49267,0.0,0.58,0.26,0.0,-1,-1,2,2,2,2,0,0,0,1,0,0,0,0,0,0,0,0,-1,-1,-1,14,13,0,27,90.9090909090909,11,10,AREA 0,5,60,1,30,30,0.55,0,sky130_fd_sc_hd,4,3
diff --git a/signoff/clk_skew_adjust/final_summary_report.csv b/signoff/clk_skew_adjust/final_summary_report.csv
index 713cb84..4bf213c 100644
--- a/signoff/clk_skew_adjust/final_summary_report.csv
+++ b/signoff/clk_skew_adjust/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/clk_skew_adjust,clk_skew_adjust,clk_skew_adjust,Flow_completed,0h1m8s,0h0m32s,46875.0,0.0016,18750.0,48,385.05,30,0,0,0,0,0,0,0,0,0,0,0,980,208,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,0.0,16.57,18.31,0.0,-1,-1,32,35,32,35,0,0,0,30,0,0,0,0,0,0,0,0,-1,-1,-1,20,6,0,26,90.9090909090909,11,10,AREA 0,5,40,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,3
+0,/project/openlane/clk_skew_adjust,clk_skew_adjust,clk_skew_adjust,Flow_completed,0h1m11s,0h0m33s,7500.0,0.01,3000.0,5,405.05,30,0,0,0,0,0,0,0,0,0,0,0,2811,205,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,0.0,5.86,7.62,0.0,-1,-1,32,35,32,35,0,0,0,30,0,0,0,0,0,0,0,0,-1,-1,-1,64,102,0,166,90.9090909090909,11,10,AREA 0,5,40,1,30,30,0.55,0,sky130_fd_sc_hd,4,3
diff --git a/signoff/glbl_cfg/final_summary_report.csv b/signoff/glbl_cfg/final_summary_report.csv
index 1ec2d16..751ec7f 100644
--- a/signoff/glbl_cfg/final_summary_report.csv
+++ b/signoff/glbl_cfg/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/glbl_cfg,glbl_cfg,glbl_cfg,Flow_completed,0h5m16s,0h3m23s,45883.33333333334,0.12,22941.66666666667,40,559.94,2753,0,0,0,0,0,0,0,1,0,-1,0,141067,23714,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,98939272,0.0,28.84,28.31,0.23,-1,-1,2637,2802,459,624,0,0,0,2753,1,0,3,0,471,0,0,562,577,533,10,278,1410,0,1688,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,4
+0,/project/openlane/glbl_cfg,glbl_cfg,glbl_cfg,Flow_completed,0h6m21s,0h4m2s,45883.33333333334,0.12,22941.66666666667,40,558.82,2753,0,0,0,0,0,0,0,3,0,-1,0,141434,23871,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,98939272,0.0,28.84,28.31,0.23,-1,-1,2637,2802,459,624,0,0,0,2753,1,0,3,0,471,0,0,562,577,533,10,278,1410,0,1688,100.0,10.0,10,AREA 0,4,50,1,100,100,0.55,0,sky130_fd_sc_hd,4,4
diff --git a/signoff/sdram/final_summary_report.csv b/signoff/sdram/final_summary_report.csv
index 9f8bba1..efe606d 100644
--- a/signoff/sdram/final_summary_report.csv
+++ b/signoff/sdram/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/sdram,sdrc_top,sdram,Flow_completed,0h8m49s,0h4m33s,41131.42857142857,0.35,20565.714285714286,27,656.29,7198,0,0,0,0,0,0,0,14,0,-1,0,307108,51429,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,245789185,0.0,20.86,16.44,1.36,-1,-1,7102,7361,1246,1505,0,0,0,7198,197,107,83,94,354,211,32,2289,1267,1186,27,350,4248,0,4598,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,3
+0,/project/openlane/sdram,sdrc_top,sdram,Flow_completed,0h9m52s,0h5m32s,41131.42857142857,0.35,20565.714285714286,27,652.35,7198,0,0,0,0,0,0,0,11,0,-1,0,307721,51643,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,245789185,0.0,20.86,16.44,1.36,-1,-1,7102,7361,1246,1505,0,0,0,7198,197,107,83,94,354,211,32,2289,1267,1186,27,350,4248,0,4598,100.0,10.0,10,AREA 0,4,50,1,100,100,0.55,0,sky130_fd_sc_hd,4,3
diff --git a/signoff/spi_master/final_summary_report.csv b/signoff/spi_master/final_summary_report.csv
index 9d40c99..909798e 100644
--- a/signoff/spi_master/final_summary_report.csv
+++ b/signoff/spi_master/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/spi_master,spim_top,spi_master,Flow_completed,0h7m22s,0h4m17s,45758.33333333334,0.24,22879.16666666667,33,609.27,5491,0,0,0,0,0,0,0,4,4,-1,0,244856,41928,-0.01,-0.01,0.0,0.0,0.0,-0.01,-0.01,0.0,0.0,0.0,192084576,0.0,17.57,28.06,0.0,-1,-1,5427,5567,901,1041,0,0,0,5491,223,0,184,93,748,126,37,1613,982,921,24,424,2889,0,3313,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,3
+0,/project/openlane/spi_master,spim_top,spi_master,Flow_completed,0h10m10s,0h6m52s,45758.33333333334,0.24,22879.16666666667,33,621.43,5491,0,0,0,0,0,0,0,2,4,-1,0,246103,42258,-0.01,-0.01,0.0,0.0,0.0,-0.01,-0.01,0.0,0.0,0.0,192084576,0.0,17.57,28.06,0.0,-1,-1,5427,5567,901,1041,0,0,0,5491,223,0,184,93,748,126,37,1613,982,921,24,424,2889,0,3313,100.0,10.0,10,AREA 0,4,50,1,100,100,0.55,0,sky130_fd_sc_hd,4,3
diff --git a/signoff/syntacore/final_summary_report.csv b/signoff/syntacore/final_summary_report.csv
index 0fd7224..a7d32d3 100644
--- a/signoff/syntacore/final_summary_report.csv
+++ b/signoff/syntacore/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/syntacore,scr1_top_wb,syntacore,Flow_completed,0h53m13s,0h28m58s,34498.88888888888,1.8,17249.44444444444,23,1213.48,31049,0,0,0,0,0,0,0,57,10,-1,0,1624212,251814,-4.82,-4.82,-4.79,-4.79,-4.92,-38.56,-38.56,-38.91,-38.91,-39.55,1349556396,0.0,18.58,16.71,4.86,0.69,-1,30872,31173,2777,3078,0,0,0,31049,637,0,695,2031,3988,2108,1314,7432,2838,2808,95,866,22836,5,23707,67.02412868632707,14.92,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,3
+0,/project/openlane/syntacore,scr1_top_wb,syntacore,Flow_completed,1h2m32s,0h38m33s,34498.88888888888,1.8,17249.44444444444,23,1214.57,31049,0,0,0,0,0,0,0,95,10,-1,0,1627641,253589,-4.82,-4.82,-4.79,-4.79,-4.89,-38.56,-38.56,-38.91,-38.91,-39.32,1349556396,0.0,18.61,16.76,4.8,0.61,-1,30872,31173,2777,3078,0,0,0,31049,637,0,695,2031,3988,2108,1314,7432,2838,2808,95,866,22836,0,23702,67.15916722632639,14.89,10,AREA 0,4,50,1,100,100,0.55,0,sky130_fd_sc_hd,4,3
diff --git a/signoff/uart/final_summary_report.csv b/signoff/uart/final_summary_report.csv
index ee96d6e..c2b4760 100644
--- a/signoff/uart/final_summary_report.csv
+++ b/signoff/uart/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/uart,uart_core,uart,Flow_completed,0h4m44s,0h2m53s,46166.66666666667,0.12,23083.333333333336,35,547.19,2770,0,0,0,0,0,0,0,0,0,-1,0,93003,20847,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,62462955,0.0,19.71,19.11,0.0,-1,-1,2769,2789,456,476,0,0,0,2770,56,0,29,41,182,125,26,685,435,396,18,278,1410,0,1688,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,4
+0,/project/openlane/uart,uart_core,uart,Flow_completed,0h5m3s,0h2m57s,46166.66666666667,0.12,23083.333333333336,35,548.05,2770,0,0,0,0,0,0,0,0,0,-1,0,93312,20907,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,62462955,0.0,19.71,19.11,0.0,-1,-1,2769,2789,456,476,0,0,0,2770,56,0,29,41,182,125,26,685,435,396,18,278,1410,0,1688,100.0,10.0,10,AREA 0,4,50,1,100,100,0.55,0,sky130_fd_sc_hd,4,4
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index 9d16e43..82ad7d4 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,Flow_completed,0h41m55s,0h4m57s,4.086239103362392,10.2784,2.043119551681196,0,570.2,21,0,0,0,0,0,0,0,0,38,-1,-1,1176072,4123,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,-1,0.0,1.35,4.28,0.87,1.77,-1,852,1470,852,1470,0,0,0,21,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,180,180,0.55,0,sky130_fd_sc_hd,4,0
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,Flow_completed,0h42m37s,0h5m15s,3.3079078455790785,10.2784,1.6539539227895392,0,604.07,17,0,0,0,0,0,0,0,0,4,-1,-1,1189768,4428,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,-1,0.0,1.39,4.32,0.78,1.79,-1,848,1466,848,1466,0,0,0,17,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,80,0.55,0,sky130_fd_sc_hd,4,0
diff --git a/signoff/wb_host/final_summary_report.csv b/signoff/wb_host/final_summary_report.csv
index 7d06a32..02deb7d 100644
--- a/signoff/wb_host/final_summary_report.csv
+++ b/signoff/wb_host/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/wb_host,wb_host,wb_host,Flow_completed,0h5m14s,0h3m25s,61400.0,0.1,30700.0,49,582.5,3070,0,0,0,0,0,0,0,0,0,-1,0,172500,26194,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,140873672,0.0,49.1,23.43,16.91,-1,-1,2926,3180,551,805,0,0,0,3070,78,0,3,11,50,27,10,799,605,775,14,130,1139,0,1269,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,5
+0,/project/openlane/wb_host,wb_host,wb_host,Flow_completed,0h6m19s,0h4m12s,61400.0,0.1,30700.0,49,584.38,3070,0,0,0,0,0,0,0,1,0,-1,0,172826,26248,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,140873672,0.0,49.1,23.43,16.91,-1,-1,2926,3180,551,805,0,0,0,3070,78,0,3,11,50,27,10,799,605,775,14,130,1139,0,1269,100.0,10.0,10,AREA 0,4,50,1,100,100,0.55,0,sky130_fd_sc_hd,4,5
diff --git a/signoff/wb_interconnect/final_summary_report.csv b/signoff/wb_interconnect/final_summary_report.csv
index afa6597..078e36d 100644
--- a/signoff/wb_interconnect/final_summary_report.csv
+++ b/signoff/wb_interconnect/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,Flow_completed,0h10m20s,0h6m12s,5868.181818181818,0.44,2934.090909090909,5,576.81,1291,0,0,0,0,0,0,0,2,0,-1,0,483765,20458,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,415470896,0.0,32.05,8.47,19.72,-1,-1,1041,1614,204,777,0,0,0,1291,244,0,75,15,111,0,0,180,431,414,11,130,5189,0,5319,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.55,0,sky130_fd_sc_hd,4,4
+0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,Flow_completed,0h8m12s,0h4m43s,7824.242424242424,0.33,3912.121212121212,7,548.17,1291,0,0,0,0,0,0,0,1,0,-1,0,392265,17144,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,341299996,0.0,36.24,7.66,20.54,-1,-1,1041,1614,204,777,0,0,0,1291,244,0,75,15,111,0,0,180,431,414,11,94,3794,0,3888,100.0,10.0,10,AREA 0,4,50,1,180,180,0.55,0,sky130_fd_sc_hd,4,4
diff --git a/verilog/dv/risc_boot/risc_boot_tb.v b/verilog/dv/risc_boot/risc_boot_tb.v
index 666880f..2cb80c3 100644
--- a/verilog/dv/risc_boot/risc_boot_tb.v
+++ b/verilog/dv/risc_boot/risc_boot_tb.v
@@ -476,25 +476,6 @@
 	force uut.mprj.u_wb_host.u_clkbuf_rtc.VGND =VSS;
 	force uut.mprj.u_wb_host.u_clkbuf_rtc.VNB = VSS;
 
-	force uut.mprj.u_buf1_wb_rstn.u_buf.VPWR =USER_VDD1V8;
-	force uut.mprj.u_buf1_wb_rstn.u_buf.VPB  =USER_VDD1V8;
-	force uut.mprj.u_buf1_wb_rstn.u_buf.VGND =VSS;
-	force uut.mprj.u_buf1_wb_rstn.u_buf.VNB = VSS;
-
-	force uut.mprj.u_buf2_wb_rstn.u_buf.VPWR =USER_VDD1V8;
-	force uut.mprj.u_buf2_wb_rstn.u_buf.VPB  =USER_VDD1V8;
-	force uut.mprj.u_buf2_wb_rstn.u_buf.VGND =VSS;
-	force uut.mprj.u_buf2_wb_rstn.u_buf.VNB = VSS;
-
-	force uut.mprj.u_buf1_wbclk.u_buf.VPWR =USER_VDD1V8;
-	force uut.mprj.u_buf1_wbclk.u_buf.VPB  =USER_VDD1V8;
-	force uut.mprj.u_buf1_wbclk.u_buf.VGND =VSS;
-	force uut.mprj.u_buf1_wbclk.u_buf.VNB = VSS;
-
-	force uut.mprj.u_buf2_wbclk.u_buf.VPWR =USER_VDD1V8;
-	force uut.mprj.u_buf2_wbclk.u_buf.VPB  =USER_VDD1V8;
-	force uut.mprj.u_buf2_wbclk.u_buf.VGND =VSS;
-	force uut.mprj.u_buf2_wbclk.u_buf.VNB = VSS;
     end
 `endif    
 
diff --git a/verilog/dv/user_risc_boot/user_risc_boot_tb.v b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
index 8da63e3..aa4c71a 100644
--- a/verilog/dv/user_risc_boot/user_risc_boot_tb.v
+++ b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
@@ -346,25 +346,6 @@
 	force u_top.u_wb_host.u_clkbuf_rtc.VPB  =USER_VDD1V8;
 	force u_top.u_wb_host.u_clkbuf_rtc.VGND =VSS;
 	force u_top.u_wb_host.u_clkbuf_rtc.VNB = VSS;
-	force u_top.u_buf1_wb_rstn.u_buf.VPWR =USER_VDD1V8;
-	force u_top.u_buf1_wb_rstn.u_buf.VPB  =USER_VDD1V8;
-	force u_top.u_buf1_wb_rstn.u_buf.VGND =VSS;
-	force u_top.u_buf1_wb_rstn.u_buf.VNB = VSS;
-
-	force u_top.u_buf2_wb_rstn.u_buf.VPWR =USER_VDD1V8;
-	force u_top.u_buf2_wb_rstn.u_buf.VPB  =USER_VDD1V8;
-	force u_top.u_buf2_wb_rstn.u_buf.VGND =VSS;
-	force u_top.u_buf2_wb_rstn.u_buf.VNB = VSS;
-
-	force u_top.u_buf1_wbclk.u_buf.VPWR =USER_VDD1V8;
-	force u_top.u_buf1_wbclk.u_buf.VPB  =USER_VDD1V8;
-	force u_top.u_buf1_wbclk.u_buf.VGND =VSS;
-	force u_top.u_buf1_wbclk.u_buf.VNB = VSS;
-
-	force u_top.u_buf2_wbclk.u_buf.VPWR =USER_VDD1V8;
-	force u_top.u_buf2_wbclk.u_buf.VPB  =USER_VDD1V8;
-	force u_top.u_buf2_wbclk.u_buf.VGND =VSS;
-	force u_top.u_buf2_wbclk.u_buf.VNB = VSS;
     end
 `endif    
 
diff --git a/verilog/dv/user_spi/user_spi_tb.v b/verilog/dv/user_spi/user_spi_tb.v
index 9b1e753..60ad1f9 100644
--- a/verilog/dv/user_spi/user_spi_tb.v
+++ b/verilog/dv/user_spi/user_spi_tb.v
@@ -480,25 +480,6 @@
 	force u_top.u_wb_host.u_clkbuf_rtc.VPB  =USER_VDD1V8;
 	force u_top.u_wb_host.u_clkbuf_rtc.VGND =VSS;
 	force u_top.u_wb_host.u_clkbuf_rtc.VNB = VSS;
-	force u_top.u_buf1_wb_rstn.u_buf.VPWR =USER_VDD1V8;
-	force u_top.u_buf1_wb_rstn.u_buf.VPB  =USER_VDD1V8;
-	force u_top.u_buf1_wb_rstn.u_buf.VGND =VSS;
-	force u_top.u_buf1_wb_rstn.u_buf.VNB = VSS;
-
-	force u_top.u_buf2_wb_rstn.u_buf.VPWR =USER_VDD1V8;
-	force u_top.u_buf2_wb_rstn.u_buf.VPB  =USER_VDD1V8;
-	force u_top.u_buf2_wb_rstn.u_buf.VGND =VSS;
-	force u_top.u_buf2_wb_rstn.u_buf.VNB = VSS;
-
-	force u_top.u_buf1_wbclk.u_buf.VPWR =USER_VDD1V8;
-	force u_top.u_buf1_wbclk.u_buf.VPB  =USER_VDD1V8;
-	force u_top.u_buf1_wbclk.u_buf.VGND =VSS;
-	force u_top.u_buf1_wbclk.u_buf.VNB = VSS;
-
-	force u_top.u_buf2_wbclk.u_buf.VPWR =USER_VDD1V8;
-	force u_top.u_buf2_wbclk.u_buf.VPB  =USER_VDD1V8;
-	force u_top.u_buf2_wbclk.u_buf.VGND =VSS;
-	force u_top.u_buf2_wbclk.u_buf.VNB = VSS;
     end
 `endif    
 
diff --git a/verilog/dv/user_uart/user_uart_tb.v b/verilog/dv/user_uart/user_uart_tb.v
index 986be10..10dca8b 100644
--- a/verilog/dv/user_uart/user_uart_tb.v
+++ b/verilog/dv/user_uart/user_uart_tb.v
@@ -386,25 +386,6 @@
 	force u_top.u_wb_host.u_clkbuf_rtc.VGND =VSS;
 	force u_top.u_wb_host.u_clkbuf_rtc.VNB = VSS;
 
-	force u_top.u_buf1_wb_rstn.u_buf.VPWR =USER_VDD1V8;
-	force u_top.u_buf1_wb_rstn.u_buf.VPB  =USER_VDD1V8;
-	force u_top.u_buf1_wb_rstn.u_buf.VGND =VSS;
-	force u_top.u_buf1_wb_rstn.u_buf.VNB = VSS;
-
-	force u_top.u_buf2_wb_rstn.u_buf.VPWR =USER_VDD1V8;
-	force u_top.u_buf2_wb_rstn.u_buf.VPB  =USER_VDD1V8;
-	force u_top.u_buf2_wb_rstn.u_buf.VGND =VSS;
-	force u_top.u_buf2_wb_rstn.u_buf.VNB = VSS;
-
-	force u_top.u_buf1_wbclk.u_buf.VPWR =USER_VDD1V8;
-	force u_top.u_buf1_wbclk.u_buf.VPB  =USER_VDD1V8;
-	force u_top.u_buf1_wbclk.u_buf.VGND =VSS;
-	force u_top.u_buf1_wbclk.u_buf.VNB = VSS;
-
-	force u_top.u_buf2_wbclk.u_buf.VPWR =USER_VDD1V8;
-	force u_top.u_buf2_wbclk.u_buf.VPB  =USER_VDD1V8;
-	force u_top.u_buf2_wbclk.u_buf.VGND =VSS;
-	force u_top.u_buf2_wbclk.u_buf.VNB = VSS;
     end
 `endif    
 //------------------------------------------------------
diff --git a/verilog/dv/wb_port/wb_port_tb.v b/verilog/dv/wb_port/wb_port_tb.v
index b045e13..7b12e0e 100644
--- a/verilog/dv/wb_port/wb_port_tb.v
+++ b/verilog/dv/wb_port/wb_port_tb.v
@@ -261,25 +261,6 @@
 	force uut.mprj.u_wb_host.u_clkbuf_rtc.VGND =VSS;
 	force uut.mprj.u_wb_host.u_clkbuf_rtc.VNB = VSS;
 
-	force uut.mprj.u_buf1_wb_rstn.u_buf.VPWR =USER_VDD1V8;
-	force uut.mprj.u_buf1_wb_rstn.u_buf.VPB  =USER_VDD1V8;
-	force uut.mprj.u_buf1_wb_rstn.u_buf.VGND =VSS;
-	force uut.mprj.u_buf1_wb_rstn.u_buf.VNB = VSS;
-
-	force uut.mprj.u_buf2_wb_rstn.u_buf.VPWR =USER_VDD1V8;
-	force uut.mprj.u_buf2_wb_rstn.u_buf.VPB  =USER_VDD1V8;
-	force uut.mprj.u_buf2_wb_rstn.u_buf.VGND =VSS;
-	force uut.mprj.u_buf2_wb_rstn.u_buf.VNB = VSS;
-
-	force uut.mprj.u_buf1_wbclk.u_buf.VPWR =USER_VDD1V8;
-	force uut.mprj.u_buf1_wbclk.u_buf.VPB  =USER_VDD1V8;
-	force uut.mprj.u_buf1_wbclk.u_buf.VGND =VSS;
-	force uut.mprj.u_buf1_wbclk.u_buf.VNB = VSS;
-
-	force uut.mprj.u_buf2_wbclk.u_buf.VPWR =USER_VDD1V8;
-	force uut.mprj.u_buf2_wbclk.u_buf.VPB  =USER_VDD1V8;
-	force uut.mprj.u_buf2_wbclk.u_buf.VGND =VSS;
-	force uut.mprj.u_buf2_wbclk.u_buf.VNB = VSS;
     end
 `endif    
 endmodule
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 35e10c8..99d5b86 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -271,11 +271,11 @@
 wire                              cpu_clk       ;
 wire                              rtc_clk       ;
 wire                              wbd_clk_int   ;
-wire                              wbd_clk_int1  ;
-wire                              wbd_clk_int2  ;
+//wire                              wbd_clk_int1  ;
+//wire                              wbd_clk_int2  ;
 wire                              wbd_int_rst_n ;
-wire                              wbd_int1_rst_n ;
-wire                              wbd_int2_rst_n ;
+//wire                              wbd_int1_rst_n ;
+//wire                              wbd_int2_rst_n ;
 
 wire [31:0]                       fuse_mhartid  ;
 wire [15:0]                       irq_lines     ;
@@ -352,11 +352,11 @@
 //assign la_data_out    = {riscv_debug,spi_debug,sdram_debug};
 assign la_data_out[127:0]    = {sdram_debug,spi_debug,riscv_debug};
 
-clk_buf u_buf1_wb_rstn  (.clk_i(wbd_int_rst_n),.clk_o(wbd_int1_rst_n));
-clk_buf u_buf2_wb_rstn  (.clk_i(wbd_int1_rst_n),.clk_o(wbd_int2_rst_n));
-
-clk_buf u_buf1_wbclk    (.clk_i(wbd_clk_int),.clk_o(wbd_clk_int1));
-clk_buf u_buf2_wbclk    (.clk_i(wbd_clk_int1),.clk_o(wbd_clk_int2));
+//clk_buf u_buf1_wb_rstn  (.clk_i(wbd_int_rst_n),.clk_o(wbd_int1_rst_n));
+//clk_buf u_buf2_wb_rstn  (.clk_i(wbd_int1_rst_n),.clk_o(wbd_int2_rst_n));
+//
+//clk_buf u_buf1_wbclk    (.clk_i(wbd_clk_int),.clk_o(wbd_clk_int1));
+//clk_buf u_buf2_wbclk    (.clk_i(wbd_clk_int1),.clk_o(wbd_clk_int2));
 
 wb_host u_wb_host(
        .user_clock1      (wb_clk_i             ),
@@ -504,7 +504,7 @@
     .sdram_debug            (sdram_debug                ),
                     
     // WB bus
-    .wb_rst_n               (wbd_int2_rst_n             ),
+    .wb_rst_n               (wbd_int_rst_n              ),
     .wb_clk_i               (wbd_clk_sdram              ),
     
     .wb_stb_i               (wbd_sdram_stb_o            ),
@@ -544,7 +544,7 @@
 
 wb_interconnect  u_intercon (
          .clk_i         (wbd_clk_wi            ), 
-         .rst_n         (wbd_int2_rst_n        ),
+         .rst_n         (wbd_int_rst_n         ),
 
          // Master 0 Interface
          .m0_wbd_dat_i  (wbd_int_dat_i         ),
@@ -628,7 +628,7 @@
 glbl_cfg   u_glbl_cfg (
 
        .mclk                   (wbd_clk_glbl              ),
-       .reset_n                (wbd_int2_rst_n            ),
+       .reset_n                (wbd_int_rst_n             ),
 
         // Reg Bus Interface Signal
        .reg_cs                 (wbd_glbl_stb_o            ),
@@ -669,7 +669,7 @@
         );
 
 uart_core   u_uart_core (
-        .arst_n                 (wbd_int1_rst_n           ), // async reset
+        .arst_n                 (wbd_int_rst_n            ), // async reset
         .app_clk                (wbd_clk_uart             ),
 
         // Reg Bus Interface Signal
@@ -701,7 +701,7 @@
                .vccd1      (vccd1                      ),// User area 1 1.8V supply
                .vssd1      (vssd1                      ),// User area 1 digital ground
 `endif
-	       .clk_in     (wbd_clk_int1                ), 
+	       .clk_in     (wbd_clk_int                 ), 
 	       .sel        (cfg_cska_wi                 ), 
 	       .clk_out    (wbd_clk_wi                  ) 
        );
@@ -725,7 +725,7 @@
                .vccd1      (vccd1                      ),// User area 1 1.8V supply
                .vssd1      (vssd1                      ),// User area 1 digital ground
 `endif
-	       .clk_in     (wbd_clk_int1                ), 
+	       .clk_in     (wbd_clk_int                 ), 
 	       .sel        (cfg_cska_uart               ), 
 	       .clk_out    (wbd_clk_uart                ) 
        );
@@ -737,7 +737,7 @@
                .vccd1      (vccd1                      ),// User area 1 1.8V supply
                .vssd1      (vssd1                      ),// User area 1 digital ground
 `endif
-	       .clk_in     (wbd_clk_int2               ), 
+	       .clk_in     (wbd_clk_int                ), 
 	       .sel        (cfg_cska_spi               ), 
 	       .clk_out    (wbd_clk_spi                ) 
        );
@@ -749,7 +749,7 @@
                .vccd1      (vccd1                      ),// User area 1 1.8V supply
                .vssd1      (vssd1                      ),// User area 1 digital ground
 `endif
-	       .clk_in     (wbd_clk_int2               ), 
+	       .clk_in     (wbd_clk_int                ), 
 	       .sel        (cfg_cska_sdram             ), 
 	       .clk_out    (wbd_clk_sdram              ) 
        );
@@ -761,7 +761,7 @@
                .vccd1      (vccd1                      ),// User area 1 1.8V supply
                .vssd1      (vssd1                      ),// User area 1 digital ground
 `endif
-	       .clk_in     (wbd_clk_int2              ), 
+	       .clk_in     (wbd_clk_int               ), 
 	       .sel        (cfg_cska_glbl             ), 
 	       .clk_out    (wbd_clk_glbl              ) 
        );