diff --git a/openlane/yifive/base.sdc b/openlane/yifive/base.sdc
index 777ec2d..626a527 100644
--- a/openlane/yifive/base.sdc
+++ b/openlane/yifive/base.sdc
@@ -1,9 +1,4 @@
 ###############################################################################
-# Created by write_sdc
-# Mon Nov  8 09:31:35 2021
-###############################################################################
-current_design scr1_top_wb
-###############################################################################
 # Timing Constraints
 ###############################################################################
 create_clock -name core_clk -period 20.0000 [get_ports {core_clk}]
diff --git a/verilog/dv/user_basic/user_basic_tb.v b/verilog/dv/user_basic/user_basic_tb.v
index 47fe0bc..fbad972 100644
--- a/verilog/dv/user_basic/user_basic_tb.v
+++ b/verilog/dv/user_basic/user_basic_tb.v
@@ -151,8 +151,8 @@
 
 	`ifdef WFDUMP
 	   initial begin
-	   	$dumpfile("risc_boot.vcd");
-	   	$dumpvars(3, user_basic_tb);
+	   	$dumpfile("simx.vcd");
+	   	$dumpvars(4, user_basic_tb);
 	   end
        `endif
 
diff --git a/verilog/dv/user_spi/user_spi_tb.v b/verilog/dv/user_spi/user_spi_tb.v
index 137fc2a..2396183 100644
--- a/verilog/dv/user_spi/user_spi_tb.v
+++ b/verilog/dv/user_spi/user_spi_tb.v
@@ -201,12 +201,13 @@
 
 	`ifdef WFDUMP
 	   initial begin
-	   	$dumpfile("user_spi.vcd");
+	   	$dumpfile("simx.vcd");
 	   	$dumpvars(5, user_spi_tb);
 	   end
        `endif
 
 	initial begin
+		$dumpon;
 
 		#200; // Wait for reset removal
 	        repeat (10) @(posedge clock);
@@ -259,6 +260,7 @@
 		wb_user_core_read_check(32'h00000314,read_data,32'h004902B7);
 		wb_user_core_read_check(32'h00000318,read_data,32'h03130291);
 		wb_user_core_read_check(32'h0000031C,read_data,32'ha0230630);
+		$dumpoff;
 		$display("#############################################");
 		$display("Testing Direct SPI Memory Read              ");
 		$display(" SPI Mode: Normal/Single Bit                ");
@@ -1165,10 +1167,10 @@
    wire #1 io_oeb_27 = io_oeb[27];
    wire #1 io_oeb_28 = io_oeb[28];
    wire #1 io_oeb_29 = io_oeb[29];
-   tri  flash_io0 = (io_oeb_26== 1'b0) ? io_out[26] : 1'bz;
-   tri  flash_io1 = (io_oeb_27== 1'b0) ? io_out[27] : 1'bz;
-   tri  flash_io2 = (io_oeb_28== 1'b0) ? io_out[28] : 1'bz;
-   tri  flash_io3 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz;
+   tri  #1 flash_io0 = (io_oeb_26== 1'b0) ? io_out[26] : 1'bz;
+   tri  #1 flash_io1 = (io_oeb_27== 1'b0) ? io_out[27] : 1'bz;
+   tri  #1 flash_io2 = (io_oeb_28== 1'b0) ? io_out[28] : 1'bz;
+   tri  #1 flash_io3 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz;
 
    assign io_in[26] = flash_io0;
    assign io_in[27] = flash_io1;
diff --git a/verilog/rtl/lib/wb_stagging.sv b/verilog/rtl/lib/wb_stagging.sv
index 8f54f0f..2661005 100644
--- a/verilog/rtl/lib/wb_stagging.sv
+++ b/verilog/rtl/lib/wb_stagging.sv
@@ -81,21 +81,27 @@
          input   logic	[31:0]	m_wbd_dat_i,
          input   logic  [31:0]	m_wbd_adr_i,
          input   logic  [3:0]	m_wbd_sel_i,
+         input   logic  [9:0]	m_wbd_bl_i,
+         input   logic  	m_wbd_bry_i,
          input   logic  	m_wbd_we_i,
          input   logic  	m_wbd_cyc_i,
          input   logic  	m_wbd_stb_i,
          input   logic  [3:0]	m_wbd_tid_i,
          output  logic	[31:0]	m_wbd_dat_o,
          output  logic		m_wbd_ack_o,
+         output  logic		m_wbd_lack_o,
          output  logic		m_wbd_err_o,
 
          // Slave Interface
          input	logic [31:0]	s_wbd_dat_i,
          input	logic 	        s_wbd_ack_i,
+         input	logic 	        s_wbd_lack_i,
          input	logic 	        s_wbd_err_i,
          output	logic [31:0]	s_wbd_dat_o,
          output	logic [31:0]	s_wbd_adr_o,
          output	logic [3:0]	s_wbd_sel_o,
+         output	logic [9:0]	s_wbd_bl_o,
+         output	logic    	s_wbd_bry_o,
          output	logic 	        s_wbd_we_o,
          output	logic 	        s_wbd_cyc_o,
          output	logic 	        s_wbd_stb_o,
@@ -103,22 +109,26 @@
 
 );
 
-logic        holding_busy   ; // Indicate Stagging for Free or not
 logic [31:0] m_wbd_dat_i_ff ; // Flopped vesion of m_wbd_dat_i
 logic [31:0] m_wbd_adr_i_ff ; // Flopped vesion of m_wbd_adr_i
 logic [3:0]  m_wbd_sel_i_ff ; // Flopped vesion of m_wbd_sel_i
+logic [9:0]  m_wbd_bl_i_ff ;  // Flopped vesion of m_wbd_bl_i
+logic        m_wbd_bry_i_ff ; // Flopped vesion of m_wbd_bry_i
 logic        m_wbd_we_i_ff  ; // Flopped vesion of m_wbd_we_i
 logic        m_wbd_cyc_i_ff ; // Flopped vesion of m_wbd_cyc_i
 logic        m_wbd_stb_i_ff ; // Flopped vesion of m_wbd_stb_i
 logic [3:0]  m_wbd_tid_i_ff ; // Flopped vesion of m_wbd_tid_i
 logic [31:0] s_wbd_dat_i_ff ; // Flopped vesion of s_wbd_dat_i
 logic        s_wbd_ack_i_ff ; // Flopped vesion of s_wbd_ack_i
+logic        s_wbd_lack_i_ff ; // Flopped vesion of s_wbd_ack_i
 logic        s_wbd_err_i_ff ; // Flopped vesion of s_wbd_err_i
 
 
 assign s_wbd_dat_o = m_wbd_dat_i_ff;
 assign s_wbd_adr_o = m_wbd_adr_i_ff;
 assign s_wbd_sel_o = m_wbd_sel_i_ff;
+assign s_wbd_bl_o  = m_wbd_bl_i_ff;
+assign s_wbd_bry_o = m_wbd_bry_i_ff;
 assign s_wbd_we_o  = m_wbd_we_i_ff;
 assign s_wbd_cyc_o = m_wbd_cyc_i_ff;
 assign s_wbd_stb_o = m_wbd_stb_i_ff;
@@ -126,28 +136,32 @@
 
 assign m_wbd_dat_o = s_wbd_dat_i_ff;
 assign m_wbd_ack_o = s_wbd_ack_i_ff;
+assign m_wbd_lack_o = s_wbd_lack_i_ff;
 assign m_wbd_err_o = s_wbd_err_i_ff;
 
 always @(negedge rst_n or posedge clk_i)
 begin
    if(rst_n == 1'b0) begin
-       holding_busy   <= 1'b0;
        m_wbd_dat_i_ff <= 'h0;
        m_wbd_adr_i_ff <= 'h0;
        m_wbd_sel_i_ff <= 'h0;
+       m_wbd_bl_i_ff  <= 'h0;
+       m_wbd_bry_i_ff <= 'b0;
        m_wbd_we_i_ff  <= 'h0;
        m_wbd_cyc_i_ff <= 'h0;
        m_wbd_stb_i_ff <= 'h0;
        m_wbd_tid_i_ff <= 'h0;
        s_wbd_dat_i_ff <= 'h0;
        s_wbd_ack_i_ff <= 'h0;
+       s_wbd_lack_i_ff <= 'h0;
        s_wbd_err_i_ff <= 'h0;
    end else begin
-       s_wbd_dat_i_ff <= s_wbd_dat_i;
-       s_wbd_ack_i_ff <= s_wbd_ack_i;
+       s_wbd_dat_i_ff  <= s_wbd_dat_i;
+       s_wbd_ack_i_ff  <= s_wbd_ack_i;
+       s_wbd_lack_i_ff <= s_wbd_lack_i;
        s_wbd_err_i_ff <= s_wbd_err_i;
-       if(m_wbd_stb_i && holding_busy == 0 && m_wbd_ack_o == 0) begin
-          holding_busy   <= 1'b1;
+       if((m_wbd_stb_i && m_wbd_bry_i && s_wbd_ack_i == 0 && m_wbd_lack_o == 0) ||
+          (m_wbd_stb_i && m_wbd_bry_i && s_wbd_ack_i == 1 && s_wbd_lack_i == 0)) begin
           m_wbd_dat_i_ff <= m_wbd_dat_i;
           m_wbd_adr_i_ff <= m_wbd_adr_i;
           m_wbd_sel_i_ff <= m_wbd_sel_i;
@@ -155,8 +169,11 @@
           m_wbd_cyc_i_ff <= m_wbd_cyc_i;
           m_wbd_stb_i_ff <= m_wbd_stb_i;
           m_wbd_tid_i_ff <= m_wbd_tid_i;
-       end else if (holding_busy && s_wbd_ack_i) begin
-          holding_busy   <= 1'b0;
+          m_wbd_bl_i_ff  <= m_wbd_bl_i;
+          m_wbd_bry_i_ff <= 'b1;
+       end else  if ((m_wbd_stb_i && !m_wbd_bry_i && s_wbd_ack_i == 1 && s_wbd_lack_i == 0)) begin // De-Assert burst ready
+          m_wbd_bry_i_ff <= 'b0;
+       end else if (s_wbd_lack_i) begin
           m_wbd_dat_i_ff <= 'h0;
           m_wbd_adr_i_ff <= 'h0;
           m_wbd_sel_i_ff <= 'h0;
@@ -164,6 +181,8 @@
           m_wbd_cyc_i_ff <= 'h0;
           m_wbd_stb_i_ff <= 'h0;
           m_wbd_tid_i_ff <= 'h0;
+          m_wbd_bl_i_ff  <= 'h0;
+          m_wbd_bry_i_ff <= 'b0;
        end
    end
 end
diff --git a/verilog/rtl/mbist_wrapper/src/mbist_wrapper.sv b/verilog/rtl/mbist_wrapper/src/mbist_wrapper.sv
new file mode 100644
index 0000000..e33134a
--- /dev/null
+++ b/verilog/rtl/mbist_wrapper/src/mbist_wrapper.sv
@@ -0,0 +1,319 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya                          
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  MBIST TOP                                                   ////
+////                                                              ////
+////  This file is part of the mbist_ctrl cores project           ////
+////  https://github.com/dineshannayya/mbist_ctrl.git             ////
+////                                                              ////
+////  Description                                                 ////
+////      This block integrate mbist controller with row          ////
+////      redendency feature                                      ////
+////                                                              ////
+////  To Do:                                                      ////
+////    nothing                                                   ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Dinesh Annayya, dinesha@opencores.org                 ////
+////                                                              ////
+////  Revision :                                                  ////
+////    0.0 - 11th Oct 2021, Dinesh A                             ////
+////          Initial integration                                 ////
+////    0.1 - 26th Oct 2021, Dinesh A                             ////
+////          Fixed Error Address are serial shifted through      ////
+////          sdi/sdo                                             ////
+////    0.2 - 15 Dec 2021, Dinesh A                               ////
+////          Added support for common MBIST for 4 SRAM           ////
+////    0.3 - 29th Dec 2021, Dinesh A                             ////
+////          yosys synthesis issue for two dimension variable    ////
+////          changed the variable defination from logic to wire  ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+`include "mbist_def.svh"
+module mbist_wrapper
+     #(  
+         parameter BIST_NO_SRAM           = 4,
+	 parameter BIST_ADDR_WD           = 9,
+	 parameter BIST_DATA_WD           = 32,
+	 parameter BIST_ADDR_START        = 9'h000,
+	 parameter BIST_ADDR_END          = 9'h1FB,
+	 parameter BIST_REPAIR_ADDR_START = 9'h1FC,
+	 parameter BIST_RAD_WD_I          = BIST_ADDR_WD,
+	 parameter BIST_RAD_WD_O          = BIST_ADDR_WD) (
+
+`ifdef USE_POWER_PINS
+    inout vccd1,	// User area 1 1.8V supply
+    inout vssd1,	// User area 1 digital ground
+`endif
+
+    // Clock Skew Adjust
+       input  wire                           wbd_clk_int, 
+       output wire                           wbd_clk_mbist,
+       input  wire [3:0]                     cfg_cska_mbist, // clock skew adjust for web host
+
+	input logic                            rst_n,
+
+	// MBIST I/F
+	input wire                           bist_en,
+	input wire                            bist_run,
+	input wire                            bist_shift,
+	input wire                            bist_load,
+	input wire                            bist_sdi,
+
+	output wire [3:0]                     bist_error_cnt0,
+	output wire [3:0]                     bist_error_cnt1,
+	output wire [3:0]                     bist_error_cnt2,
+	output wire [3:0]                     bist_error_cnt3,
+	output wire [BIST_NO_SRAM-1:0]        bist_correct   ,
+	output wire [BIST_NO_SRAM-1:0]        bist_error     ,
+	output wire                           bist_done,
+	output wire                           bist_sdo,
+
+
+        // WB I/F
+        input   wire                          wb_clk_i,  // System clock
+        input   wire                          wb_clk2_i, // System clock2 is no cts
+        input   wire                          wb_cyc_i,  // strobe/request
+        input   wire                          wb_stb_i,  // strobe/request
+	input   wire [(BIST_NO_SRAM+1)/2-1:0] wb_cs_i,
+        input   wire [BIST_ADDR_WD-1:0]       wb_adr_i,  // address
+        input   wire                          wb_we_i ,  // write
+        input   wire [BIST_DATA_WD-1:0]       wb_dat_i,  // data output
+        input   wire [BIST_DATA_WD/8-1:0]     wb_sel_i,  // byte enable
+        output  wire [BIST_DATA_WD-1:0]       wb_dat_o,  // data input
+        output  wire                          wb_ack_o,  // acknowlegement
+        output  wire                          wb_err_o  // error
+
+
+
+
+
+);
+
+parameter     BIST_NO_SRAM= 4; // NO of MBIST MEMORY
+parameter  NO_SRAM_WD = (BIST_NO_SRAM+1)/2;
+parameter     BIST1_ADDR_WD = 11; // 512x32 SRAM
+parameter     BIST_DATA_WD = 32;
+
+// FUNCTIONAL PORT 
+// towards memory MBIST1
+// PORT-A
+wire   [BIST_NO_SRAM-1:0]      mem_clk_a;
+wire   [BIST1_ADDR_WD-1:2]     mem0_addr_a;
+wire   [BIST1_ADDR_WD-1:2]     mem1_addr_a;
+wire   [BIST1_ADDR_WD-1:2]     mem2_addr_a;
+wire   [BIST1_ADDR_WD-1:2]     mem3_addr_a;
+wire   [BIST_NO_SRAM-1:0]      mem_cen_a;
+wire   [BIST_NO_SRAM-1:0]      mem_web_a;
+wire [BIST_DATA_WD/8-1:0]      mem0_mask_a;
+wire [BIST_DATA_WD/8-1:0]      mem1_mask_a;
+wire [BIST_DATA_WD/8-1:0]      mem2_mask_a;
+wire [BIST_DATA_WD/8-1:0]      mem3_mask_a;
+wire   [BIST_DATA_WD-1:0]      mem0_din_a;
+wire   [BIST_DATA_WD-1:0]      mem1_din_a;
+wire   [BIST_DATA_WD-1:0]      mem2_din_a;
+wire   [BIST_DATA_WD-1:0]      mem3_din_a;
+wire   [BIST_DATA_WD-1:0]      mem0_dout_a;
+wire   [BIST_DATA_WD-1:0]      mem1_dout_a;
+wire   [BIST_DATA_WD-1:0]      mem2_dout_a;
+wire   [BIST_DATA_WD-1:0]      mem3_dout_a;
+
+// PORT-B
+wire [BIST_NO_SRAM-1:0]        mem_clk_b;
+wire [BIST_NO_SRAM-1:0]        mem_cen_b;
+wire [BIST1_ADDR_WD-1:2]       mem0_addr_b;
+wire [BIST1_ADDR_WD-1:2]       mem1_addr_b;
+wire [BIST1_ADDR_WD-1:2]       mem2_addr_b;
+wire [BIST1_ADDR_WD-1:2]       mem3_addr_b;
+
+
+mbist_top  #(
+	`ifndef SYNTHESIS
+	.BIST_NO_SRAM           (4                      ),
+	.BIST_ADDR_WD           (BIST1_ADDR_WD-2        ),
+	.BIST_DATA_WD           (BIST_DATA_WD           ),
+	.BIST_ADDR_START        (9'h000                 ),
+	.BIST_ADDR_END          (9'h1FB                 ),
+	.BIST_REPAIR_ADDR_START (9'h1FC                 ),
+	.BIST_RAD_WD_I          (BIST1_ADDR_WD-2        ),
+	.BIST_RAD_WD_O          (BIST1_ADDR_WD-2        )
+        `endif
+     ) 
+	     u_mbist (
+
+`ifdef USE_POWER_PINS
+       .vccd1                  (vccd1                     ),// User area 1 1.8V supply
+       .vssd1                  (vssd1                     ),// User area 1 digital ground
+`endif
+
+     // Clock Skew adjust
+	.wbd_clk_int          (wbd_clk_int          ), 
+	.cfg_cska_mbist       (cfg_cska_mbist       ), 
+	.wbd_clk_mbist        (wbd_clk_mbist        ),
+
+	// WB I/F
+        .wb_clk2_i            (wb_clk2_i            ),  
+        .wb_clk_i             (wb_clk_i             ),  
+        .wb_cyc_i             (wb_cyc_i             ),  
+        .wb_stb_i             (wb_stb_i             ),  
+	.wb_cs_i              (wb_cs_i              ),
+        .wb_adr_i             (wb_adr_i             ),  
+        .wb_we_i              (wb_we_i              ),  
+        .wb_dat_i             (wb_dat_i             ),  
+        .wb_sel_i             (wb_sel_i             ),  
+        .wb_dat_o             (wb_dat_o             ),  
+        .wb_ack_o             (wb_ack_o             ),  
+        .wb_err_o             (                     ), 
+
+	.rst_n                (rst_n                ),
+
+	
+	.bist_en              (bist_en              ),
+	.bist_run             (bist_run             ),
+	.bist_shift           (bist_shift           ),
+	.bist_load            (bist_load            ),
+	.bist_sdi             (bist_sdi             ),
+
+	.bist_error_cnt3      (bist_error_cnt3  ),
+	.bist_error_cnt2      (bist_error_cnt2  ),
+	.bist_error_cnt1      (bist_error_cnt1  ),
+	.bist_error_cnt0      (bist_error_cnt0  ),
+	.bist_correct         (bist_correct     ),
+	.bist_error           (bist_error       ),
+	.bist_done            (bist_done        ),
+	.bist_sdo             (bist_sdo         ),
+
+     // towards memory
+     // PORT-A
+        .mem_clk_a            (mem_clk_a         ),
+        .mem_addr_a0          (mem0_addr_a       ),
+        .mem_addr_a1          (mem1_addr_a       ),
+        .mem_addr_a2          (mem2_addr_a       ),
+        .mem_addr_a3          (mem3_addr_a       ),
+        .mem_cen_a            (mem_cen_a         ),
+        .mem_web_a            (mem_web_a         ),
+        .mem_mask_a0          (mem0_mask_a       ),
+        .mem_mask_a1          (mem1_mask_a       ),
+        .mem_mask_a2          (mem2_mask_a       ),
+        .mem_mask_a3          (mem3_mask_a       ),
+        .mem_din_a0           (mem0_din_a        ),
+        .mem_din_a1           (mem1_din_a        ),
+        .mem_din_a2           (mem2_din_a        ),
+        .mem_din_a3           (mem3_din_a        ),
+        .mem_dout_a0          (mem0_dout_a       ),
+        .mem_dout_a1          (mem1_dout_a       ),
+        .mem_dout_a2          (mem2_dout_a       ),
+        .mem_dout_a3          (mem3_dout_a       ),
+     // PORT-B
+        .mem_clk_b            (mem_clk_b         ),
+        .mem_cen_b            (mem_cen_b         ),
+        .mem_addr_b0          (mem0_addr_b       ),
+        .mem_addr_b1          (mem1_addr_b       ),
+        .mem_addr_b2          (mem2_addr_b       ),
+        .mem_addr_b3          (mem3_addr_b       )
+
+
+);
+
+
+
+sky130_sram_2kbyte_1rw1r_32x512_8 u_sram0_2kb(
+`ifdef USE_POWER_PINS
+    .vccd1 (vccd1),// User area 1 1.8V supply
+    .vssd1 (vssd1),// User area 1 digital ground
+`endif
+// Port 0: RW
+    .clk0     (mem_clk_a[0]),
+    .csb0     (mem_cen_a[0]),
+    .web0     (mem_web_a[0]),
+    .wmask0   (mem0_mask_a),
+    .addr0    (mem0_addr_a),
+    .din0     (mem0_din_a),
+    .dout0    (mem0_dout_a),
+// Port 1: R
+    .clk1     (mem_clk_b[0]),
+    .csb1     (mem_cen_b[0]),
+    .addr1    (mem0_addr_b),
+    .dout1    ()
+  );
+
+sky130_sram_2kbyte_1rw1r_32x512_8 u_sram1_2kb(
+`ifdef USE_POWER_PINS
+    .vccd1 (vccd1),// User area 1 1.8V supply
+    .vssd1 (vssd1),// User area 1 digital ground
+`endif
+// Port 0: RW
+    .clk0     (mem_clk_a[1]),
+    .csb0     (mem_cen_a[1]),
+    .web0     (mem_web_a[1]),
+    .wmask0   (mem1_mask_a),
+    .addr0    (mem1_addr_a),
+    .din0     (mem1_din_a),
+    .dout0    (mem1_dout_a),
+// Port 1: R
+    .clk1     (mem_clk_b[1]),
+    .csb1     (mem_cen_b[1]),
+    .addr1    (mem1_addr_b),
+    .dout1    ()
+  );
+
+sky130_sram_2kbyte_1rw1r_32x512_8 u_sram2_2kb(
+`ifdef USE_POWER_PINS
+    .vccd1 (vccd1),// User area 1 1.8V supply
+    .vssd1 (vssd1),// User area 1 digital ground
+`endif
+// Port 0: RW
+    .clk0     (mem_clk_a[2]),
+    .csb0     (mem_cen_a[2]),
+    .web0     (mem_web_a[2]),
+    .wmask0   (mem2_mask_a),
+    .addr0    (mem2_addr_a),
+    .din0     (mem2_din_a),
+    .dout0    (mem2_dout_a),
+// Port 1: R
+    .clk1     (mem_clk_b[2]),
+    .csb1     (mem_cen_b[2]),
+    .addr1    (mem2_addr_b),
+    .dout1    ()
+  );
+
+
+sky130_sram_2kbyte_1rw1r_32x512_8 u_sram3_2kb(
+`ifdef USE_POWER_PINS
+    .vccd1 (vccd1),// User area 1 1.8V supply
+    .vssd1 (vssd1),// User area 1 digital ground
+`endif
+// Port 0: RW
+    .clk0     (mem_clk_a[3]),
+    .csb0     (mem_cen_a[3]),
+    .web0     (mem_web_a[3]),
+    .wmask0   (mem3_mask_a),
+    .addr0    (mem3_addr_a),
+    .din0     (mem3_din_a),
+    .dout0    (mem3_dout_a),
+// Port 1: R
+    .clk1     (mem_clk_b[3]),
+    .csb1     (mem_cen_b[3]),
+    .addr1    (mem3_addr_b),
+    .dout1    ()
+  );
+
+endmodule
+
diff --git a/verilog/rtl/qspim b/verilog/rtl/qspim
index b9ef372..f7a1f82 160000
--- a/verilog/rtl/qspim
+++ b/verilog/rtl/qspim
@@ -1 +1 @@
-Subproject commit b9ef37289d55f9982427331b4621dc531a09d1d1
+Subproject commit f7a1f824fda54c5103bcbd5b9401f36d28551491
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index fb4aea9..0c0f7cf 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -280,9 +280,12 @@
 wire                           wbd_spim_we_o;  // write
 wire   [WB_WIDTH-1:0]          wbd_spim_dat_o; // data output
 wire   [3:0]                   wbd_spim_sel_o; // byte enable
+wire   [9:0]                   wbd_spim_bl_o;  // Burst count
+wire                           wbd_spim_bry_o; // Busrt Ready
 wire                           wbd_spim_cyc_o ;
 wire   [WB_WIDTH-1:0]          wbd_spim_dat_i; // data input
 wire                           wbd_spim_ack_i; // acknowlegement
+wire                           wbd_spim_lack_i;// Last acknowlegement
 wire                           wbd_spim_err_i;  // error
 
 //---------------------------------------------------------------------
@@ -347,6 +350,7 @@
 wire                              i2c_rst_n     ;// i2c reset
 wire                              usb_rst_n     ;// i2c reset
 wire   [3:0]                      boot_remap    ;// Boot Remap
+wire   [3:0]                      dcache_remap  ;// Remap the dcache address
 wire                              cpu_clk       ;
 wire                              rtc_clk       ;
 wire                              usb_clk       ;
@@ -599,6 +603,7 @@
 assign  cfg_cska_mbist2   = cfg_clk_ctrl2[7:4];
 assign  cfg_cska_mbist3   = cfg_clk_ctrl2[11:8];
 assign  cfg_cska_mbist4   = cfg_clk_ctrl2[15:12];
+assign  dcache_remap      = cfg_clk_ctrl2[27:24];
 assign  boot_remap        = cfg_clk_ctrl2[31:28];
 
 //assign la_data_out    = {riscv_debug,spi_debug,sdram_debug};
@@ -840,8 +845,11 @@
     .wbd_we_i               (wbd_spim_we_o             ), 
     .wbd_dat_i              (wbd_spim_dat_o            ),
     .wbd_sel_i              (wbd_spim_sel_o            ),
+    .wbd_bl_i               (wbd_spim_bl_o             ),
+    .wbd_bry_i              (wbd_spim_bry_o            ),
     .wbd_dat_o              (wbd_spim_dat_i            ),
     .wbd_ack_o              (wbd_spim_ack_i            ),
+    .wbd_lack_o             (wbd_spim_lack_i           ),
     .wbd_err_o              (wbd_spim_err_i            ),
 
     .spi_debug              (spi_debug                 ),
@@ -969,6 +977,7 @@
 
          .clk_i         (wbd_clk_wi_skew       ), 
          .rst_n         (wbd_int_rst_n         ),
+	 .dcache_remap  (dcache_remap          ),
 	 .boot_remap    (boot_remap            ),
 
          // Master 0 Interface
@@ -1009,8 +1018,11 @@
          // .s0_wbd_err_i  (1'b0           ), - Moved inside IP
          .s0_wbd_dat_i  (wbd_spim_dat_i ),
          .s0_wbd_ack_i  (wbd_spim_ack_i ),
+         .s0_wbd_lack_i (wbd_spim_lack_i ),
          .s0_wbd_dat_o  (wbd_spim_dat_o ),
          .s0_wbd_adr_o  (wbd_spim_adr_o ),
+         .s0_wbd_bry_o  (wbd_spim_bry_o ),
+         .s0_wbd_bl_o   (wbd_spim_bl_o ),
          .s0_wbd_sel_o  (wbd_spim_sel_o ),
          .s0_wbd_we_o   (wbd_spim_we_o  ),  
          .s0_wbd_cyc_o  (wbd_spim_cyc_o ),
diff --git a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
index f6ee7d8..14e716e 100644
--- a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
+++ b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
@@ -122,6 +122,13 @@
 	 input logic  [3:0]     boot_remap, // When remap is enabled
 	                                     // [0] - 0x0000_0000 - 0x0000_07FF Map to MBIST1
 					     // [1] - 0x0000_0800 - 0x0000_0FFF Map to MBIST2
+					     // [2] - 0x0000_1000 - 0x0000_17FF Map to MBIST3
+					     // [3] - 0x0000_1800 - 0x0000_1FFF Map to MBIST4
+	 input logic  [3:0]     dcache_remap, // When dcache remap is enabled, 
+	                                     // [0] - 0x0800_0000 - 0x0800_07FF Map to MBIST1
+					     // [1] - 0x0800_0800 - 0x0800_0FFF Map to MBIST2
+					     // [2] - 0x0800_1000 - 0x0800_17FF Map to MBIST3
+					     // [3] - 0x0800_1800 - 0x0800_1FFF Map to MBIST4
          
          // Master 0 Interface
          input   logic	[31:0]	m0_wbd_dat_i,
@@ -132,6 +139,7 @@
          input   logic  	m0_wbd_stb_i,
          output  logic	[31:0]	m0_wbd_dat_o,
          output  logic		m0_wbd_ack_o,
+         output  logic		m0_wbd_lack_o,
          output  logic		m0_wbd_err_o,
          
          // Master 1 Interface
@@ -143,6 +151,7 @@
          input	logic 	        m1_wbd_stb_i,
          output	logic [31:0]	m1_wbd_dat_o,
          output	logic 	        m1_wbd_ack_o,
+         output	logic 	        m1_wbd_lack_o,
          output	logic 	        m1_wbd_err_o,
          
          // Master 2 Interface
@@ -154,16 +163,20 @@
          input	logic 	        m2_wbd_stb_i,
          output	logic [31:0]	m2_wbd_dat_o,
          output	logic 	        m2_wbd_ack_o,
+         output	logic 	        m2_wbd_lack_o,
          output	logic 	        m2_wbd_err_o,
          
          
          // Slave 0 Interface
          input	logic [31:0]	s0_wbd_dat_i,
          input	logic 	        s0_wbd_ack_i,
+         input	logic 	        s0_wbd_lack_i,
          //input	logic 	s0_wbd_err_i, - unused
          output	logic [31:0]	s0_wbd_dat_o,
          output	logic [31:0]	s0_wbd_adr_o,
          output	logic [3:0]	s0_wbd_sel_o,
+         output	logic [9:0]	s0_wbd_bl_o,
+         output	logic 	        s0_wbd_bry_o,
          output	logic 	        s0_wbd_we_o,
          output	logic 	        s0_wbd_cyc_o,
          output	logic 	        s0_wbd_stb_o,
@@ -219,6 +232,8 @@
   logic	[31:0]	wbd_dat;
   logic  [31:0]	wbd_adr;
   logic  [3:0]	wbd_sel;
+  logic  [9:0]	wbd_bl;
+  logic  	wbd_bry;
   logic  	wbd_we;
   logic  	wbd_cyc;
   logic  	wbd_stb;
@@ -229,6 +244,7 @@
 typedef struct packed { 
   logic	[31:0]	wbd_dat;
   logic  	wbd_ack;
+  logic  	wbd_lack;
   logic  	wbd_err;
 } type_wb_rd_intf;
 
@@ -320,6 +336,10 @@
 	                      (boot_remap[1] && m1_wbd_adr_i[31:11] == 21'h1) ? TARGET_MBIST:
 	                      (boot_remap[2] && m1_wbd_adr_i[31:11] == 21'h2) ? TARGET_MBIST:
 	                      (boot_remap[3] && m1_wbd_adr_i[31:11] == 21'h3) ? TARGET_MBIST:
+			      (dcache_remap[0] && m1_wbd_adr_i[31:11] == 21'b0000_1000_0000_0000_0000_0) ? TARGET_MBIST:
+	                      (dcache_remap[1] && m1_wbd_adr_i[31:11] == 21'b0000_1000_0000_0000_0000_1) ? TARGET_MBIST:
+	                      (dcache_remap[2] && m1_wbd_adr_i[31:11] == 21'b0000_1000_0000_0000_0001_0) ? TARGET_MBIST:
+	                      (dcache_remap[3] && m1_wbd_adr_i[31:11] == 21'b0000_1000_0000_0000_0001_1) ? TARGET_MBIST:
 	                      (m1_wbd_adr_i[31:28] ==  4'b0000 ) ? TARGET_SPI_MEM :
                               (m1_wbd_adr_i[31:16] == 16'h1000 ) ? TARGET_SPI_REG :
                               (m1_wbd_adr_i[31:16] == 16'h1001 ) ? TARGET_UART :
@@ -331,6 +351,10 @@
 	                      (boot_remap[1] && m2_wbd_adr_i[31:11] == 21'h1) ? TARGET_MBIST:
 	                      (boot_remap[2] && m2_wbd_adr_i[31:11] == 21'h2) ? TARGET_MBIST:
 	                      (boot_remap[3] && m2_wbd_adr_i[31:11] == 21'h3) ? TARGET_MBIST:
+			      (dcache_remap[0] && m1_wbd_adr_i[31:11] == 21'b0000_1000_0000_0000_0000_0) ? TARGET_MBIST:
+	                      (dcache_remap[1] && m1_wbd_adr_i[31:11] == 21'b0000_1000_0000_0000_0000_1) ? TARGET_MBIST:
+	                      (dcache_remap[2] && m1_wbd_adr_i[31:11] == 21'b0000_1000_0000_0000_0001_0) ? TARGET_MBIST:
+	                      (dcache_remap[3] && m1_wbd_adr_i[31:11] == 21'b0000_1000_0000_0000_0001_1) ? TARGET_MBIST:
 	                      (m2_wbd_adr_i[31:28] ==  4'b0000 ) ? TARGET_SPI_MEM :
                               (m2_wbd_adr_i[31:16] == 16'h1000 ) ? TARGET_SPI_REG :
                               (m2_wbd_adr_i[31:16] == 16'h1001 ) ? TARGET_UART : 
@@ -343,6 +367,8 @@
 assign m0_wb_wr.wbd_dat = m0_wbd_dat_i;
 assign m0_wb_wr.wbd_adr = {m0_wbd_adr_i[31:2],2'b00};
 assign m0_wb_wr.wbd_sel = m0_wbd_sel_i;
+assign m0_wb_wr.wbd_bl  = 'h1;
+assign m0_wb_wr.wbd_bry = 'b1;
 assign m0_wb_wr.wbd_we  = m0_wbd_we_i;
 assign m0_wb_wr.wbd_cyc = m0_wbd_cyc_i;
 assign m0_wb_wr.wbd_stb = m0_wbd_stb_i;
@@ -351,6 +377,8 @@
 assign m1_wb_wr.wbd_dat = m1_wbd_dat_i;
 assign m1_wb_wr.wbd_adr = {m1_wbd_adr_i[31:2],2'b00};
 assign m1_wb_wr.wbd_sel = m1_wbd_sel_i;
+assign m1_wb_wr.wbd_bl  = 'h1;
+assign m1_wb_wr.wbd_bry = 'b1;
 assign m1_wb_wr.wbd_we  = m1_wbd_we_i;
 assign m1_wb_wr.wbd_cyc = m1_wbd_cyc_i;
 assign m1_wb_wr.wbd_stb = m1_wbd_stb_i;
@@ -359,6 +387,8 @@
 assign m2_wb_wr.wbd_dat = m2_wbd_dat_i;
 assign m2_wb_wr.wbd_adr = {m2_wbd_adr_i[31:2],2'b00};
 assign m2_wb_wr.wbd_sel = m2_wbd_sel_i;
+assign m2_wb_wr.wbd_bl  = 'h1;
+assign m2_wb_wr.wbd_bry = 'b1;
 assign m2_wb_wr.wbd_we  = m2_wbd_we_i;
 assign m2_wb_wr.wbd_cyc = m2_wbd_cyc_i;
 assign m2_wb_wr.wbd_stb = m2_wbd_stb_i;
@@ -366,14 +396,17 @@
 
 assign m0_wbd_dat_o  =  m0_wb_rd.wbd_dat;
 assign m0_wbd_ack_o  =  m0_wb_rd.wbd_ack;
+assign m0_wbd_lack_o =  m0_wb_rd.wbd_lack;
 assign m0_wbd_err_o  =  m0_wb_rd.wbd_err;
 
 assign m1_wbd_dat_o  =  m1_wb_rd.wbd_dat;
 assign m1_wbd_ack_o  =  m1_wb_rd.wbd_ack;
+assign m1_wbd_lack_o =  m1_wb_rd.wbd_lack;
 assign m1_wbd_err_o  =  m1_wb_rd.wbd_err;
 
 assign m2_wbd_dat_o  =  m2_wb_rd.wbd_dat;
 assign m2_wbd_ack_o  =  m2_wb_rd.wbd_ack;
+assign m2_wbd_lack_o =  m2_wb_rd.wbd_lack;
 assign m2_wbd_err_o  =  m2_wb_rd.wbd_err;
 
 //----------------------------------------
@@ -383,6 +416,8 @@
  assign  s0_wbd_dat_o =  s0_wb_wr.wbd_dat ;
  assign  s0_wbd_adr_o =  s0_wb_wr.wbd_adr ;
  assign  s0_wbd_sel_o =  s0_wb_wr.wbd_sel ;
+ assign  s0_wbd_bl_o  =  s0_wb_wr.wbd_bl ;
+ assign  s0_wbd_bry_o =  s0_wb_wr.wbd_bry ;
  assign  s0_wbd_we_o  =  s0_wb_wr.wbd_we  ;
  assign  s0_wbd_cyc_o =  s0_wb_wr.wbd_cyc ;
  assign  s0_wbd_stb_o =  s0_wb_wr.wbd_stb ;
@@ -409,20 +444,24 @@
  assign  s3_wbd_stb_o =  s3_wb_wr.wbd_stb ;
  
  
- assign s0_wb_rd.wbd_dat  = s0_wbd_dat_i ;
- assign s0_wb_rd.wbd_ack  = s0_wbd_ack_i ;
+ assign s0_wb_rd.wbd_dat   = s0_wbd_dat_i ;
+ assign s0_wb_rd.wbd_ack   = s0_wbd_ack_i ;
+ assign s0_wb_rd.wbd_lack  = s0_wbd_lack_i ;
  assign s0_wb_rd.wbd_err  = 1'b0; // s0_wbd_err_i ; - unused
  
  assign s1_wb_rd.wbd_dat  = s1_wbd_dat_i ;
  assign s1_wb_rd.wbd_ack  = s1_wbd_ack_i ;
+ assign s1_wb_rd.wbd_lack  = s1_wbd_ack_i ;
  assign s1_wb_rd.wbd_err  = 1'b0; // s1_wbd_err_i ; - unused
  
  assign s2_wb_rd.wbd_dat  = s2_wbd_dat_i ;
  assign s2_wb_rd.wbd_ack  = s2_wbd_ack_i ;
+ assign s2_wb_rd.wbd_lack = s2_wbd_ack_i ;
  assign s2_wb_rd.wbd_err  = 1'b0; // s2_wbd_err_i ; - unused
 
  assign s3_wb_rd.wbd_dat  = s3_wbd_dat_i ;
  assign s3_wb_rd.wbd_ack  = s3_wbd_ack_i ;
+ assign s3_wb_rd.wbd_lack = s3_wbd_ack_i ;
  assign s3_wb_rd.wbd_err  = 1'b0; // s3_wbd_err_i ; - unused
 
 //
@@ -433,9 +472,9 @@
 wb_arb	u_wb_arb(
 	.clk(clk_i), 
 	.rstn(rst_n),
-	.req({	m2_wbd_stb_i & !m2_wbd_ack_o,
-		m1_wbd_stb_i & !m1_wbd_ack_o,
-		m0_wbd_stb_i & !m0_wbd_ack_o}),
+	.req({	m2_wbd_stb_i & !m2_wbd_lack_o,
+		m1_wbd_stb_i & !m1_wbd_lack_o,
+		m0_wbd_stb_i & !m0_wbd_lack_o}),
 	.gnt(gnt)
 );
 
@@ -484,21 +523,27 @@
          .m_wbd_dat_i      (m_bus_wr.wbd_dat    ),
          .m_wbd_adr_i      (m_bus_wr.wbd_adr    ),
          .m_wbd_sel_i      (m_bus_wr.wbd_sel    ),
+         .m_wbd_bl_i       (m_bus_wr.wbd_bl     ),
+         .m_wbd_bry_i      (m_bus_wr.wbd_bry    ),
          .m_wbd_we_i       (m_bus_wr.wbd_we     ),
          .m_wbd_cyc_i      (m_bus_wr.wbd_cyc    ),
          .m_wbd_stb_i      (m_bus_wr.wbd_stb    ),
          .m_wbd_tid_i      (m_bus_wr.wbd_tid    ),
          .m_wbd_dat_o      (m_bus_rd.wbd_dat    ),
          .m_wbd_ack_o      (m_bus_rd.wbd_ack    ),
+         .m_wbd_lack_o     (m_bus_rd.wbd_lack   ),
          .m_wbd_err_o      (m_bus_rd.wbd_err    ),
 
          // Slave Interface
          .s_wbd_dat_i      (s_bus_rd.wbd_dat    ),
          .s_wbd_ack_i      (s_bus_rd.wbd_ack    ),
+         .s_wbd_lack_i     (s_bus_rd.wbd_lack   ),
          .s_wbd_err_i      (s_bus_rd.wbd_err    ),
          .s_wbd_dat_o      (s_bus_wr.wbd_dat    ),
          .s_wbd_adr_o      (s_bus_wr.wbd_adr    ),
          .s_wbd_sel_o      (s_bus_wr.wbd_sel    ),
+         .s_wbd_bl_o       (s_bus_wr.wbd_bl    ),
+         .s_wbd_bry_o      (s_bus_wr.wbd_bry    ),
          .s_wbd_we_o       (s_bus_wr.wbd_we     ),
          .s_wbd_cyc_o      (s_bus_wr.wbd_cyc    ),
          .s_wbd_stb_o      (s_bus_wr.wbd_stb    ),