diff --git a/verilog/dv/riscv_regress/Makefile b/verilog/dv/riscv_regress/Makefile
index f6e545f..8aac4cc 100644
--- a/verilog/dv/riscv_regress/Makefile
+++ b/verilog/dv/riscv_regress/Makefile
@@ -172,14 +172,14 @@
 ifeq (,$(findstring e,$(ARCH_lowercase)))
 	# These tests cannot be compiled for RVE
 	# Comment this target if you don't want to run the riscv_isa
-	TARGETS += riscv_isa
+	#TARGETS += riscv_isa
 
 	# Comment this target if you don't want to run the riscv_compliance
-	TARGETS += riscv_compliance
+	#TARGETS += riscv_compliance
 endif
 
 # Comment this target if you don't want to run the isr_sample
-#TARGETS += isr_sample
+TARGETS += isr_sample
 
 # Comment this target if you don't want to run the coremark
 #TARGETS += coremark
@@ -283,15 +283,20 @@
 	printf "$$(cat $(test_results)) \n"
 
 run_iverilog_wf: $(test_info)
-	$(MAKE) -C $(root_dir)/sim build_iverilog_wf SIM_CFG_DEF=$(SIM_CFG_DEF) SIM_TRACE_DEF=$(SIM_TRACE_DEF) SIM_BUILD_OPTS=$(SIM_BUILD_OPTS); \
-	printf "" > $(test_results); \
 	cd $(bld_dir); \
-        iverilog-vpi ../../sim/iverilog_vpi/system.c; \
+	iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_AGENTS)    \
+	-I $(UPRJ_INCLUDE_PATH1)    -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
+	-I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_TESTS_PATH) \
+	$(sv_list) \
+	-o $(top_module).vvp; \
+	printf "" > $(test_results); \
+        iverilog-vpi ../../../vpi/system/system.c; \
 	vvp  -M. -msystem  $(top_module).vvp \
 	+test_info=$(test_info) \
 	+test_results=$(test_results) \
-	+imem_pattern=$(imem_pattern) \
-	+dmem_pattern=$(dmem_pattern) \
 	| tee $(sim_results)  ;\
 	printf "Simulation performed on $$(vvp -V) \n" ;\
 	printf "                          Test               | build | simulation \n" ; \
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/isr_sample/isr_sample.S b/verilog/rtl/syntacore/scr1/sim/tests/isr_sample/isr_sample.S
index 6855370..288b8fb 100644
--- a/verilog/rtl/syntacore/scr1/sim/tests/isr_sample/isr_sample.S
+++ b/verilog/rtl/syntacore/scr1/sim/tests/isr_sample/isr_sample.S
@@ -11,9 +11,9 @@
 #define MCAUSE_TMR_IRQ              (1 << 31 | IRQ_M_TIMER)
 
 // IPIC
-#define IRQ_LINES_ADDR              0xF0000100      // simulation
-#define TRIG_EXT_IRQ_ADDR           0xF0000100      // external irq is triggered when tb memory is set to non-zero
-#define TRIG_SW_IRQ_ADDR            0xF0000200      // software irq is triggered when tb memory is set to non-zero
+#define IRQ_LINES_ADDR              0x3000000C      // simulation
+#define TRIG_EXT_IRQ_ADDR           0x3000000C      // external irq is triggered when tb memory is set to non-zero // Bit [15:0]
+#define TRIG_SW_IRQ_ADDR            0x3000000C      // software irq is triggered when tb memory is set to non-zero // Bit [16]
 
 #define IPIC_EOI                    0xBF4           // end of interrupt
 #define IPIC_SOI                    0xBF5           // start of interrupt
@@ -178,8 +178,8 @@
     /// configuring software interrupt /// 
     csrw                mie, zero                      // disable all interrupts
     li                  t0, TRIG_SW_IRQ_ADDR
-    li                  t1, 0x00000001
-    sh                  t1, (t0)                       //send command to generate software interrupt 
+    li                  t1, 0x00010000
+    sw                  t1, (t0)                       //send command to generate software interrupt 
     li                  t0, MSIE
     csrs                mie, t0                        // enable software interrupt 
     nop
@@ -272,7 +272,7 @@
     csrc            mie, t0                 // disable software interrupt 
     li              t0, TRIG_SW_IRQ_ADDR
     li              t1, 0x00000000
-    sh              t1, (t0)                // send command to stop generating  software interrupt 
+    sw              t1, (t0)                // send command to stop generating  software interrupt 
     li              t0, MIP_MSIP
     csrc            mip, t0
     csrr            t1, mip
diff --git a/verilog/rtl/syntacore/scr1/src/includes/scr1_arch_description.svh b/verilog/rtl/syntacore/scr1/src/includes/scr1_arch_description.svh
index 71b9928..c00ffe3 100644
--- a/verilog/rtl/syntacore/scr1/src/includes/scr1_arch_description.svh
+++ b/verilog/rtl/syntacore/scr1/src/includes/scr1_arch_description.svh
@@ -227,7 +227,7 @@
 // Addresses used in testbench
 localparam [`SCR1_XLEN-1:0]      SCR1_SIM_EXIT_ADDR      = 32'h0000_00F8;
 localparam [`SCR1_XLEN-1:0]      SCR1_SIM_PRINT_ADDR     = 32'hF000_0000;
-localparam [`SCR1_XLEN-1:0]      SCR1_SIM_EXT_IRQ_ADDR   = 32'hF000_0100;
-localparam [`SCR1_XLEN-1:0]      SCR1_SIM_SOFT_IRQ_ADDR  = 32'hF000_0200;
+localparam [`SCR1_XLEN-1:0]      SCR1_SIM_EXT_IRQ_ADDR   = 32'h3000_000C; // Bit [15:0]
+localparam [`SCR1_XLEN-1:0]      SCR1_SIM_SOFT_IRQ_ADDR  = 32'h3000_000C; // Bit[16]
 
 `endif // SCR1_ARCH_DESCRIPTION_SVH
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_intf.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_intf.sv
index bb51ee9..b0efee3 100644
--- a/verilog/rtl/syntacore/scr1/src/top/scr1_intf.sv
+++ b/verilog/rtl/syntacore/scr1/src/top/scr1_intf.sv
@@ -121,6 +121,7 @@
 `endif
     // Memory-mapped external timer
     output   logic [63:0]                           timer_val,          // Machine timer value
+    output   logic                                  timer_irq,
     // Instruction Memory Interface
     output   logic                                  core_imem_req_ack,        // IMEM request acknowledge
     input    logic                                  core_imem_req,            // IMEM request
@@ -197,7 +198,6 @@
 logic [`SCR1_DMEM_DWIDTH-1:0]                       timer_dmem_rdata;
 logic [1:0]                                         timer_dmem_resp;
 
-logic                                               timer_irq;
 
 
 //---------------------------------------------------------------------------------
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv
index 302adda..adc8f86 100644
--- a/verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv
+++ b/verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv
@@ -40,6 +40,8 @@
 ////             Async fifo added in imem and dmem path           ////
 ////     v2:    July 7, 2021, Dinesh A                            ////
 ////            64bit debug signal added                          ////
+////     v3:    Aug 23, 2021, Dinesh A                            ////
+////            timer_irq connective bug fix                      ////
 ////                                                              ////
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
@@ -293,6 +295,7 @@
 `endif
     // Memory-mapped external timer
     .timer_val                          (timer_val),          // Machine timer value
+    .timer_irq                          (timer_irq),          // Machine timer value
     // Instruction Memory Interface
     .core_imem_req_ack                  (core_imem_req_ack),  // IMEM request acknowledge
     .core_imem_req                      (core_imem_req),      // IMEM request