diff --git a/README.md b/README.md
index b962a9f..01f8de5 100644
--- a/README.md
+++ b/README.md
@@ -27,6 +27,8 @@
 - [Tests preparation](#tests-preparation)
     - [Running Simuation](#running-simulation)
 - [Tool sets](#tool-sets)
+- [News](#news)
+- [Contacts](#contacts)
 - [Documentation](#documentation)
 
 
@@ -592,16 +594,72 @@
     4. `CVC` - Performs Circuit Validity Checks
 
 
+# News
+* **Riscduino Aim** - https://www.youtube.com/watch?v=lFVnicPhTI0
 
-## Contacts
+# MPW Shuttle
+<table>
+  <tr>
+    <td  align="center"> MPW</td> 
+    <td  align="center"> Tape-out</td>
+    <td  align="center"> Project Name</td>
+    <td  align="center"> Project Details</td>
+    <td  align="center"> Github</td>
+    <td  align="center"> Efabless</td>
+  </tr>
+  <tr>
+    <td  align="center"> MPW-2 </td> 
+    <td  align="center"> 18-June-2021  </td>
+    <td  align="center"> YiFive</td>
+    <td  align="center"> Single 32bit RISCV core without cache + SDRAM Controller + WB Interconnect</td>
+    <td  align="center"> <a href="https://github.com/dineshannayya/yifive">Github</a><> </td>
+    <td  align="center"> <a href="https://platform.efabless.com/projects/152">Efabless</a><> </td>
+  </tr>
+  <tr>
+    <td  align="center"> MPW-3 </td> 
+    <td  align="center"> 15-Nov-2021  </td>
+    <td  align="center"> Riscduino</td>
+    <td  align="center"> Single 32bit RISCV core without cache + Onchip SRAM + WB Interconnect</td>
+    <td  align="center"> <a href="https://github.com/dineshannayya/riscduino">Github</a><> </td>
+    <td  align="center"> <a https://platform.efabless.com/projects/385">Efabless</a><> </td>
+  </tr>
+  <tr>
+    <td  align="center"> MPW-4 </td> 
+    <td  align="center"> 31-Dec-2021  </td>
+    <td  align="center"> Riscduino-R1</td>
+    <td  align="center"> Single 32bit RISCV core with cache + Onchip SRAM + WB Inter Connect</td>
+    <td  align="center"> <a href="https://github.com/dineshannayya/riscduino">Github</a><> </td>
+    <td  align="center"> <a https://platform.efabless.com/projects/575">Efabless</a><> </td>
+  </tr>
+  <tr>
+    <td  align="center"> MPW-5 </td> 
+    <td  align="center"> 21-Mar-2022  </td>
+    <td  align="center"> Riscduino-SCORE</td>
+    <td  align="center"> Single 32bit RISCV core with cache + Onchip SRAM+ WB Cross Bar</td>
+    <td  align="center"> <a href="https://github.com/dineshannayya/riscduino">Github</a><> </td>
+    <td  align="center"> <a https://platform.efabless.com/projects/670">Efabless</a><> </td>
+  </tr>
+  <tr>
+    <td  align="center"> MPW-5 </td> 
+    <td  align="center"> 21-Mar-2022  </td>
+    <td  align="center"> Riscduino-DCORE</td>
+    <td  align="center"> Dual 32bit RISCV core with cache + Onchip SRAM+ WB Cross Bar</td>
+    <td  align="center"> <a href="https://github.com/dineshannayya/riscduino_dcore">Github</a><> </td>
+    <td  align="center"> <a https://platform.efabless.com/projects/718">Efabless</a><> </td>
+  </tr>
+  <tr>
+    <td  align="center"> MPW-5 </td> 
+    <td  align="center"> 21-Mar-2022  </td>
+    <td  align="center"> Riscduino-QCORE</td>
+    <td  align="center"> Quad 32bit RISCV core with cache + Onchip SRAM+ WB Cross Bar</td>
+    <td  align="center"> <a href="https://github.com/dineshannayya/riscduino_qcore">Github</a><> </td>
+    <td  align="center"> <a https://platform.efabless.com/projects/782">Efabless</a><> </td>
+  </tr>
+</table>
+
+# Contacts
 
 Report an issue: <https://github.com/dineshannayya/riscduino/issues>
 
 # Documentation
 * **Syntacore Link** - https://github.com/syntacore/scr1
-
-News on Riscduino
-===============
-* **Riscduino Aim** - https://www.youtube.com/watch?v=lFVnicPhTI0
-
-