diff --git a/README.md b/README.md
index 50ea5f5..bfa78f9 100644
--- a/README.md
+++ b/README.md
@@ -660,7 +660,7 @@
 
 # Contacts
 
-Report an issue: <https://github.com/dineshannayya/riscduino/issues>
+Report an issue: <https://github.com/dineshannayya/riscduino_qcore/issues>
 
 # Documentation
 * **Syntacore Link** - https://github.com/syntacore/scr1
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index 055b296..c4ee99f 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -4,8 +4,8 @@
 
 u_riscv_top.i_core_top_0    50	            1400 	   N
 u_riscv_top.i_core_top_1    1200	    1400	   FN
-u_riscv_top.i_core_top_2    50	            2450 	   N
-u_riscv_top.i_core_top_3    1200	    2450	   FN
+u_riscv_top.i_core_top_2    50	            2475 	   N
+u_riscv_top.i_core_top_3    1200	    2475	   FN
 u_riscv_top.u_connect       725	            1400	   N
 u_riscv_top.u_intf          950 	    650	           N
 u_icache_2kb                150             130            N
diff --git a/openlane/ycr_core_top/config.tcl b/openlane/ycr_core_top/config.tcl
index ffbc279..4eb836f 100644
--- a/openlane/ycr_core_top/config.tcl
+++ b/openlane/ycr_core_top/config.tcl
@@ -18,7 +18,8 @@
 set ::env(ROUTING_CORES) "6"
 
 set ::env(DESIGN_NAME) ycr_core_top
-set ::env(DESIGN_IS_CORE) 0
+set ::env(DESIGN_IS_CORE) "0"
+set ::env(FP_PDN_CORE_RING) "0"
 
 set ::env(CLOCK_PERIOD) "10"
 set ::env(CLOCK_PORT) "clk"
@@ -71,10 +72,10 @@
 ## Floorplan
 set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
 set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 580 930 "
+set ::env(DIE_AREA) "0 0 590 960 "
 
 set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg
-set ::env(PL_TARGET_DENSITY) 0.38
+set ::env(PL_TARGET_DENSITY) 0.37
 set ::env(CELL_PAD) "6"
 
 set ::env(GLB_RT_MAXLAYER) 5
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index 05ba7f1..db85b1d 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow completed,1h2m47s0ms,0h4m13s0ms,-2.0,-1,-1,-1,588.16,14,0,0,0,0,0,0,-1,0,0,-1,-1,1516980,13216,0.0,-1,-1,0.0,0.0,0.0,-1,-1,0.0,0.0,-1,0.0,7.65,8.91,1.7,2.19,0.0,389,4273,389,4273,0,0,0,14,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,90,0.55,0.3,sky130_fd_sc_hd,4,0
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow completed,1h5m44s0ms,0h4m36s0ms,-2.0,-1,-1,-1,586.6,14,0,0,0,0,0,0,-1,0,0,-1,-1,1525321,14003,0.0,-1,-1,0.0,0.0,0.0,-1,-1,0.0,0.0,-1,0.0,7.9,9.34,1.49,2.29,0.0,389,4273,389,4273,0,0,0,14,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,90,0.55,0.3,sky130_fd_sc_hd,4,0
diff --git a/signoff/ycr4_iconnect/final_summary_report.csv b/signoff/ycr4_iconnect/final_summary_report.csv
index 6b94665..7fce1fa 100644
--- a/signoff/ycr4_iconnect/final_summary_report.csv
+++ b/signoff/ycr4_iconnect/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/ycr4_iconnect,ycr4_iconnect,ycr4_iconnect,flow completed,0h38m19s0ms,0h31m37s0ms,11686.98060941828,0.722,5843.49030470914,5.29,1569.5,4219,0,0,0,0,0,0,0,177,0,0,-1,1273610,69630,0.0,0.0,-1,0.0,0.0,0.0,0.0,-1,0.0,0.0,1054561473.0,0.0,28.17,58.08,14.25,56.9,-1,4301,10616,622,6874,0,0,0,4568,425,85,139,123,430,136,20,1551,1026,730,22,1380,9688,0,11068,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.2,0.3,sky130_fd_sc_hd,14,3
+0,/project/openlane/ycr4_iconnect,ycr4_iconnect,ycr4_iconnect,flow completed,0h50m5s0ms,0h40m33s0ms,11700.831024930747,0.722,5850.4155124653735,5.28,1442.88,4224,0,0,0,0,0,0,0,171,0,0,-1,1207613,66195,0.0,0.0,-1,0.0,0.0,0.0,0.0,-1,0.0,0.0,1018439984.0,0.0,28.82,56.67,8.96,52.15,-1,4217,10502,618,6840,0,0,0,4488,417,87,147,120,427,148,8,1550,1027,731,19,1380,9688,0,11068,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.2,0.3,sky130_fd_sc_hd,14,3
diff --git a/signoff/ycr_core_top/final_summary_report.csv b/signoff/ycr_core_top/final_summary_report.csv
index 91617ca..e32df54 100644
--- a/signoff/ycr_core_top/final_summary_report.csv
+++ b/signoff/ycr_core_top/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/ycr_core_top,ycr_core_top,ycr_core_top,flow completed,0h59m58s0ms,0h49m49s0ms,75335.55802743789,0.5394,37667.779013718944,37.72,2294.39,20318,0,0,0,0,0,0,0,147,0,0,-1,1254475,182224,0.0,-8.36,-1,0.0,0.0,0.0,-8104.68,-1,0.0,0.0,962392628.0,0.0,51.91,69.19,23.06,51.39,-1,16388,22628,537,6677,0,0,0,19143,686,261,526,603,2869,894,266,4810,2496,2403,42,666,7370,0,8036,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.38,0.3,sky130_fd_sc_hd,6,3
+0,/project/openlane/ycr_core_top,ycr_core_top,ycr_core_top,flow completed,0h41m10s0ms,0h32m59s0ms,72853.10734463276,0.5664,36426.55367231638,36.53,2336.21,20632,0,0,0,0,0,0,0,156,0,0,-1,1330305,186613,0.0,-9.27,-1,0.0,0.0,0.0,-8367.8,-1,0.0,0.0,1042199582.0,0.0,49.66,70.89,25.54,53.73,-1,16396,22729,542,6775,0,0,0,19178,557,261,518,596,2917,897,259,4835,2528,2435,36,688,7612,0,8300,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.37,0.3,sky130_fd_sc_hd,6,3
diff --git a/signoff/ycr_intf/final_summary_report.csv b/signoff/ycr_intf/final_summary_report.csv
index 2eb6cfe..3b861e4 100644
--- a/signoff/ycr_intf/final_summary_report.csv
+++ b/signoff/ycr_intf/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/ycr_intf,ycr_intf,ycr_intf,flow completed,0h21m46s0ms,0h10m38s0ms,60171.875,0.512,30085.9375,33.89,1969.86,15404,0,0,0,0,0,0,0,80,0,0,-1,1129521,148621,-6.74,-21.03,-1,0.0,0.0,-9567.3,-29197.47,-1,0.0,0.0,810410684.0,0.0,67.78,55.22,40.54,30.01,-1,9027,17783,900,9282,0,0,0,11541,549,128,352,277,1962,916,379,1530,2988,2779,24,454,6984,0,7438,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.38,0.3,sky130_fd_sc_hd,4,4
+0,/project/openlane/ycr_intf,ycr_intf,ycr_intf,flow completed,0h30m11s0ms,0h17m28s0ms,60675.78125,0.512,30337.890625,34.18,2036.78,15533,0,0,0,0,0,0,0,96,0,0,-1,1153189,147312,-6.78,-20.93,-1,0.0,0.0,-9651.06,-29117.39,-1,0.0,0.0,829937169.0,0.0,65.33,54.11,46.0,34.52,-1,8844,17559,900,9282,0,0,0,11360,577,129,292,278,1938,890,375,1584,2991,2779,24,454,6984,0,7438,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.38,0.3,sky130_fd_sc_hd,4,4
diff --git a/verilog/rtl/yifive/ycr4c b/verilog/rtl/yifive/ycr4c
index 5f18b62..7841cdc 160000
--- a/verilog/rtl/yifive/ycr4c
+++ b/verilog/rtl/yifive/ycr4c
@@ -1 +1 @@
-Subproject commit 5f18b62e9ee613c4cf9664ccfbf069bb5ca8be12
+Subproject commit 7841cdc26eafd7ebd83aadc4e0a9a7da5a13da3f