diff --git a/README.md b/README.md
index 8bc464b..bb20207 100644
--- a/README.md
+++ b/README.md
@@ -37,7 +37,7 @@
 
 # Overview
 
-Riscduino is a Quad 32 bit RISC V based SOC design pin compatible to arudino platform and this soc targetted for efabless Shuttle program.  This project uses only open source tool set for simulation,synthesis and backend tools.  The SOC flow follow the openlane methodology and SOC environment is compatible with efabless/carvel methodology.
+Riscduino is a Quad 32 bit RISC V based SOC design pin compatible to arduino platform and this soc targetted for efabless Shuttle program.  This project uses only open source tool set for simulation,synthesis and backend tools.  The SOC flow follow the openlane methodology and SOC environment is compatible with efabless/carvel methodology.
 <table>
   <tr>
     <td  align="center"><img src="./docs/source/_static/Riscduino_Integration.png" ></td>
@@ -70,7 +70,7 @@
     * 6 Channel ADC (in Progress)
     * 6 x PWM
     * 3 x Timer (16 Bit), 1us/1ms/1second resolution
-    * Pin Compatbible to arudino uno
+    * Pin Compatbible to arduino uno
     * Wishbone compatible design
     * Written in System Verilog
     * Open-source tool set