| # ////////////////////////////////////////////////////////////////////////////// |
| # // SPDX-FileCopyrightText: 2021, Dinesh Annayya |
| # // |
| # // Licensed under the Apache License, Version 2.0 (the "License"); |
| # // you may not use this file except in compliance with the License. |
| # // You may obtain a copy of the License at |
| # // |
| # // http://www.apache.org/licenses/LICENSE-2.0 |
| # // |
| # // Unless required by applicable law or agreed to in writing, software |
| # // distributed under the License is distributed on an "AS IS" BASIS, |
| # // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| # // See the License for the specific language governing permissions and |
| # // limitations under the License. |
| # // SPDX-License-Identifier: Apache-2.0 |
| # // SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org> |
| # // ////////////////////////////////////////////////////////////////////////// |
| #add -DWFDUMP to enable waveform dump |
| iverilog -DWFDUMP -g2005-sv -DFUNCTIONAL -DSIM -I $PDK_PATH \ |
| -I $CARAVEL_ROOT/verilog/dv/caravel -I $CARAVEL_ROOT/verilog/rtl \ |
| -I ../model -I ../agents -I ../../../verilog/rtl -I ../../../verilog \ |
| -I ../../../verilog/rtl/syntacore/scr1/src/includes -I ../../../verilog/rtl/sdram_ctrl/src/defs \ |
| risc_boot_tb.v -o risc_boot.vvp |
| |
| vvp risc_boot.vvp |
| rm risc_boot.vvp |
