#BUS_SORT

#MANUAL_PLACE


#S
rst_n            0000 0        


#E
cfg_cska_mbist\[3\]  0000 0 4
cfg_cska_mbist\[2\]
cfg_cska_mbist\[1\]
cfg_cska_mbist\[0\]
wb_clk2_i         
wb_clk_i         
wbd_clk_mbist
wbd_clk_int         

wb_cyc_i            0025 0 2
wb_stb_i
wb_we_i
wb_cs_i\[1\]
wb_cs_i\[0\]
wb_adr_i\[8\]
wb_adr_i\[7\]
wb_adr_i\[6\]
wb_adr_i\[5\]
wb_adr_i\[4\]
wb_adr_i\[3\]
wb_adr_i\[2\]
wb_adr_i\[1\]
wb_adr_i\[0\]
wb_dat_i\[31\]
wb_dat_i\[30\]
wb_dat_i\[29\]
wb_dat_i\[28\]
wb_dat_i\[27\]
wb_dat_i\[26\]
wb_dat_i\[25\]
wb_dat_i\[24\]
wb_dat_i\[23\]
wb_dat_i\[22\]
wb_dat_i\[21\]
wb_dat_i\[20\]
wb_dat_i\[19\]
wb_dat_i\[18\]
wb_dat_i\[17\]
wb_dat_i\[16\]
wb_dat_i\[15\]
wb_dat_i\[14\]
wb_dat_i\[13\]
wb_dat_i\[12\]
wb_dat_i\[11\]
wb_dat_i\[10\]
wb_dat_i\[9\]
wb_dat_i\[8\]
wb_dat_i\[7\]
wb_dat_i\[6\]
wb_dat_i\[5\]
wb_dat_i\[4\]
wb_dat_i\[3\]
wb_dat_i\[2\]
wb_dat_i\[1\]
wb_dat_i\[0\]
wb_sel_i\[3\]
wb_sel_i\[2\]
wb_sel_i\[1\]
wb_sel_i\[0\]
wb_dat_o\[31\]
wb_dat_o\[30\]
wb_dat_o\[29\]
wb_dat_o\[28\]
wb_dat_o\[27\]
wb_dat_o\[26\]
wb_dat_o\[25\]
wb_dat_o\[24\]
wb_dat_o\[23\]
wb_dat_o\[22\]
wb_dat_o\[21\]
wb_dat_o\[20\]
wb_dat_o\[19\]
wb_dat_o\[18\]
wb_dat_o\[17\]
wb_dat_o\[16\]
wb_dat_o\[15\]
wb_dat_o\[14\]
wb_dat_o\[13\]
wb_dat_o\[12\]
wb_dat_o\[11\]
wb_dat_o\[10\]
wb_dat_o\[9\]
wb_dat_o\[8\]
wb_dat_o\[7\]
wb_dat_o\[6\]
wb_dat_o\[5\]
wb_dat_o\[4\]
wb_dat_o\[3\]
wb_dat_o\[2\]
wb_dat_o\[1\]
wb_dat_o\[0\]
wb_ack_o
wb_err_o


bist_error_cnt3\[3\] 0150 0 2
bist_error_cnt3\[2\]
bist_error_cnt3\[1\]
bist_error_cnt3\[0\]
bist_correct\[3\]
bist_error\[3\]
bist_error_cnt2\[3\]
bist_error_cnt2\[2\]
bist_error_cnt2\[1\]
bist_error_cnt2\[0\]
bist_correct\[2\]
bist_error\[2\]
bist_error_cnt1\[3\]
bist_error_cnt1\[2\]
bist_error_cnt1\[1\]
bist_error_cnt1\[0\]
bist_correct\[1\]
bist_error\[1\]
bist_error_cnt0\[3\]
bist_error_cnt0\[2\]
bist_error_cnt0\[1\]
bist_error_cnt0\[0\]
bist_correct\[0\]
bist_error\[0\]
bist_done
bist_sdo
bist_shift
bist_sdi
bist_load
bist_run
bist_en           

#S
mem_clk_a\[0\]       250 0 2
mem_cen_a\[0\]
mem_web_a\[0\]
mem_addr_a0\[0\]
mem_addr_a0\[1\]
mem_addr_a0\[2\]
mem_addr_a0\[3\]
mem_addr_a0\[4\]
mem_addr_a0\[5\]
mem_addr_a0\[6\]
mem_addr_a0\[7\]
mem_addr_a0\[8\]
mem_mask_a0\[0\]
mem_mask_a0\[1\]
mem_mask_a0\[2\]
mem_mask_a0\[3\]
mem_din_a0\[0\]
mem_din_a0\[1\]
mem_din_a0\[2\]
mem_din_a0\[3\]
mem_din_a0\[4\]
mem_din_a0\[5\]
mem_din_a0\[6\]
mem_din_a0\[7\]
mem_din_a0\[8\]
mem_din_a0\[9\]
mem_din_a0\[10\]
mem_din_a0\[11\]
mem_din_a0\[12\]
mem_din_a0\[13\]
mem_din_a0\[14\]
mem_din_a0\[15\]
mem_din_a0\[16\]
mem_din_a0\[17\]
mem_din_a0\[18\]
mem_din_a0\[19\]
mem_din_a0\[20\]
mem_din_a0\[21\]
mem_din_a0\[22\]
mem_din_a0\[23\]
mem_din_a0\[24\]
mem_din_a0\[25\]
mem_din_a0\[26\]
mem_din_a0\[27\]
mem_din_a0\[28\]
mem_din_a0\[29\]
mem_din_a0\[30\]
mem_din_a0\[31\]


mem_dout_a0\[0\]  350 0 2
mem_dout_a0\[1\]
mem_dout_a0\[2\]
mem_dout_a0\[3\]
mem_dout_a0\[4\]
mem_dout_a0\[5\]
mem_dout_a0\[6\]
mem_dout_a0\[7\]
mem_dout_a0\[8\]
mem_dout_a0\[9\]
mem_dout_a0\[10\]
mem_dout_a0\[11\]
mem_dout_a0\[12\]
mem_dout_a0\[13\]
mem_dout_a0\[14\]
mem_dout_a0\[15\]
mem_dout_a0\[16\]
mem_dout_a0\[17\]
mem_dout_a0\[18\]
mem_dout_a0\[19\]
mem_dout_a0\[20\]
mem_dout_a0\[21\]
mem_dout_a0\[22\]
mem_dout_a0\[23\]
mem_dout_a0\[24\]
mem_dout_a0\[25\]
mem_dout_a0\[26\]
mem_dout_a0\[27\]
mem_dout_a0\[28\]
mem_dout_a0\[29\]
mem_dout_a0\[30\]
mem_dout_a0\[31\]


mem_clk_b\[0\]    0450 0 2
mem_cen_b\[0\]
mem_addr_b0\[8\]
mem_addr_b0\[7\]
mem_addr_b0\[6\]
mem_addr_b0\[5\]
mem_addr_b0\[4\]
mem_addr_b0\[3\]
mem_addr_b0\[2\]
mem_addr_b0\[1\]
mem_addr_b0\[0\]


mem_clk_a\[1\]       1000 0 2
mem_cen_a\[1\]
mem_web_a\[1\]
mem_addr_a1\[0\]
mem_addr_a1\[1\]
mem_addr_a1\[2\]
mem_addr_a1\[3\]
mem_addr_a1\[4\]
mem_addr_a1\[5\]
mem_addr_a1\[6\]
mem_addr_a1\[7\]
mem_addr_a1\[8\]
mem_mask_a1\[0\]
mem_mask_a1\[1\]
mem_mask_a1\[2\]
mem_mask_a1\[3\]
mem_din_a1\[0\]
mem_din_a1\[1\]
mem_din_a1\[2\]
mem_din_a1\[3\]
mem_din_a1\[4\]
mem_din_a1\[5\]
mem_din_a1\[6\]
mem_din_a1\[7\]
mem_din_a1\[8\]
mem_din_a1\[9\]
mem_din_a1\[10\]
mem_din_a1\[11\]
mem_din_a1\[12\]
mem_din_a1\[13\]
mem_din_a1\[14\]
mem_din_a1\[15\]
mem_din_a1\[16\]
mem_din_a1\[17\]
mem_din_a1\[18\]
mem_din_a1\[19\]
mem_din_a1\[20\]
mem_din_a1\[21\]
mem_din_a1\[22\]
mem_din_a1\[23\]
mem_din_a1\[24\]
mem_din_a1\[25\]
mem_din_a1\[26\]
mem_din_a1\[27\]
mem_din_a1\[28\]
mem_din_a1\[29\]
mem_din_a1\[30\]
mem_din_a1\[31\]


mem_dout_a1\[0\]  1100 0 2
mem_dout_a1\[1\]
mem_dout_a1\[2\]
mem_dout_a1\[3\]
mem_dout_a1\[4\]
mem_dout_a1\[5\]
mem_dout_a1\[6\]
mem_dout_a1\[7\]
mem_dout_a1\[8\]
mem_dout_a1\[9\]
mem_dout_a1\[10\]
mem_dout_a1\[11\]
mem_dout_a1\[12\]
mem_dout_a1\[13\]
mem_dout_a1\[14\]
mem_dout_a1\[15\]
mem_dout_a1\[16\]
mem_dout_a1\[17\]
mem_dout_a1\[18\]
mem_dout_a1\[19\]
mem_dout_a1\[20\]
mem_dout_a1\[21\]
mem_dout_a1\[22\]
mem_dout_a1\[23\]
mem_dout_a1\[24\]
mem_dout_a1\[25\]
mem_dout_a1\[26\]
mem_dout_a1\[27\]
mem_dout_a1\[28\]
mem_dout_a1\[29\]
mem_dout_a1\[30\]
mem_dout_a1\[31\]


mem_clk_b\[1\]    1200 0 2
mem_cen_b\[1\]
mem_addr_b1\[8\]
mem_addr_b1\[7\]
mem_addr_b1\[6\]
mem_addr_b1\[5\]
mem_addr_b1\[4\]
mem_addr_b1\[3\]
mem_addr_b1\[2\]
mem_addr_b1\[1\]
mem_addr_b1\[0\]


#N
mem_clk_a\[2\]       250 0 2
mem_cen_a\[2\]
mem_web_a\[2\]
mem_addr_a2\[0\]
mem_addr_a2\[1\]
mem_addr_a2\[2\]
mem_addr_a2\[3\]
mem_addr_a2\[4\]
mem_addr_a2\[5\]
mem_addr_a2\[6\]
mem_addr_a2\[7\]
mem_addr_a2\[8\]
mem_mask_a2\[0\]
mem_mask_a2\[1\]
mem_mask_a2\[2\]
mem_mask_a2\[3\]
mem_din_a2\[0\]
mem_din_a2\[1\]
mem_din_a2\[2\]
mem_din_a2\[3\]
mem_din_a2\[4\]
mem_din_a2\[5\]
mem_din_a2\[6\]
mem_din_a2\[7\]
mem_din_a2\[8\]
mem_din_a2\[9\]
mem_din_a2\[10\]
mem_din_a2\[11\]
mem_din_a2\[12\]
mem_din_a2\[13\]
mem_din_a2\[14\]
mem_din_a2\[15\]
mem_din_a2\[16\]
mem_din_a2\[17\]
mem_din_a2\[18\]
mem_din_a2\[19\]
mem_din_a2\[20\]
mem_din_a2\[21\]
mem_din_a2\[22\]
mem_din_a2\[23\]
mem_din_a2\[24\]
mem_din_a2\[25\]
mem_din_a2\[26\]
mem_din_a2\[27\]
mem_din_a2\[28\]
mem_din_a2\[29\]
mem_din_a2\[30\]
mem_din_a2\[31\]


mem_dout_a2\[0\]  0350 0 2
mem_dout_a2\[1\]
mem_dout_a2\[2\]
mem_dout_a2\[3\]
mem_dout_a2\[4\]
mem_dout_a2\[5\]
mem_dout_a2\[6\]
mem_dout_a2\[7\]
mem_dout_a2\[8\]
mem_dout_a2\[9\]
mem_dout_a2\[10\]
mem_dout_a2\[11\]
mem_dout_a2\[12\]
mem_dout_a2\[13\]
mem_dout_a2\[14\]
mem_dout_a2\[15\]
mem_dout_a2\[16\]
mem_dout_a2\[17\]
mem_dout_a2\[18\]
mem_dout_a2\[19\]
mem_dout_a2\[20\]
mem_dout_a2\[21\]
mem_dout_a2\[22\]
mem_dout_a2\[23\]
mem_dout_a2\[24\]
mem_dout_a2\[25\]
mem_dout_a2\[26\]
mem_dout_a2\[27\]
mem_dout_a2\[28\]
mem_dout_a2\[29\]
mem_dout_a2\[30\]
mem_dout_a2\[31\]


mem_clk_b\[2\]    0450 0 2
mem_cen_b\[2\]
mem_addr_b2\[8\]
mem_addr_b2\[7\]
mem_addr_b2\[6\]
mem_addr_b2\[5\]
mem_addr_b2\[4\]
mem_addr_b2\[3\]
mem_addr_b2\[2\]
mem_addr_b2\[1\]
mem_addr_b2\[0\]


mem_clk_a\[3\]       1000 0 2
mem_cen_a\[3\]
mem_web_a\[3\]
mem_addr_a3\[0\]
mem_addr_a3\[1\]
mem_addr_a3\[2\]
mem_addr_a3\[3\]
mem_addr_a3\[4\]
mem_addr_a3\[5\]
mem_addr_a3\[6\]
mem_addr_a3\[7\]
mem_addr_a3\[8\]
mem_mask_a3\[0\]
mem_mask_a3\[1\]
mem_mask_a3\[2\]
mem_mask_a3\[3\]
mem_din_a3\[0\]
mem_din_a3\[1\]
mem_din_a3\[2\]
mem_din_a3\[3\]
mem_din_a3\[4\]
mem_din_a3\[5\]
mem_din_a3\[6\]
mem_din_a3\[7\]
mem_din_a3\[8\]
mem_din_a3\[9\]
mem_din_a3\[10\]
mem_din_a3\[11\]
mem_din_a3\[12\]
mem_din_a3\[13\]
mem_din_a3\[14\]
mem_din_a3\[15\]
mem_din_a3\[16\]
mem_din_a3\[17\]
mem_din_a3\[18\]
mem_din_a3\[19\]
mem_din_a3\[20\]
mem_din_a3\[21\]
mem_din_a3\[22\]
mem_din_a3\[23\]
mem_din_a3\[24\]
mem_din_a3\[25\]
mem_din_a3\[26\]
mem_din_a3\[27\]
mem_din_a3\[28\]
mem_din_a3\[29\]
mem_din_a3\[30\]
mem_din_a3\[31\]


mem_dout_a3\[0\]  1100 0 2
mem_dout_a3\[1\]
mem_dout_a3\[2\]
mem_dout_a3\[3\]
mem_dout_a3\[4\]
mem_dout_a3\[5\]
mem_dout_a3\[6\]
mem_dout_a3\[7\]
mem_dout_a3\[8\]
mem_dout_a3\[9\]
mem_dout_a3\[10\]
mem_dout_a3\[11\]
mem_dout_a3\[12\]
mem_dout_a3\[13\]
mem_dout_a3\[14\]
mem_dout_a3\[15\]
mem_dout_a3\[16\]
mem_dout_a3\[17\]
mem_dout_a3\[18\]
mem_dout_a3\[19\]
mem_dout_a3\[20\]
mem_dout_a3\[21\]
mem_dout_a3\[22\]
mem_dout_a3\[23\]
mem_dout_a3\[24\]
mem_dout_a3\[25\]
mem_dout_a3\[26\]
mem_dout_a3\[27\]
mem_dout_a3\[28\]
mem_dout_a3\[29\]
mem_dout_a3\[30\]
mem_dout_a3\[31\]


mem_clk_b\[3\]    1200 0 2
mem_cen_b\[3\]
mem_addr_b3\[8\]
mem_addr_b3\[7\]
mem_addr_b3\[6\]
mem_addr_b3\[5\]
mem_addr_b3\[4\]
mem_addr_b3\[3\]
mem_addr_b3\[2\]
mem_addr_b3\[1\]
mem_addr_b3\[0\]