| ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY |
| 0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,flow completed,0h39m31s0ms,0h29m40s0ms,37826.38888888888,0.5760000000000001,18913.19444444444,16.95,1333.09,10894,0,0,0,0,0,0,0,-1,0,-1,-1,1010027,91907,-1.53,-3.35,-1,-3.07,-3.34,-106.67,-240.35,-1,-319.27,-324.23,794830726.0,0.0,23.63,45.8,2.76,26.56,-1,3846,12864,637,9652,0,0,0,5341,269,12,304,131,626,98,13,1402,1753,1688,16,1306,7532,0,8838,74.96251874062969,13.34,10,AREA 0,2,50,1,153.6,153.18,0.2,0,sky130_fd_sc_hd,10,4 |
