| ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY |
| 0,/project/openlane/ycr_core_top,ycr_core_top,ycr_core_top,flow completed,0h38m44s0ms,0h30m58s0ms,77563.90977443609,0.532,38781.954887218046,38.87,2393.08,20632,0,0,0,0,0,0,0,168,0,0,-1,1282144,186082,0.0,-8.35,-1,-1.37,-1.36,0.0,-7560.07,-1,-14.97,-15.06,1013951041.0,0.0,49.79,73.32,29.81,58.9,-1,16396,22729,542,6775,0,0,0,19178,557,261,518,596,2917,897,259,4835,2528,2435,36,682,7203,0,7885,88.02816901408451,11.36,10,AREA 0,4,50,1,153.6,153.18,0.4,0.3,sky130_fd_sc_hd,4,3 |
