| ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY |
| 0,/project/openlane/qspim,qspim_top,qspim,flow completed,0h12m4s0ms,0h8m46s0ms,65664.64646464646,0.2475,32832.32323232323,37.94,1000.87,8126,0,0,0,0,0,0,0,-1,0,-1,-1,392720,69830,-0.58,-5.13,-1,0.0,0.0,-34.73,-2037.41,-1,0.0,0.0,257576668.0,0.0,48.93,48.14,17.63,18.71,-1,7367,11031,803,4466,0,0,0,8341,263,96,194,115,1413,214,34,1460,1553,1517,18,388,3234,0,3622,100.0,10.0,10,AREA 0,4,50,1,100,100,0.42,0.3,sky130_fd_sc_hd,4,4 |
