blob: e168c5f1e757f4d6faaafa85f11b5bff7509d489 [file] [log] [blame]
#BUS_SORT
#MANUAL_PLACE
#E
soft_irq 0500 0 2
irq_lines\[15\]
irq_lines\[14\]
irq_lines\[13\]
irq_lines\[12\]
irq_lines\[11\]
irq_lines\[10\]
irq_lines\[9\]
irq_lines\[8\]
irq_lines\[7\]
irq_lines\[6\]
irq_lines\[5\]
irq_lines\[4\]
irq_lines\[3\]
irq_lines\[2\]
irq_lines\[1\]
irq_lines\[0\]
fuse_mhartid\[31\]
fuse_mhartid\[30\]
fuse_mhartid\[29\]
fuse_mhartid\[28\]
fuse_mhartid\[27\]
fuse_mhartid\[26\]
fuse_mhartid\[25\]
fuse_mhartid\[24\]
fuse_mhartid\[23\]
fuse_mhartid\[22\]
fuse_mhartid\[21\]
fuse_mhartid\[20\]
fuse_mhartid\[19\]
fuse_mhartid\[18\]
fuse_mhartid\[17\]
fuse_mhartid\[16\]
fuse_mhartid\[15\]
fuse_mhartid\[14\]
fuse_mhartid\[13\]
fuse_mhartid\[12\]
fuse_mhartid\[11\]
fuse_mhartid\[10\]
fuse_mhartid\[9\]
fuse_mhartid\[8\]
fuse_mhartid\[7\]
fuse_mhartid\[6\]
fuse_mhartid\[5\]
fuse_mhartid\[4\]
fuse_mhartid\[3\]
fuse_mhartid\[2\]
fuse_mhartid\[1\]
fuse_mhartid\[0\]
cfg_cska_riscv\[3\]
cfg_cska_riscv\[2\]
cfg_cska_riscv\[1\]
cfg_cska_riscv\[0\]
wbd_clk_int
wbd_clk_riscv
wb_clk
wbd_dmem_stb_o 0700 0
wbd_dmem_we_o
wbd_dmem_adr_o\[31\]
wbd_dmem_adr_o\[30\]
wbd_dmem_adr_o\[29\]
wbd_dmem_adr_o\[28\]
wbd_dmem_adr_o\[27\]
wbd_dmem_adr_o\[26\]
wbd_dmem_adr_o\[25\]
wbd_dmem_adr_o\[24\]
wbd_dmem_adr_o\[23\]
wbd_dmem_adr_o\[22\]
wbd_dmem_adr_o\[21\]
wbd_dmem_adr_o\[20\]
wbd_dmem_adr_o\[19\]
wbd_dmem_adr_o\[18\]
wbd_dmem_adr_o\[17\]
wbd_dmem_adr_o\[16\]
wbd_dmem_adr_o\[15\]
wbd_dmem_adr_o\[14\]
wbd_dmem_adr_o\[13\]
wbd_dmem_adr_o\[12\]
wbd_dmem_adr_o\[11\]
wbd_dmem_adr_o\[10\]
wbd_dmem_adr_o\[9\]
wbd_dmem_adr_o\[8\]
wbd_dmem_adr_o\[7\]
wbd_dmem_adr_o\[6\]
wbd_dmem_adr_o\[5\]
wbd_dmem_adr_o\[4\]
wbd_dmem_adr_o\[3\]
wbd_dmem_adr_o\[2\]
wbd_dmem_adr_o\[1\]
wbd_dmem_adr_o\[0\]
wbd_dmem_sel_o\[3\]
wbd_dmem_sel_o\[2\]
wbd_dmem_sel_o\[1\]
wbd_dmem_sel_o\[0\]
wbd_dmem_dat_o\[31\]
wbd_dmem_dat_o\[30\]
wbd_dmem_dat_o\[29\]
wbd_dmem_dat_o\[28\]
wbd_dmem_dat_o\[27\]
wbd_dmem_dat_o\[26\]
wbd_dmem_dat_o\[25\]
wbd_dmem_dat_o\[24\]
wbd_dmem_dat_o\[23\]
wbd_dmem_dat_o\[22\]
wbd_dmem_dat_o\[21\]
wbd_dmem_dat_o\[20\]
wbd_dmem_dat_o\[19\]
wbd_dmem_dat_o\[18\]
wbd_dmem_dat_o\[17\]
wbd_dmem_dat_o\[16\]
wbd_dmem_dat_o\[15\]
wbd_dmem_dat_o\[14\]
wbd_dmem_dat_o\[13\]
wbd_dmem_dat_o\[12\]
wbd_dmem_dat_o\[11\]
wbd_dmem_dat_o\[10\]
wbd_dmem_dat_o\[9\]
wbd_dmem_dat_o\[8\]
wbd_dmem_dat_o\[7\]
wbd_dmem_dat_o\[6\]
wbd_dmem_dat_o\[5\]
wbd_dmem_dat_o\[4\]
wbd_dmem_dat_o\[3\]
wbd_dmem_dat_o\[2\]
wbd_dmem_dat_o\[1\]
wbd_dmem_dat_o\[0\]
wbd_dmem_dat_i\[31\]
wbd_dmem_dat_i\[30\]
wbd_dmem_dat_i\[29\]
wbd_dmem_dat_i\[28\]
wbd_dmem_dat_i\[27\]
wbd_dmem_dat_i\[26\]
wbd_dmem_dat_i\[25\]
wbd_dmem_dat_i\[24\]
wbd_dmem_dat_i\[23\]
wbd_dmem_dat_i\[22\]
wbd_dmem_dat_i\[21\]
wbd_dmem_dat_i\[20\]
wbd_dmem_dat_i\[19\]
wbd_dmem_dat_i\[18\]
wbd_dmem_dat_i\[17\]
wbd_dmem_dat_i\[16\]
wbd_dmem_dat_i\[15\]
wbd_dmem_dat_i\[14\]
wbd_dmem_dat_i\[13\]
wbd_dmem_dat_i\[12\]
wbd_dmem_dat_i\[11\]
wbd_dmem_dat_i\[10\]
wbd_dmem_dat_i\[9\]
wbd_dmem_dat_i\[8\]
wbd_dmem_dat_i\[7\]
wbd_dmem_dat_i\[6\]
wbd_dmem_dat_i\[5\]
wbd_dmem_dat_i\[4\]
wbd_dmem_dat_i\[3\]
wbd_dmem_dat_i\[2\]
wbd_dmem_dat_i\[1\]
wbd_dmem_dat_i\[0\]
wbd_dmem_ack_i
wbd_dmem_err_i
wb_dcache_stb_o 0900 0 2
wb_dcache_we_o
wb_dcache_adr_o\[31\]
wb_dcache_adr_o\[30\]
wb_dcache_adr_o\[29\]
wb_dcache_adr_o\[28\]
wb_dcache_adr_o\[27\]
wb_dcache_adr_o\[26\]
wb_dcache_adr_o\[25\]
wb_dcache_adr_o\[24\]
wb_dcache_adr_o\[23\]
wb_dcache_adr_o\[22\]
wb_dcache_adr_o\[21\]
wb_dcache_adr_o\[20\]
wb_dcache_adr_o\[19\]
wb_dcache_adr_o\[18\]
wb_dcache_adr_o\[17\]
wb_dcache_adr_o\[16\]
wb_dcache_adr_o\[15\]
wb_dcache_adr_o\[14\]
wb_dcache_adr_o\[13\]
wb_dcache_adr_o\[12\]
wb_dcache_adr_o\[11\]
wb_dcache_adr_o\[10\]
wb_dcache_adr_o\[9\]
wb_dcache_adr_o\[8\]
wb_dcache_adr_o\[7\]
wb_dcache_adr_o\[6\]
wb_dcache_adr_o\[5\]
wb_dcache_adr_o\[4\]
wb_dcache_adr_o\[3\]
wb_dcache_adr_o\[2\]
wb_dcache_adr_o\[1\]
wb_dcache_adr_o\[0\]
wb_dcache_sel_o\[3\]
wb_dcache_sel_o\[2\]
wb_dcache_sel_o\[1\]
wb_dcache_sel_o\[0\]
wb_dcache_bl_o\[9\]
wb_dcache_bl_o\[8\]
wb_dcache_bl_o\[7\]
wb_dcache_bl_o\[6\]
wb_dcache_bl_o\[5\]
wb_dcache_bl_o\[4\]
wb_dcache_bl_o\[3\]
wb_dcache_bl_o\[2\]
wb_dcache_bl_o\[1\]
wb_dcache_bl_o\[0\]
wb_dcache_bry_o
wb_dcache_dat_o\[31\]
wb_dcache_dat_o\[30\]
wb_dcache_dat_o\[29\]
wb_dcache_dat_o\[28\]
wb_dcache_dat_o\[27\]
wb_dcache_dat_o\[26\]
wb_dcache_dat_o\[25\]
wb_dcache_dat_o\[24\]
wb_dcache_dat_o\[23\]
wb_dcache_dat_o\[22\]
wb_dcache_dat_o\[21\]
wb_dcache_dat_o\[20\]
wb_dcache_dat_o\[19\]
wb_dcache_dat_o\[18\]
wb_dcache_dat_o\[17\]
wb_dcache_dat_o\[16\]
wb_dcache_dat_o\[15\]
wb_dcache_dat_o\[14\]
wb_dcache_dat_o\[13\]
wb_dcache_dat_o\[12\]
wb_dcache_dat_o\[11\]
wb_dcache_dat_o\[10\]
wb_dcache_dat_o\[9\]
wb_dcache_dat_o\[8\]
wb_dcache_dat_o\[7\]
wb_dcache_dat_o\[6\]
wb_dcache_dat_o\[5\]
wb_dcache_dat_o\[4\]
wb_dcache_dat_o\[3\]
wb_dcache_dat_o\[2\]
wb_dcache_dat_o\[1\]
wb_dcache_dat_o\[0\]
wb_dcache_dat_i\[31\]
wb_dcache_dat_i\[30\]
wb_dcache_dat_i\[29\]
wb_dcache_dat_i\[28\]
wb_dcache_dat_i\[27\]
wb_dcache_dat_i\[26\]
wb_dcache_dat_i\[25\]
wb_dcache_dat_i\[24\]
wb_dcache_dat_i\[23\]
wb_dcache_dat_i\[22\]
wb_dcache_dat_i\[21\]
wb_dcache_dat_i\[20\]
wb_dcache_dat_i\[19\]
wb_dcache_dat_i\[18\]
wb_dcache_dat_i\[17\]
wb_dcache_dat_i\[16\]
wb_dcache_dat_i\[15\]
wb_dcache_dat_i\[14\]
wb_dcache_dat_i\[13\]
wb_dcache_dat_i\[12\]
wb_dcache_dat_i\[11\]
wb_dcache_dat_i\[10\]
wb_dcache_dat_i\[9\]
wb_dcache_dat_i\[8\]
wb_dcache_dat_i\[7\]
wb_dcache_dat_i\[6\]
wb_dcache_dat_i\[5\]
wb_dcache_dat_i\[4\]
wb_dcache_dat_i\[3\]
wb_dcache_dat_i\[2\]
wb_dcache_dat_i\[1\]
wb_dcache_dat_i\[0\]
wb_dcache_ack_i
wb_dcache_lack_i
wb_dcache_err_i
wb_icache_stb_o 1100 0 2
wb_icache_we_o
wb_icache_adr_o\[31\]
wb_icache_adr_o\[30\]
wb_icache_adr_o\[29\]
wb_icache_adr_o\[28\]
wb_icache_adr_o\[27\]
wb_icache_adr_o\[26\]
wb_icache_adr_o\[25\]
wb_icache_adr_o\[24\]
wb_icache_adr_o\[23\]
wb_icache_adr_o\[22\]
wb_icache_adr_o\[21\]
wb_icache_adr_o\[20\]
wb_icache_adr_o\[19\]
wb_icache_adr_o\[18\]
wb_icache_adr_o\[17\]
wb_icache_adr_o\[16\]
wb_icache_adr_o\[15\]
wb_icache_adr_o\[14\]
wb_icache_adr_o\[13\]
wb_icache_adr_o\[12\]
wb_icache_adr_o\[11\]
wb_icache_adr_o\[10\]
wb_icache_adr_o\[9\]
wb_icache_adr_o\[8\]
wb_icache_adr_o\[7\]
wb_icache_adr_o\[6\]
wb_icache_adr_o\[5\]
wb_icache_adr_o\[4\]
wb_icache_adr_o\[3\]
wb_icache_adr_o\[2\]
wb_icache_adr_o\[1\]
wb_icache_adr_o\[0\]
wb_icache_sel_o\[3\]
wb_icache_sel_o\[2\]
wb_icache_sel_o\[1\]
wb_icache_sel_o\[0\]
wb_icache_bl_o\[9\]
wb_icache_bl_o\[8\]
wb_icache_bl_o\[7\]
wb_icache_bl_o\[6\]
wb_icache_bl_o\[5\]
wb_icache_bl_o\[4\]
wb_icache_bl_o\[3\]
wb_icache_bl_o\[2\]
wb_icache_bl_o\[1\]
wb_icache_bl_o\[0\]
wb_icache_bry_o
wb_icache_dat_i\[31\]
wb_icache_dat_i\[30\]
wb_icache_dat_i\[29\]
wb_icache_dat_i\[28\]
wb_icache_dat_i\[27\]
wb_icache_dat_i\[26\]
wb_icache_dat_i\[25\]
wb_icache_dat_i\[24\]
wb_icache_dat_i\[23\]
wb_icache_dat_i\[22\]
wb_icache_dat_i\[21\]
wb_icache_dat_i\[20\]
wb_icache_dat_i\[19\]
wb_icache_dat_i\[18\]
wb_icache_dat_i\[17\]
wb_icache_dat_i\[16\]
wb_icache_dat_i\[15\]
wb_icache_dat_i\[14\]
wb_icache_dat_i\[13\]
wb_icache_dat_i\[12\]
wb_icache_dat_i\[11\]
wb_icache_dat_i\[10\]
wb_icache_dat_i\[9\]
wb_icache_dat_i\[8\]
wb_icache_dat_i\[7\]
wb_icache_dat_i\[6\]
wb_icache_dat_i\[5\]
wb_icache_dat_i\[4\]
wb_icache_dat_i\[3\]
wb_icache_dat_i\[2\]
wb_icache_dat_i\[1\]
wb_icache_dat_i\[0\]
wb_icache_ack_i
wb_icache_lack_i
wb_icache_err_i
#W
sram0_clk1 0000 0 2
sram0_csb1
sram0_addr1\[8\]
sram0_addr1\[7\]
sram0_addr1\[6\]
sram0_addr1\[5\]
sram0_addr1\[4\]
sram0_addr1\[3\]
sram0_addr1\[2\]
sram0_addr1\[1\]
sram0_addr1\[0\]
sram0_dout1\[0\] 0200 0 2
sram0_dout1\[1\]
sram0_dout1\[2\]
sram0_dout1\[3\]
sram0_dout1\[4\]
sram0_dout1\[5\]
sram0_dout1\[6\]
sram0_dout1\[7\]
sram0_dout1\[8\]
sram0_dout1\[9\]
sram0_dout1\[10\]
sram0_dout1\[11\]
sram0_dout1\[12\]
sram0_dout1\[13\]
sram0_dout1\[14\]
sram0_dout1\[15\]
sram0_dout1\[16\]
sram0_dout1\[17\]
sram0_dout1\[18\]
sram0_dout1\[19\]
sram0_dout1\[20\]
sram0_dout1\[21\]
sram0_dout1\[22\]
sram0_dout1\[23\]
sram0_dout1\[24\]
sram0_dout1\[25\]
sram0_dout1\[26\]
sram0_dout1\[27\]
sram0_dout1\[28\]
sram0_dout1\[29\]
sram0_dout1\[30\]
sram0_dout1\[31\]
icache_mem_clk0 300 0 2
icache_mem_csb0
icache_mem_web0
icache_mem_addr0\[0\]
icache_mem_addr0\[1\]
icache_mem_addr0\[2\]
icache_mem_addr0\[3\]
icache_mem_addr0\[4\]
icache_mem_addr0\[5\]
icache_mem_addr0\[6\]
icache_mem_addr0\[7\]
icache_mem_addr0\[8\]
icache_mem_wmask0\[0\]
icache_mem_wmask0\[1\]
icache_mem_wmask0\[2\]
icache_mem_wmask0\[3\]
icache_mem_din0\[0\]
icache_mem_din0\[1\]
icache_mem_din0\[2\]
icache_mem_din0\[3\]
icache_mem_din0\[4\]
icache_mem_din0\[5\]
icache_mem_din0\[6\]
icache_mem_din0\[7\]
icache_mem_din0\[8\]
icache_mem_din0\[9\]
icache_mem_din0\[10\]
icache_mem_din0\[11\]
icache_mem_din0\[12\]
icache_mem_din0\[13\]
icache_mem_din0\[14\]
icache_mem_din0\[15\]
icache_mem_din0\[16\]
icache_mem_din0\[17\]
icache_mem_din0\[18\]
icache_mem_din0\[19\]
icache_mem_din0\[20\]
icache_mem_din0\[21\]
icache_mem_din0\[22\]
icache_mem_din0\[23\]
icache_mem_din0\[24\]
icache_mem_din0\[25\]
icache_mem_din0\[26\]
icache_mem_din0\[27\]
icache_mem_din0\[28\]
icache_mem_din0\[29\]
icache_mem_din0\[30\]
icache_mem_din0\[31\]
icache_mem_clk1 0400 0 2
icache_mem_csb1
icache_mem_addr1\[8\]
icache_mem_addr1\[7\]
icache_mem_addr1\[6\]
icache_mem_addr1\[5\]
icache_mem_addr1\[4\]
icache_mem_addr1\[3\]
icache_mem_addr1\[2\]
icache_mem_addr1\[1\]
icache_mem_addr1\[0\]
icache_mem_dout1\[0\] 0450 0 2
icache_mem_dout1\[1\]
icache_mem_dout1\[2\]
icache_mem_dout1\[3\]
icache_mem_dout1\[4\]
icache_mem_dout1\[5\]
icache_mem_dout1\[6\]
icache_mem_dout1\[7\]
icache_mem_dout1\[8\]
icache_mem_dout1\[9\]
icache_mem_dout1\[10\]
icache_mem_dout1\[11\]
icache_mem_dout1\[12\]
icache_mem_dout1\[13\]
icache_mem_dout1\[14\]
icache_mem_dout1\[15\]
icache_mem_dout1\[16\]
icache_mem_dout1\[17\]
icache_mem_dout1\[18\]
icache_mem_dout1\[19\]
icache_mem_dout1\[20\]
icache_mem_dout1\[21\]
icache_mem_dout1\[22\]
icache_mem_dout1\[23\]
icache_mem_dout1\[24\]
icache_mem_dout1\[25\]
icache_mem_dout1\[26\]
icache_mem_dout1\[27\]
icache_mem_dout1\[28\]
icache_mem_dout1\[29\]
icache_mem_dout1\[30\]
icache_mem_dout1\[31\]
dcache_mem_clk0 850 0 2
dcache_mem_csb0
dcache_mem_web0
dcache_mem_addr0\[0\]
dcache_mem_addr0\[1\]
dcache_mem_addr0\[2\]
dcache_mem_addr0\[3\]
dcache_mem_addr0\[4\]
dcache_mem_addr0\[5\]
dcache_mem_addr0\[6\]
dcache_mem_addr0\[7\]
dcache_mem_addr0\[8\]
dcache_mem_wmask0\[0\]
dcache_mem_wmask0\[1\]
dcache_mem_wmask0\[2\]
dcache_mem_wmask0\[3\]
dcache_mem_din0\[0\]
dcache_mem_din0\[1\]
dcache_mem_din0\[2\]
dcache_mem_din0\[3\]
dcache_mem_din0\[4\]
dcache_mem_din0\[5\]
dcache_mem_din0\[6\]
dcache_mem_din0\[7\]
dcache_mem_din0\[8\]
dcache_mem_din0\[9\]
dcache_mem_din0\[10\]
dcache_mem_din0\[11\]
dcache_mem_din0\[12\]
dcache_mem_din0\[13\]
dcache_mem_din0\[14\]
dcache_mem_din0\[15\]
dcache_mem_din0\[16\]
dcache_mem_din0\[17\]
dcache_mem_din0\[18\]
dcache_mem_din0\[19\]
dcache_mem_din0\[20\]
dcache_mem_din0\[21\]
dcache_mem_din0\[22\]
dcache_mem_din0\[23\]
dcache_mem_din0\[24\]
dcache_mem_din0\[25\]
dcache_mem_din0\[26\]
dcache_mem_din0\[27\]
dcache_mem_din0\[28\]
dcache_mem_din0\[29\]
dcache_mem_din0\[30\]
dcache_mem_din0\[31\]
dcache_mem_dout0\[0\] 950 0 2
dcache_mem_dout0\[1\]
dcache_mem_dout0\[2\]
dcache_mem_dout0\[3\]
dcache_mem_dout0\[4\]
dcache_mem_dout0\[5\]
dcache_mem_dout0\[6\]
dcache_mem_dout0\[7\]
dcache_mem_dout0\[8\]
dcache_mem_dout0\[9\]
dcache_mem_dout0\[10\]
dcache_mem_dout0\[11\]
dcache_mem_dout0\[12\]
dcache_mem_dout0\[13\]
dcache_mem_dout0\[14\]
dcache_mem_dout0\[15\]
dcache_mem_dout0\[16\]
dcache_mem_dout0\[17\]
dcache_mem_dout0\[18\]
dcache_mem_dout0\[19\]
dcache_mem_dout0\[20\]
dcache_mem_dout0\[21\]
dcache_mem_dout0\[22\]
dcache_mem_dout0\[23\]
dcache_mem_dout0\[24\]
dcache_mem_dout0\[25\]
dcache_mem_dout0\[26\]
dcache_mem_dout0\[27\]
dcache_mem_dout0\[28\]
dcache_mem_dout0\[29\]
dcache_mem_dout0\[30\]
dcache_mem_dout0\[31\]
dcache_mem_clk1 1000 0 2
dcache_mem_csb1
dcache_mem_addr1\[8\]
dcache_mem_addr1\[7\]
dcache_mem_addr1\[6\]
dcache_mem_addr1\[5\]
dcache_mem_addr1\[4\]
dcache_mem_addr1\[3\]
dcache_mem_addr1\[2\]
dcache_mem_addr1\[1\]
dcache_mem_addr1\[0\]
dcache_mem_dout1\[0\] 1050 0 2
dcache_mem_dout1\[1\]
dcache_mem_dout1\[2\]
dcache_mem_dout1\[3\]
dcache_mem_dout1\[4\]
dcache_mem_dout1\[5\]
dcache_mem_dout1\[6\]
dcache_mem_dout1\[7\]
dcache_mem_dout1\[8\]
dcache_mem_dout1\[9\]
dcache_mem_dout1\[10\]
dcache_mem_dout1\[11\]
dcache_mem_dout1\[12\]
dcache_mem_dout1\[13\]
dcache_mem_dout1\[14\]
dcache_mem_dout1\[15\]
dcache_mem_dout1\[16\]
dcache_mem_dout1\[17\]
dcache_mem_dout1\[18\]
dcache_mem_dout1\[19\]
dcache_mem_dout1\[20\]
dcache_mem_dout1\[21\]
dcache_mem_dout1\[22\]
dcache_mem_dout1\[23\]
dcache_mem_dout1\[24\]
dcache_mem_dout1\[25\]
dcache_mem_dout1\[26\]
dcache_mem_dout1\[27\]
dcache_mem_dout1\[28\]
dcache_mem_dout1\[29\]
dcache_mem_dout1\[30\]
dcache_mem_dout1\[31\]
#S
sram0_clk0 0 0 2
sram0_csb0
sram0_web0
sram0_addr0\[0\]
sram0_addr0\[1\]
sram0_addr0\[2\]
sram0_addr0\[3\]
sram0_addr0\[4\]
sram0_addr0\[5\]
sram0_addr0\[6\]
sram0_addr0\[7\]
sram0_addr0\[8\]
sram0_wmask0\[0\]
sram0_wmask0\[1\]
sram0_wmask0\[2\]
sram0_wmask0\[3\]
sram0_din0\[0\]
sram0_din0\[1\]
sram0_din0\[2\]
sram0_din0\[3\]
sram0_din0\[4\]
sram0_din0\[5\]
sram0_din0\[6\]
sram0_din0\[7\]
sram0_din0\[8\]
sram0_din0\[9\]
sram0_din0\[10\]
sram0_din0\[11\]
sram0_din0\[12\]
sram0_din0\[13\]
sram0_din0\[14\]
sram0_din0\[15\]
sram0_din0\[16\]
sram0_din0\[17\]
sram0_din0\[18\]
sram0_din0\[19\]
sram0_din0\[20\]
sram0_din0\[21\]
sram0_din0\[22\]
sram0_din0\[23\]
sram0_din0\[24\]
sram0_din0\[25\]
sram0_din0\[26\]
sram0_din0\[27\]
sram0_din0\[28\]
sram0_din0\[29\]
sram0_din0\[30\]
sram0_din0\[31\]
sram0_dout0\[0\] 0100 0 2
sram0_dout0\[1\]
sram0_dout0\[2\]
sram0_dout0\[3\]
sram0_dout0\[4\]
sram0_dout0\[5\]
sram0_dout0\[6\]
sram0_dout0\[7\]
sram0_dout0\[8\]
sram0_dout0\[9\]
sram0_dout0\[10\]
sram0_dout0\[11\]
sram0_dout0\[12\]
sram0_dout0\[13\]
sram0_dout0\[14\]
sram0_dout0\[15\]
sram0_dout0\[16\]
sram0_dout0\[17\]
sram0_dout0\[18\]
sram0_dout0\[19\]
sram0_dout0\[20\]
sram0_dout0\[21\]
sram0_dout0\[22\]
sram0_dout0\[23\]
sram0_dout0\[24\]
sram0_dout0\[25\]
sram0_dout0\[26\]
sram0_dout0\[27\]
sram0_dout0\[28\]
sram0_dout0\[29\]
sram0_dout0\[30\]
sram0_dout0\[31\]
riscv_debug\[0\] 300 0 2
riscv_debug\[1\]
riscv_debug\[2\]
riscv_debug\[3\]
riscv_debug\[4\]
riscv_debug\[5\]
riscv_debug\[6\]
riscv_debug\[7\]
riscv_debug\[8\]
riscv_debug\[9\]
riscv_debug\[10\]
riscv_debug\[11\]
riscv_debug\[12\]
riscv_debug\[13\]
riscv_debug\[14\]
riscv_debug\[15\]
riscv_debug\[16\]
riscv_debug\[17\]
riscv_debug\[18\]
riscv_debug\[19\]
riscv_debug\[20\]
riscv_debug\[21\]
riscv_debug\[22\]
riscv_debug\[23\]
riscv_debug\[24\]
riscv_debug\[25\]
riscv_debug\[26\]
riscv_debug\[27\]
riscv_debug\[28\]
riscv_debug\[29\]
riscv_debug\[30\]
riscv_debug\[31\]
riscv_debug\[32\]
riscv_debug\[33\]
riscv_debug\[34\]
riscv_debug\[35\]
riscv_debug\[36\]
riscv_debug\[37\]
riscv_debug\[38\]
riscv_debug\[39\]
riscv_debug\[40\]
riscv_debug\[41\]
riscv_debug\[42\]
riscv_debug\[43\]
riscv_debug\[44\]
riscv_debug\[45\]
riscv_debug\[46\]
riscv_debug\[47\]
riscv_debug\[48\]
riscv_debug\[49\]
riscv_debug\[50\]
riscv_debug\[51\]
riscv_debug\[52\]
riscv_debug\[53\]
riscv_debug\[54\]
riscv_debug\[55\]
riscv_debug\[56\]
riscv_debug\[57\]
riscv_debug\[58\]
riscv_debug\[59\]
riscv_debug\[60\]
riscv_debug\[61\]
riscv_debug\[62\]
riscv_debug\[63\]
wb_rst_n 500 0 2
pwrup_rst_n
rst_n
core_clk
rtc_clk
cpu_rst_n