diff --git a/caravel b/caravel
index 793bf63..e7ade82 160000
--- a/caravel
+++ b/caravel
@@ -1 +1 @@
-Subproject commit 793bf634c2c1b1af90be95fcd85688e869bfb667
+Subproject commit e7ade8203d82c5604c7542d161765090838e5e7f
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile
index e14258d..be842fc 100644
--- a/verilog/dv/Makefile
+++ b/verilog/dv/Makefile
@@ -28,10 +28,9 @@
 
 all:  ${PATTERNS}
 
-	echo "bla"
-	# for i in ${PATTERNS}; do \
-	# 	( cd $$i && make -f Makefile $${i}.vcd &> verify.log && grep Monitor verify.log) ; \
-	# done
+	for i in ${PATTERNS}; do \
+		( cd $$i && make -f Makefile $${i}.vcd &> verify.log && grep Monitor verify.log) ; \
+	done
 
 DV_PATTERNS = $(foreach dv, $(PATTERNS), verify-$(dv))
 $(DV_PATTERNS): verify-% : 
diff --git a/verilog/dv/io_ports/RTL-io_ports.vcd b/verilog/dv/io_ports/RTL-io_ports.vcd
deleted file mode 100644
index a85a5ed..0000000
--- a/verilog/dv/io_ports/RTL-io_ports.vcd
+++ /dev/null
Binary files differ
diff --git a/verilog/dv/io_ports/io_ports.hex b/verilog/dv/io_ports/io_ports.hex
deleted file mode 100755
index 2515ebb..0000000
--- a/verilog/dv/io_ports/io_ports.hex
+++ /dev/null
@@ -1,59 +0,0 @@
-@00000000
-6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 
-13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 
-23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE 
-23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE 
-23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD 
-23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD 
-13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 
-03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 
-03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 
-03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 
-03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 
-17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 
-73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00 
-13 06 C6 2C 63 0C B5 00 83 26 06 00 23 20 D5 00 
-13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 
-93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 
-6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 
-EF 00 C0 1A 6F 00 00 00 13 01 01 FF 23 26 81 00 
-13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 
-67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 
-13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 
-13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE 
-83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 
-13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 
-23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC 
-B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 
-B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 
-13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 
-03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF 
-23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 
-13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 
-13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 
-67 80 00 00 13 01 01 FE 23 2E 11 00 23 2C 81 00 
-13 04 01 02 93 07 05 00 A3 07 F4 FE 03 47 F4 FE 
-93 07 A0 00 63 16 F7 00 13 05 D0 00 EF F0 9F FD 
-13 00 00 00 B7 67 00 F0 93 87 47 80 03 A7 07 00 
-93 07 10 00 E3 08 F7 FE B7 67 00 F0 93 87 07 80 
-03 47 F4 FE 23 A0 E7 00 13 00 00 00 83 20 C1 01 
-03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FE 
-23 2E 11 00 23 2C 81 00 13 04 01 02 23 26 A4 FE 
-6F 00 C0 01 83 27 C4 FE 13 87 17 00 23 26 E4 FE 
-83 C7 07 00 13 85 07 00 EF F0 DF F6 83 27 C4 FE 
-83 C7 07 00 E3 90 07 FE 13 00 00 00 83 20 C1 01 
-03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FF 
-23 26 81 00 13 04 01 01 B7 07 00 26 93 87 47 02 
-37 27 00 00 13 07 87 80 23 A0 E7 00 B7 07 00 26 
-93 87 87 02 37 27 00 00 13 07 87 80 23 A0 E7 00 
-B7 07 00 26 93 87 C7 02 37 27 00 00 13 07 87 80 
-23 A0 E7 00 B7 07 00 26 93 87 07 03 37 27 00 00 
-13 07 87 80 23 A0 E7 00 B7 07 00 26 93 87 47 03 
-37 27 00 00 13 07 87 80 23 A0 E7 00 B7 07 00 26 
-93 87 87 03 37 27 00 00 13 07 87 80 23 A0 E7 00 
-B7 07 00 26 93 87 C7 03 37 27 00 00 13 07 87 80 
-23 A0 E7 00 B7 07 00 26 93 87 07 04 37 27 00 00 
-13 07 87 80 23 A0 E7 00 B7 07 00 26 13 07 10 00 
-23 A0 E7 00 13 00 00 00 B7 07 00 26 03 A7 07 00 
-93 07 10 00 E3 0A F7 FE 13 00 00 00 03 24 C1 00 
-13 01 01 01 67 80 00 00 
diff --git a/verilog/dv/io_ports/io_ports.hexe b/verilog/dv/io_ports/io_ports.hexe
deleted file mode 100755
index 66f6660..0000000
--- a/verilog/dv/io_ports/io_ports.hexe
+++ /dev/null
@@ -1,59 +0,0 @@
-@10000000
-6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 
-13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 
-23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE 
-23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE 
-23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD 
-23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD 
-13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 
-03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 
-03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 
-03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 
-03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 
-17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 
-73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00 
-13 06 C6 2C 63 0C B5 00 83 26 06 00 23 20 D5 00 
-13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 
-93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 
-6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 
-EF 00 C0 1A 6F 00 00 00 13 01 01 FF 23 26 81 00 
-13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 
-67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 
-13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 
-13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE 
-83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 
-13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 
-23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC 
-B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 
-B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 
-13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 
-03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF 
-23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 
-13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 
-13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 
-67 80 00 00 13 01 01 FE 23 2E 11 00 23 2C 81 00 
-13 04 01 02 93 07 05 00 A3 07 F4 FE 03 47 F4 FE 
-93 07 A0 00 63 16 F7 00 13 05 D0 00 EF F0 9F FD 
-13 00 00 00 B7 67 00 F0 93 87 47 80 03 A7 07 00 
-93 07 10 00 E3 08 F7 FE B7 67 00 F0 93 87 07 80 
-03 47 F4 FE 23 A0 E7 00 13 00 00 00 83 20 C1 01 
-03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FE 
-23 2E 11 00 23 2C 81 00 13 04 01 02 23 26 A4 FE 
-6F 00 C0 01 83 27 C4 FE 13 87 17 00 23 26 E4 FE 
-83 C7 07 00 13 85 07 00 EF F0 DF F6 83 27 C4 FE 
-83 C7 07 00 E3 90 07 FE 13 00 00 00 83 20 C1 01 
-03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FF 
-23 26 81 00 13 04 01 01 B7 07 00 26 93 87 47 02 
-37 27 00 00 13 07 87 80 23 A0 E7 00 B7 07 00 26 
-93 87 87 02 37 27 00 00 13 07 87 80 23 A0 E7 00 
-B7 07 00 26 93 87 C7 02 37 27 00 00 13 07 87 80 
-23 A0 E7 00 B7 07 00 26 93 87 07 03 37 27 00 00 
-13 07 87 80 23 A0 E7 00 B7 07 00 26 93 87 47 03 
-37 27 00 00 13 07 87 80 23 A0 E7 00 B7 07 00 26 
-93 87 87 03 37 27 00 00 13 07 87 80 23 A0 E7 00 
-B7 07 00 26 93 87 C7 03 37 27 00 00 13 07 87 80 
-23 A0 E7 00 B7 07 00 26 93 87 07 04 37 27 00 00 
-13 07 87 80 23 A0 E7 00 B7 07 00 26 13 07 10 00 
-23 A0 E7 00 13 00 00 00 B7 07 00 26 03 A7 07 00 
-93 07 10 00 E3 0A F7 FE 13 00 00 00 03 24 C1 00 
-13 01 01 01 67 80 00 00 
diff --git a/verilog/dv/io_ports/io_ports.lst b/verilog/dv/io_ports/io_ports.lst
deleted file mode 100644
index a7bd073..0000000
--- a/verilog/dv/io_ports/io_ports.lst
+++ /dev/null
@@ -1,271 +0,0 @@
-
-io_ports.elf:     file format elf32-littleriscv
-
-
-Disassembly of section .text:
-
-10000000 <_ftext>:
-10000000:	0b00006f          	j	100000b0 <crt_init>
-10000004:	00000013          	nop
-10000008:	00000013          	nop
-1000000c:	00000013          	nop
-10000010:	00000013          	nop
-10000014:	00000013          	nop
-10000018:	00000013          	nop
-1000001c:	00000013          	nop
-
-10000020 <trap_entry>:
-10000020:	fe112e23          	sw	ra,-4(sp)
-10000024:	fe512c23          	sw	t0,-8(sp)
-10000028:	fe612a23          	sw	t1,-12(sp)
-1000002c:	fe712823          	sw	t2,-16(sp)
-10000030:	fea12623          	sw	a0,-20(sp)
-10000034:	feb12423          	sw	a1,-24(sp)
-10000038:	fec12223          	sw	a2,-28(sp)
-1000003c:	fed12023          	sw	a3,-32(sp)
-10000040:	fce12e23          	sw	a4,-36(sp)
-10000044:	fcf12c23          	sw	a5,-40(sp)
-10000048:	fd012a23          	sw	a6,-44(sp)
-1000004c:	fd112823          	sw	a7,-48(sp)
-10000050:	fdc12623          	sw	t3,-52(sp)
-10000054:	fdd12423          	sw	t4,-56(sp)
-10000058:	fde12223          	sw	t5,-60(sp)
-1000005c:	fdf12023          	sw	t6,-64(sp)
-10000060:	fc010113          	addi	sp,sp,-64
-10000064:	114000ef          	jal	ra,10000178 <isr>
-10000068:	03c12083          	lw	ra,60(sp)
-1000006c:	03812283          	lw	t0,56(sp)
-10000070:	03412303          	lw	t1,52(sp)
-10000074:	03012383          	lw	t2,48(sp)
-10000078:	02c12503          	lw	a0,44(sp)
-1000007c:	02812583          	lw	a1,40(sp)
-10000080:	02412603          	lw	a2,36(sp)
-10000084:	02012683          	lw	a3,32(sp)
-10000088:	01c12703          	lw	a4,28(sp)
-1000008c:	01812783          	lw	a5,24(sp)
-10000090:	01412803          	lw	a6,20(sp)
-10000094:	01012883          	lw	a7,16(sp)
-10000098:	00c12e03          	lw	t3,12(sp)
-1000009c:	00812e83          	lw	t4,8(sp)
-100000a0:	00412f03          	lw	t5,4(sp)
-100000a4:	00012f83          	lw	t6,0(sp)
-100000a8:	04010113          	addi	sp,sp,64
-100000ac:	30200073          	mret
-
-100000b0 <crt_init>:
-100000b0:	f1000117          	auipc	sp,0xf1000
-100000b4:	75010113          	addi	sp,sp,1872 # 1000800 <_fstack>
-100000b8:	00000517          	auipc	a0,0x0
-100000bc:	f6850513          	addi	a0,a0,-152 # 10000020 <trap_entry>
-100000c0:	30551073          	csrw	mtvec,a0
-
-100000c4 <data_init>:
-100000c4:	00000513          	li	a0,0
-100000c8:	00000593          	li	a1,0
-100000cc:	00000617          	auipc	a2,0x0
-100000d0:	2cc60613          	addi	a2,a2,716 # 10000398 <_etext>
-
-100000d4 <data_loop>:
-100000d4:	00b50c63          	beq	a0,a1,100000ec <bss_init>
-100000d8:	00062683          	lw	a3,0(a2)
-100000dc:	00d52023          	sw	a3,0(a0)
-100000e0:	00450513          	addi	a0,a0,4
-100000e4:	00460613          	addi	a2,a2,4
-100000e8:	fedff06f          	j	100000d4 <data_loop>
-
-100000ec <bss_init>:
-100000ec:	00000513          	li	a0,0
-100000f0:	00800593          	li	a1,8
-
-100000f4 <bss_loop>:
-100000f4:	00b50863          	beq	a0,a1,10000104 <bss_done>
-100000f8:	00052023          	sw	zero,0(a0)
-100000fc:	00450513          	addi	a0,a0,4
-10000100:	ff5ff06f          	j	100000f4 <bss_loop>
-
-10000104 <bss_done>:
-10000104:	00001537          	lui	a0,0x1
-10000108:	88050513          	addi	a0,a0,-1920 # 880 <_ebss+0x878>
-1000010c:	30451073          	csrw	mie,a0
-10000110:	1ac000ef          	jal	ra,100002bc <main>
-
-10000114 <infinit_loop>:
-10000114:	0000006f          	j	10000114 <infinit_loop>
-
-10000118 <flush_cpu_icache>:
-10000118:	ff010113          	addi	sp,sp,-16
-1000011c:	00812623          	sw	s0,12(sp)
-10000120:	01010413          	addi	s0,sp,16
-10000124:	00000013          	nop
-10000128:	00c12403          	lw	s0,12(sp)
-1000012c:	01010113          	addi	sp,sp,16
-10000130:	00008067          	ret
-
-10000134 <flush_cpu_dcache>:
-10000134:	ff010113          	addi	sp,sp,-16
-10000138:	00812623          	sw	s0,12(sp)
-1000013c:	01010413          	addi	s0,sp,16
-10000140:	00000013          	nop
-10000144:	00c12403          	lw	s0,12(sp)
-10000148:	01010113          	addi	sp,sp,16
-1000014c:	00008067          	ret
-
-10000150 <irq_setmask>:
-10000150:	fe010113          	addi	sp,sp,-32
-10000154:	00812e23          	sw	s0,28(sp)
-10000158:	02010413          	addi	s0,sp,32
-1000015c:	fea42623          	sw	a0,-20(s0)
-10000160:	fec42783          	lw	a5,-20(s0)
-10000164:	bc079073          	csrw	0xbc0,a5
-10000168:	00000013          	nop
-1000016c:	01c12403          	lw	s0,28(sp)
-10000170:	02010113          	addi	sp,sp,32
-10000174:	00008067          	ret
-
-10000178 <isr>:
-10000178:	ff010113          	addi	sp,sp,-16
-1000017c:	00112623          	sw	ra,12(sp)
-10000180:	00812423          	sw	s0,8(sp)
-10000184:	01010413          	addi	s0,sp,16
-10000188:	00000513          	li	a0,0
-1000018c:	fc5ff0ef          	jal	ra,10000150 <irq_setmask>
-10000190:	f00037b7          	lui	a5,0xf0003
-10000194:	03878793          	addi	a5,a5,56 # f0003038 <_etext+0xe0002ca0>
-10000198:	00a00713          	li	a4,10
-1000019c:	00e7a023          	sw	a4,0(a5)
-100001a0:	f00037b7          	lui	a5,0xf0003
-100001a4:	03c78793          	addi	a5,a5,60 # f000303c <_etext+0xe0002ca4>
-100001a8:	00020737          	lui	a4,0x20
-100001ac:	00e7a023          	sw	a4,0(a5)
-100001b0:	00100713          	li	a4,1
-100001b4:	00e01023          	sh	a4,0(zero) # 0 <__DYNAMIC>
-100001b8:	00000013          	nop
-100001bc:	00c12083          	lw	ra,12(sp)
-100001c0:	00812403          	lw	s0,8(sp)
-100001c4:	01010113          	addi	sp,sp,16
-100001c8:	00008067          	ret
-
-100001cc <flush_cpu_icache>:
-100001cc:	ff010113          	addi	sp,sp,-16
-100001d0:	00812623          	sw	s0,12(sp)
-100001d4:	01010413          	addi	s0,sp,16
-100001d8:	00000013          	nop
-100001dc:	00c12403          	lw	s0,12(sp)
-100001e0:	01010113          	addi	sp,sp,16
-100001e4:	00008067          	ret
-
-100001e8 <flush_cpu_dcache>:
-100001e8:	ff010113          	addi	sp,sp,-16
-100001ec:	00812623          	sw	s0,12(sp)
-100001f0:	01010413          	addi	s0,sp,16
-100001f4:	00000013          	nop
-100001f8:	00c12403          	lw	s0,12(sp)
-100001fc:	01010113          	addi	sp,sp,16
-10000200:	00008067          	ret
-
-10000204 <putchar>:
-10000204:	fe010113          	addi	sp,sp,-32
-10000208:	00112e23          	sw	ra,28(sp)
-1000020c:	00812c23          	sw	s0,24(sp)
-10000210:	02010413          	addi	s0,sp,32
-10000214:	00050793          	mv	a5,a0
-10000218:	fef407a3          	sb	a5,-17(s0)
-1000021c:	fef44703          	lbu	a4,-17(s0)
-10000220:	00a00793          	li	a5,10
-10000224:	00f71663          	bne	a4,a5,10000230 <putchar+0x2c>
-10000228:	00d00513          	li	a0,13
-1000022c:	fd9ff0ef          	jal	ra,10000204 <putchar>
-10000230:	00000013          	nop
-10000234:	f00067b7          	lui	a5,0xf0006
-10000238:	80478793          	addi	a5,a5,-2044 # f0005804 <_etext+0xe000546c>
-1000023c:	0007a703          	lw	a4,0(a5)
-10000240:	00100793          	li	a5,1
-10000244:	fef708e3          	beq	a4,a5,10000234 <putchar+0x30>
-10000248:	f00067b7          	lui	a5,0xf0006
-1000024c:	80078793          	addi	a5,a5,-2048 # f0005800 <_etext+0xe0005468>
-10000250:	fef44703          	lbu	a4,-17(s0)
-10000254:	00e7a023          	sw	a4,0(a5)
-10000258:	00000013          	nop
-1000025c:	01c12083          	lw	ra,28(sp)
-10000260:	01812403          	lw	s0,24(sp)
-10000264:	02010113          	addi	sp,sp,32
-10000268:	00008067          	ret
-
-1000026c <print>:
-1000026c:	fe010113          	addi	sp,sp,-32
-10000270:	00112e23          	sw	ra,28(sp)
-10000274:	00812c23          	sw	s0,24(sp)
-10000278:	02010413          	addi	s0,sp,32
-1000027c:	fea42623          	sw	a0,-20(s0)
-10000280:	01c0006f          	j	1000029c <print+0x30>
-10000284:	fec42783          	lw	a5,-20(s0)
-10000288:	00178713          	addi	a4,a5,1
-1000028c:	fee42623          	sw	a4,-20(s0)
-10000290:	0007c783          	lbu	a5,0(a5)
-10000294:	00078513          	mv	a0,a5
-10000298:	f6dff0ef          	jal	ra,10000204 <putchar>
-1000029c:	fec42783          	lw	a5,-20(s0)
-100002a0:	0007c783          	lbu	a5,0(a5)
-100002a4:	fe0790e3          	bnez	a5,10000284 <print+0x18>
-100002a8:	00000013          	nop
-100002ac:	01c12083          	lw	ra,28(sp)
-100002b0:	01812403          	lw	s0,24(sp)
-100002b4:	02010113          	addi	sp,sp,32
-100002b8:	00008067          	ret
-
-100002bc <main>:
-100002bc:	ff010113          	addi	sp,sp,-16
-100002c0:	00812623          	sw	s0,12(sp)
-100002c4:	01010413          	addi	s0,sp,16
-100002c8:	260007b7          	lui	a5,0x26000
-100002cc:	02478793          	addi	a5,a5,36 # 26000024 <_etext+0x15fffc8c>
-100002d0:	00002737          	lui	a4,0x2
-100002d4:	80870713          	addi	a4,a4,-2040 # 1808 <_ebss+0x1800>
-100002d8:	00e7a023          	sw	a4,0(a5)
-100002dc:	260007b7          	lui	a5,0x26000
-100002e0:	02878793          	addi	a5,a5,40 # 26000028 <_etext+0x15fffc90>
-100002e4:	00002737          	lui	a4,0x2
-100002e8:	80870713          	addi	a4,a4,-2040 # 1808 <_ebss+0x1800>
-100002ec:	00e7a023          	sw	a4,0(a5)
-100002f0:	260007b7          	lui	a5,0x26000
-100002f4:	02c78793          	addi	a5,a5,44 # 2600002c <_etext+0x15fffc94>
-100002f8:	00002737          	lui	a4,0x2
-100002fc:	80870713          	addi	a4,a4,-2040 # 1808 <_ebss+0x1800>
-10000300:	00e7a023          	sw	a4,0(a5)
-10000304:	260007b7          	lui	a5,0x26000
-10000308:	03078793          	addi	a5,a5,48 # 26000030 <_etext+0x15fffc98>
-1000030c:	00002737          	lui	a4,0x2
-10000310:	80870713          	addi	a4,a4,-2040 # 1808 <_ebss+0x1800>
-10000314:	00e7a023          	sw	a4,0(a5)
-10000318:	260007b7          	lui	a5,0x26000
-1000031c:	03478793          	addi	a5,a5,52 # 26000034 <_etext+0x15fffc9c>
-10000320:	00002737          	lui	a4,0x2
-10000324:	80870713          	addi	a4,a4,-2040 # 1808 <_ebss+0x1800>
-10000328:	00e7a023          	sw	a4,0(a5)
-1000032c:	260007b7          	lui	a5,0x26000
-10000330:	03878793          	addi	a5,a5,56 # 26000038 <_etext+0x15fffca0>
-10000334:	00002737          	lui	a4,0x2
-10000338:	80870713          	addi	a4,a4,-2040 # 1808 <_ebss+0x1800>
-1000033c:	00e7a023          	sw	a4,0(a5)
-10000340:	260007b7          	lui	a5,0x26000
-10000344:	03c78793          	addi	a5,a5,60 # 2600003c <_etext+0x15fffca4>
-10000348:	00002737          	lui	a4,0x2
-1000034c:	80870713          	addi	a4,a4,-2040 # 1808 <_ebss+0x1800>
-10000350:	00e7a023          	sw	a4,0(a5)
-10000354:	260007b7          	lui	a5,0x26000
-10000358:	04078793          	addi	a5,a5,64 # 26000040 <_etext+0x15fffca8>
-1000035c:	00002737          	lui	a4,0x2
-10000360:	80870713          	addi	a4,a4,-2040 # 1808 <_ebss+0x1800>
-10000364:	00e7a023          	sw	a4,0(a5)
-10000368:	260007b7          	lui	a5,0x26000
-1000036c:	00100713          	li	a4,1
-10000370:	00e7a023          	sw	a4,0(a5) # 26000000 <_etext+0x15fffc68>
-10000374:	00000013          	nop
-10000378:	260007b7          	lui	a5,0x26000
-1000037c:	0007a703          	lw	a4,0(a5) # 26000000 <_etext+0x15fffc68>
-10000380:	00100793          	li	a5,1
-10000384:	fef70ae3          	beq	a4,a5,10000378 <main+0xbc>
-10000388:	00000013          	nop
-1000038c:	00c12403          	lw	s0,12(sp)
-10000390:	01010113          	addi	sp,sp,16
-10000394:	00008067          	ret
diff --git a/verilog/dv/io_ports/io_ports_tb.v b/verilog/dv/io_ports/io_ports_tb.v
index 8da4873..08843ce 100644
--- a/verilog/dv/io_ports/io_ports_tb.v
+++ b/verilog/dv/io_ports/io_ports_tb.v
@@ -54,7 +54,7 @@
 		// Repeat cycles of 1000 clock edges as needed to complete testbench
 		repeat (25) begin
 			repeat (1000) @(posedge clock);
-			$display("+1000 cycles");
+			// $display("+1000 cycles");
 		end
 		$display("%c[1;31m",27);
 		`ifdef GL
diff --git a/verilog/dv/la_test1/Makefile b/verilog/dv/la_test1/Makefile
index 508ac7b..ea1b0e0 100644
--- a/verilog/dv/la_test1/Makefile
+++ b/verilog/dv/la_test1/Makefile
@@ -21,7 +21,13 @@
 
 # ---- Include Partitioned Makefiles ----
 
-CONFIG = caravel_user_porject
+$(info $(TARGET_PATH))
+
+export DESIGNS = $(TARGET_PATH)
+export TOOLS = /opt/riscv32i/
+
+CONFIG = caravel_user_project
+
 
 include $(MCW_ROOT)/verilog/dv/make/env.makefile
 include $(MCW_ROOT)/verilog/dv/make/var.makefile
diff --git a/verilog/dv/la_test2/Makefile b/verilog/dv/la_test2/Makefile
index 508ac7b..ea1b0e0 100644
--- a/verilog/dv/la_test2/Makefile
+++ b/verilog/dv/la_test2/Makefile
@@ -21,7 +21,13 @@
 
 # ---- Include Partitioned Makefiles ----
 
-CONFIG = caravel_user_porject
+$(info $(TARGET_PATH))
+
+export DESIGNS = $(TARGET_PATH)
+export TOOLS = /opt/riscv32i/
+
+CONFIG = caravel_user_project
+
 
 include $(MCW_ROOT)/verilog/dv/make/env.makefile
 include $(MCW_ROOT)/verilog/dv/make/var.makefile
diff --git a/verilog/dv/la_test2/la_test2_tb.v b/verilog/dv/la_test2/la_test2_tb.v
index 2acf43d..168664b 100644
--- a/verilog/dv/la_test2/la_test2_tb.v
+++ b/verilog/dv/la_test2/la_test2_tb.v
@@ -47,7 +47,7 @@
 		// Repeat cycles of 1000 clock edges as needed to complete testbench
 		repeat (75) begin
 			repeat (1000) @(posedge clock);
-			$display("+1000 cycles");
+			// $display("+1000 cycles");
 		end
 		$display("%c[1;31m",27);
 		`ifdef GL
diff --git a/verilog/dv/mprj_stimulus/Makefile b/verilog/dv/mprj_stimulus/Makefile
index 508ac7b..ea1b0e0 100644
--- a/verilog/dv/mprj_stimulus/Makefile
+++ b/verilog/dv/mprj_stimulus/Makefile
@@ -21,7 +21,13 @@
 
 # ---- Include Partitioned Makefiles ----
 
-CONFIG = caravel_user_porject
+$(info $(TARGET_PATH))
+
+export DESIGNS = $(TARGET_PATH)
+export TOOLS = /opt/riscv32i/
+
+CONFIG = caravel_user_project
+
 
 include $(MCW_ROOT)/verilog/dv/make/env.makefile
 include $(MCW_ROOT)/verilog/dv/make/var.makefile
diff --git a/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v b/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v
index 15d7849..8088ecc 100644
--- a/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v
+++ b/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v
@@ -72,23 +72,14 @@
         $display("Monitor: mprj_stimulus test started");
         wait(status == 4'ha);
         wait(status == 4'h5);
-
-        $display("Monitor: mprj_stimulus test 1 Passed");
-
+        
 	// Values reflect copying user-controlled outputs to memory and back
 	// to management-controlled outputs.  Note that there is a slight
 	// discrepancy in timing when using gate level simulation;  either
 	// of the specified values is okay.
 
-        wait(checkbits == 16'h0840 || checkbits == 16'h0841);
-
-        $display("Monitor: mprj_stimulus test 2 Passed");
-
-
-        wait(checkbits == 16'h0a00 || checkbits == 16'h0a01);
-
-        $display("Monitor: mprj_stimulus test 3 Passed");
-
+        wait(checkbits == 16'h198F);
+        wait(checkbits == 16'h1DDC);
         wait(checkbits == 16'hAB51);
         $display("Monitor: mprj_stimulus test Passed");
         #10000;
diff --git a/verilog/dv/wb_port/Makefile b/verilog/dv/wb_port/Makefile
index 508ac7b..ea1b0e0 100644
--- a/verilog/dv/wb_port/Makefile
+++ b/verilog/dv/wb_port/Makefile
@@ -21,7 +21,13 @@
 
 # ---- Include Partitioned Makefiles ----
 
-CONFIG = caravel_user_porject
+$(info $(TARGET_PATH))
+
+export DESIGNS = $(TARGET_PATH)
+export TOOLS = /opt/riscv32i/
+
+CONFIG = caravel_user_project
+
 
 include $(MCW_ROOT)/verilog/dv/make/env.makefile
 include $(MCW_ROOT)/verilog/dv/make/var.makefile