)]}'
{
  "commit": "07d7fdef0641d0f9ac5e57ad0c9d0e19135e012e",
  "tree": "a4ff41bdfd4098b40c37bad5bca00d9a674cf727",
  "parents": [
    "df70bc468479ee71ea1bc9bb07fe4e429a0a9a06"
  ],
  "author": {
    "name": "Anton Blanchard",
    "email": "anton@linux.ibm.com",
    "time": "Fri Apr 29 10:48:12 2022 +1000"
  },
  "committer": {
    "name": "Anton Blanchard",
    "email": "anton@ozlabs.org",
    "time": "Fri Apr 29 21:32:42 2022 +1000"
  },
  "message": "Add paths and defines to allow partial GL sim\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "07e8925d20c48abbf036495d319987d1a376bbc4",
      "old_mode": 33188,
      "old_path": "verilog/dv/microwatt/make.env",
      "new_id": "5ada6737e6e3a563c40cad65c07703297ff09db7",
      "new_mode": 33188,
      "new_path": "verilog/dv/microwatt/make.env"
    },
    {
      "type": "modify",
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      "old_mode": 33188,
      "old_path": "verilog/dv/microwatt/make.rules",
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      "new_path": "verilog/dv/microwatt/make.rules"
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}