)]}'
{
  "commit": "c1565be8a0bf07e765c81942f8e67c201ae46515",
  "tree": "d40dad8f7adebe92eb04eb01cc46ce19849929be",
  "parents": [
    "7488c0275863e4601b371de4168c37622db0fa79"
  ],
  "author": {
    "name": "Sukru Uzun",
    "email": "sukru.uzun@procenne.com",
    "time": "Sat Mar 12 11:59:23 2022 +0300"
  },
  "committer": {
    "name": "Sukru Uzun",
    "email": "sukru.uzun@procenne.com",
    "time": "Sat Mar 12 11:59:23 2022 +0300"
  },
  "message": "rename module\n",
  "tree_diff": [
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "d68156d53c927d39ade2de6bc82c7f9ce93d4e02",
      "new_mode": 33188,
      "new_path": "verilog/rtl/wb_interconnect/wb_signal_reg.sv"
    },
    {
      "type": "delete",
      "old_id": "2d0121e6ba9c61ec44db5bad17d42667c58e5928",
      "old_mode": 33188,
      "old_path": "verilog/rtl/wb_interconnect/wb_stagging.sv",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    }
  ]
}
