diff --git a/openlane/wb_interconnect/config.tcl b/openlane/wb_interconnect/config.tcl
new file mode 100644
index 0000000..28f8856
--- /dev/null
+++ b/openlane/wb_interconnect/config.tcl
@@ -0,0 +1,28 @@
+# User config
+set ::env(DESIGN_NAME) wb_interconnect
+
+# Change if needed
+set ::env(VERILOG_FILES) "\
+	$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
+	$::env(DESIGN_DIR)/../../verilog/rtl/wb_interconnect/wb_interconnect.sv"
+
+# Fill this
+set ::env(CLOCK_PERIOD) "10.0"
+set ::env(CLOCK_PORT) "clk_i"
+
+set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
+if { [file exists $filename] == 1} {
+	source $filename
+}
+
+# Preserve gate instances in the rtl of the design.
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 400 1200"
+
+set ::env(PL_BASIC_PLACEMENT) 1
+set ::env(PL_TARGET_DENSITY) 0.50
+
+set ::env(VDD_PIN) [list {vccd1}]
+set ::env(GND_PIN) [list {vssd1}]