)]}'
{
  "commit": "7f5a361e316c8354fa6d29a8fc4cd34606c15a44",
  "tree": "34646d4e63e9952da7b277d224105e19a8ed82b4",
  "parents": [
    "1fa178db9879860e512da854877f23dbf3ba2354"
  ],
  "author": {
    "name": "Sukru Uzun",
    "email": "sukru.uzun@procenne.com",
    "time": "Sun Mar 13 13:50:56 2022 +0300"
  },
  "committer": {
    "name": "Sukru Uzun",
    "email": "sukru.uzun@procenne.com",
    "time": "Sun Mar 13 13:50:56 2022 +0300"
  },
  "message": "adding cyc signal\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "a1104c3f6a6421d9d1793ee39495c13a88437c45",
      "old_mode": 33188,
      "old_path": "verilog/rtl/sram/sram_wb_wrapper.sv",
      "new_id": "e003b4a9394b01bd3f2d9403dee649379f36182f",
      "new_mode": 33188,
      "new_path": "verilog/rtl/sram/sram_wb_wrapper.sv"
    }
  ]
}