)]}'
{
  "commit": "7676284b007f15ff3a25bf846160dd33a23e7bb3",
  "tree": "67b02d53d9c48ddd06f2e78b3bf745fff9a8e85b",
  "parents": [
    "b3ac77dd3737f2aa461199484538fd91c363deed"
  ],
  "author": {
    "name": "Sukru Uzun",
    "email": "sukru.uzun@procenne.com",
    "time": "Thu Mar 10 08:39:51 2022 +0300"
  },
  "committer": {
    "name": "Sukru Uzun",
    "email": "sukru.uzun@procenne.com",
    "time": "Thu Mar 10 08:39:51 2022 +0300"
  },
  "message": "initial versions\n",
  "tree_diff": [
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "d9444fe2ec9230ff3d0a60f55092825d13ace209",
      "new_mode": 33188,
      "new_path": "verilog/rtl/sram/sky130_sram_1kbyte_1rw1r_32x256_8.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "289a770ca28b8bb2e1378a85337a03b7bff26aed",
      "new_mode": 33188,
      "new_path": "verilog/rtl/sram/sky130_sram_2kbyte_1rw1r_32x512_8.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "58ec2d381512c2c94738deae381d45fb37423702",
      "new_mode": 33188,
      "new_path": "verilog/rtl/sram/sram_wb_wrapper.sv"
    },
    {
      "type": "modify",
      "old_id": "26081e98ecdd98ac1a677c29dfbd5fb0dbc4ee53",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_proj_example.v",
      "new_id": "d898a3978db94019a357ff26c51a78c2de219441",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_proj_example.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "4631887f36eb5ffa5fb692ddb259b7f9e89a0312",
      "new_mode": 33188,
      "new_path": "verilog/rtl/wb_interconnect/wb_interconnect.sv"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "2d0121e6ba9c61ec44db5bad17d42667c58e5928",
      "new_mode": 33188,
      "new_path": "verilog/rtl/wb_interconnect/wb_stagging.sv"
    }
  ]
}