)]}'
{
  "commit": "7488c0275863e4601b371de4168c37622db0fa79",
  "tree": "c3a26d82ec015e32a88106bf9ff7cf23f4595691",
  "parents": [
    "75ab39e8a39c347c8051532d1289c9f5e503118b"
  ],
  "author": {
    "name": "Sukru Uzun",
    "email": "sukru.uzun@procenne.com",
    "time": "Sat Mar 12 11:59:07 2022 +0300"
  },
  "committer": {
    "name": "Sukru Uzun",
    "email": "sukru.uzun@procenne.com",
    "time": "Sat Mar 12 11:59:07 2022 +0300"
  },
  "message": "adding design paths\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "c9266ee072fe7b741663eee1e72e7e26daf0d072",
      "old_mode": 33261,
      "old_path": "openlane/user_proj_example/config.tcl",
      "new_id": "94eecca2e5b45cc7f3bf66b750562e88f972cc2a",
      "new_mode": 33261,
      "new_path": "openlane/user_proj_example/config.tcl"
    },
    {
      "type": "modify",
      "old_id": "31ab09bb353fc0b5677a44beee6b8cdf6c51e6e7",
      "old_mode": 33188,
      "old_path": "verilog/includes/includes.rtl.caravel_user_project",
      "new_id": "231177155fd67a6d079805638291e17b5b9f18bf",
      "new_mode": 33188,
      "new_path": "verilog/includes/includes.rtl.caravel_user_project"
    },
    {
      "type": "modify",
      "old_id": "3537de803dd1d472e447f0791344cbf5c9391455",
      "old_mode": 33188,
      "old_path": "verilog/rtl/uprj_netlists.v",
      "new_id": "4a1dec95bf3474b5329e655020c880793c87df91",
      "new_mode": 33188,
      "new_path": "verilog/rtl/uprj_netlists.v"
    }
  ]
}
