)]}'
{
  "commit": "61aac8ccd5caef282d7ec53b748859a3a1397b3e",
  "tree": "01ed10d01d9646a0c23cc8cdefb4ea1a113ad951",
  "parents": [
    "7f5a361e316c8354fa6d29a8fc4cd34606c15a44"
  ],
  "author": {
    "name": "Sukru Uzun",
    "email": "sukru.uzun@procenne.com",
    "time": "Sun Mar 13 13:51:29 2022 +0300"
  },
  "committer": {
    "name": "Sukru Uzun",
    "email": "sukru.uzun@procenne.com",
    "time": "Sun Mar 13 13:51:29 2022 +0300"
  },
  "message": "comment unsued, inherent reg struct\n",
  "tree_diff": [
    {
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      "old_mode": 33188,
      "old_path": "verilog/rtl/wb_interconnect/wb_interconnect.sv",
      "new_id": "426a3e0cb1e060fc151b3c7bb4922fcce84352bf",
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}