)]}'
{
  "commit": "5850f65a31d62a9140ecf651288aa48dddc5a6d0",
  "tree": "8015c5076bf8bc575ad3c0d1db53a0622b66978f",
  "parents": [
    "c1565be8a0bf07e765c81942f8e67c201ae46515"
  ],
  "author": {
    "name": "Sukru Uzun",
    "email": "sukru.uzun@procenne.com",
    "time": "Sat Mar 12 12:00:19 2022 +0300"
  },
  "committer": {
    "name": "Sukru Uzun",
    "email": "sukru.uzun@procenne.com",
    "time": "Sat Mar 12 12:00:19 2022 +0300"
  },
  "message": "logic to wire conversion\n",
  "tree_diff": [
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      "old_mode": 33188,
      "old_path": "verilog/rtl/sram/sram_wb_wrapper.sv",
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      "new_mode": 33188,
      "new_path": "verilog/rtl/sram/sram_wb_wrapper.sv"
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      "new_id": "72d6f8954f1a4389b0dc0e4f59247f0aca49bc62",
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}