)]}'
{
  "commit": "2b56126d26813a7c176cc8af858d9a7cec57889e",
  "tree": "b6bd5c4e710a49d2cc078edc1873021237f01999",
  "parents": [
    "2d22d4f0c0c0bcc0deacdf843980b7f88b00f4ce"
  ],
  "author": {
    "name": "Emre Goncu",
    "email": "emre.goncu@procenne.com",
    "time": "Sun Mar 20 02:05:28 2022 +0300"
  },
  "committer": {
    "name": "Emre Goncu",
    "email": "emre.goncu@procenne.com",
    "time": "Sun Mar 20 02:05:28 2022 +0300"
  },
  "message": "Openlane flow passed for SPI core and fixed UART\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "159c97bba0e4c84f425aa207b27c4a536502737f",
      "old_mode": 33188,
      "old_path": "gds/user_proj_example.gds",
      "new_id": "efc009dc2054e3eb98ef9df69abe605b3b7202f5",
      "new_mode": 33188,
      "new_path": "gds/user_proj_example.gds"
    },
    {
      "type": "modify",
      "old_id": "3c3bb7e43e1b31810666cfaadf0e1bf527662288",
      "old_mode": 33188,
      "old_path": "lef/user_proj_example.lef",
      "new_id": "38e6777f5c8141e02913c4cd0bf52c07af9940c2",
      "new_mode": 33188,
      "new_path": "lef/user_proj_example.lef"
    },
    {
      "type": "modify",
      "old_id": "3672fa930720e05ed08492e46875a2bc1a424ebb",
      "old_mode": 33188,
      "old_path": "openlane/user_proj_example/config.tcl",
      "new_id": "bee70c69db2874a9d60844c2d6f2078e1d553b16",
      "new_mode": 33188,
      "new_path": "openlane/user_proj_example/config.tcl"
    },
    {
      "type": "modify",
      "old_id": "48af6a29eeada9e52d1f0ad9dea7f6f9f399e138",
      "old_mode": 33188,
      "old_path": "verilog/gl/user_proj_example.v",
      "new_id": "604172f3d6e4fb11c3eb055bca5bc46cc8e9ac8f",
      "new_mode": 33188,
      "new_path": "verilog/gl/user_proj_example.v"
    }
  ]
}
