diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index a7365ab..32645a7 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1 +1,3 @@
-mprj 1175 1690 N
+interconnect 400  1200 N
+wb_wrapper0  400  600  N
+u_sram1_1kb  2000 800  N
\ No newline at end of file
diff --git a/verilog/rtl/sram/sram_wb_wrapper.sv b/verilog/rtl/sram/sram_wb_wrapper.sv
index e003b4a..4bdfba8 100644
--- a/verilog/rtl/sram/sram_wb_wrapper.sv
+++ b/verilog/rtl/sram/sram_wb_wrapper.sv
@@ -17,14 +17,18 @@
 // @revision :
 //    0.1 - 10 March 2022, Sukru Uzun
 //          initial version
+//    0.2 - 16 March 2022, Sukru Uzun
+//          remove SRAM design
 //-----------------------------------------------------------------------------
 
 module sram_wb_wrapper #(
-    parameter SRAM_ADDR_WD    = 9,
-    parameter SRAM_DATA_WD    = 32,
-    parameter SRAM_ADDR_START = 9'h000,
-    parameter SRAM_ADDR_END   = 9'h1F8)
+    parameter SRAM_ADDR_WD = 8,
+    parameter SRAM_DATA_WD = 32)
     (
+`ifdef USE_POWER_PINS
+    input   logic                       vccd1,    // User area 1 1.8V supply
+    input   logic                       vssd1,    // User area 1 digital ground
+`endif
     input   logic                       rst_n,
     // Wishbone Interface
     input   logic                       wb_clk_i,  // System clock
@@ -34,26 +38,37 @@
     input   logic                       wb_we_i,   // write
     input   logic [SRAM_DATA_WD-1:0]    wb_dat_i,  // data output
     input   logic [SRAM_DATA_WD/8-1:0]  wb_sel_i,  // byte enable
-    output  wire  [SRAM_DATA_WD-1:0]    wb_dat_o,  // data input
-    output  logic                       wb_ack_o   // acknowlegement
+    // output  wire  [SRAM_DATA_WD-1:0]    wb_dat_o,  // data input
+    output  logic                       wb_ack_o,  // acknowlegement
+    // SRAM Interface
+    // Port A
+    output  wire                        sram_csb_a,
+    output  wire [SRAM_ADDR_WD-1:0]     sram_addr_a,
+
+    // Port B
+    output  wire                        sram_csb_b,
+    output  wire                        sram_web_b,
+    output  wire [SRAM_DATA_WD/8-1:0]   sram_mask_b,
+    output  wire [SRAM_ADDR_WD-1:0]     sram_addr_b,
+    output  wire [SRAM_DATA_WD-1:0]     sram_din_b
 );
 
-// Port A
-wire                      sram_clk_a;
-wire                      sram_csb_a;
-wire [SRAM_ADDR_WD-1:0]   sram_addr_a;
-wire [SRAM_DATA_WD-1:0]   sram_dout_a;
+// // Port A
+// wire                      sram_clk_a;
+// wire                      sram_csb_a;
+// wire [SRAM_ADDR_WD-1:0]   sram_addr_a;
+// wire [SRAM_DATA_WD-1:0]   sram_dout_a;
 
-// Port B
-wire                      sram_clk_b;
-wire                      sram_csb_b;
-wire                      sram_web_b;
-wire [SRAM_DATA_WD/8-1:0] sram_mask_b;
-wire [SRAM_ADDR_WD-1:0]   sram_addr_b;
-wire [SRAM_DATA_WD-1:0]   sram_din_b;
+// // Port B
+// wire                      sram_clk_b;
+// wire                      sram_csb_b;
+// wire                      sram_web_b;
+// wire [SRAM_DATA_WD/8-1:0] sram_mask_b;
+// wire [SRAM_ADDR_WD-1:0]   sram_addr_b;
+// wire [SRAM_DATA_WD-1:0]   sram_din_b;
 
 // Memory Write Port
-assign sram_clk_b  = wb_clk_i;
+// assign sram_clk_b  = wb_clk_i;
 assign sram_csb_b  = !wb_stb_i;
 assign sram_web_b  = !wb_we_i;
 assign sram_mask_b = wb_sel_i;
@@ -61,31 +76,31 @@
 assign sram_din_b  = wb_dat_i;
 
 // Memory Read Port
-assign sram_clk_a  = wb_clk_i;
+// assign sram_clk_a  = wb_clk_i;
 assign sram_csb_a  = (wb_stb_i == 1'b1 && wb_we_i == 1'b0 && wb_cyc_i == 1'b1) ? 1'b0 : 1'b1;
 assign sram_addr_a = wb_adr_i;
 
-assign wb_dat_o    = sram_dout_a;
+// assign wb_dat_o    = sram_dout_a;
 
-sky130_sram_2kbyte_1rw1r_32x512_8 u_sram1_2kb(
-`ifdef USE_POWER_PINS
-    .vccd1 (vccd1), // User area 1 1.8V supply
-    .vssd1 (vssd1), // User area 1 digital ground
-`endif
-    // Port 0: RW
-    .clk0     (sram_clk_b),
-    .csb0     (sram_csb_b),
-    .web0     (sram_web_b),
-    .wmask0   (sram_mask_b),
-    .addr0    (sram_addr_b),
-    .din0     (sram_din_b),
-    .dout0    (),   // dont read from Port B
-    // Port 1: R
-    .clk1     (sram_clk_a),
-    .csb1     (sram_csb_a),
-    .addr1    (sram_addr_a),
-    .dout1    (sram_dout_a)
-);
+// sky130_sram_1kbyte_1rw1r_32x256_8 u_sram1_1kb(
+// `ifdef USE_POWER_PINS
+//     .vccd1 (vccd1), // User area 1 1.8V supply
+//     .vssd1 (vssd1), // User area 1 digital ground
+// `endif
+//     // Port 0: RW
+//     .clk0     (sram_clk_b),
+//     .csb0     (sram_csb_b),
+//     .web0     (sram_web_b),
+//     .wmask0   (sram_mask_b),
+//     .addr0    (sram_addr_b),
+//     .din0     (sram_din_b),
+//     .dout0    (),   // dont read from Port B
+//     // Port 1: R
+//     .clk1     (sram_clk_a),
+//     .csb1     (sram_csb_a),
+//     .addr1    (sram_addr_a),
+//     .dout1    (sram_dout_a)
+// );
 
 // Generate once cycle delayed ACK to get the data from SRAM
 always @(negedge rst_n or posedge wb_clk_i) 
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 5ee1cee..e19ac9b 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -82,40 +82,157 @@
 /* User project is instantiated  here   */
 /*--------------------------------------*/
 
-user_proj_example mprj (
+parameter WB_WIDTH        = 32; // WB ADDRESS/DATA WIDTH
+parameter SRAM_ADDR_WD    = 8;
+parameter SRAM_DATA_WD    = 32;
+
+//---------------------------------------------------------------------
+// WB Master Interface
+//---------------------------------------------------------------------
+wire rst_n = not(wb_rst_i);
+wire [`MPRJ_IO_PADS-1:0] io_in;
+wire [`MPRJ_IO_PADS-1:0] io_out;
+wire [`MPRJ_IO_PADS-1:0] io_oeb;
+
+//---------------------------------------------------------------------
+// SRAM
+//---------------------------------------------------------------------
+wire                       s0_wb_cyc_i;
+wire                       s0_wb_stb_i;
+wire [SRAM_ADDR_WD-1:0]    s0_wb_adr_i;
+wire                       s0_wb_we_i;
+wire [SRAM_DATA_WD-1:0]    s0_wb_dat_i;
+wire [SRAM_DATA_WD/8-1:0]  s0_wb_sel_i;
+wire [SRAM_DATA_WD-1:0]    s0_wb_dat_o;
+wire                       s0_wb_ack_o;
+
+// Port A
+wire                      sram_clk_a;
+wire                      sram_csb_a;
+wire [SRAM_ADDR_WD-1:0]   sram_addr_a;
+wire [SRAM_DATA_WD-1:0]   sram_dout_a;
+
+// Port B
+wire                      sram_clk_b;
+wire                      sram_csb_b;
+wire                      sram_web_b;
+wire [SRAM_DATA_WD/8-1:0] sram_mask_b;
+wire [SRAM_ADDR_WD-1:0]   sram_addr_b;
+wire [SRAM_DATA_WD-1:0]   sram_din_b;
+
+wb_interconnect interconnect
+(
 `ifdef USE_POWER_PINS
-	.vccd1(vccd1),	// User area 1 1.8V power
-	.vssd1(vssd1),	// User area 1 digital ground
+    .vccd1(vccd1),    // User area 1 1.8V supply
+    .vssd1(vssd1),    // User area 1 digital ground
 `endif
+    .clk_i(wb_clk_i),
+    .rst_n(rst_n),
 
-    .wb_clk_i(wb_clk_i),
-    .wb_rst_i(wb_rst_i),
+    // Master 0 Interface
+    .m0_wb_dat_i(wbs_dat_i),
+    .m0_wb_adr_i(wbs_adr_i),
+    .m0_wb_sel_i(wbs_sel_i),
+    .m0_wb_we_i (wbs_we_i),
+    .m0_wb_cyc_i(wbs_cyc_i),
+    .m0_wb_stb_i(wbs_stb_i),
+    .m0_wb_dat_o(wbs_dat_o),
+    .m0_wb_ack_o(wbs_ack_o),
 
-    // MGMT SoC Wishbone Slave
+    // Slave 0 Interface
+    .s0_wb_dat_i(sram_dout_a),
+    .s0_wb_ack_i(s0_wb_ack_o),
+    .s0_wb_dat_o(s0_wb_dat_i),
+    .s0_wb_adr_o(s0_wb_adr_i),
+    .s0_wb_sel_o(s0_wb_sel_i),
+    .s0_wb_we_o (s0_wb_we_i),
+    .s0_wb_cyc_o(s0_wb_cyc_i),
+    .s0_wb_stb_o(s0_wb_stb_i)
 
-    .wbs_cyc_i(wbs_cyc_i),
-    .wbs_stb_i(wbs_stb_i),
-    .wbs_we_i(wbs_we_i),
-    .wbs_sel_i(wbs_sel_i),
-    .wbs_adr_i(wbs_adr_i),
-    .wbs_dat_i(wbs_dat_i),
-    .wbs_ack_o(wbs_ack_o),
-    .wbs_dat_o(wbs_dat_o),
+    // Slave 1 Interface
+    // .s1_wb_dat_i(),
+    // .s1_wb_ack_i(),
+    // .s1_wb_dat_o(),
+    // .s1_wb_adr_o(),
+    // .s1_wb_sel_o(),
+    // .s1_wb_we_o (),
+    // .s1_wb_cyc_o(),
+    // .s1_wb_stb_o(),
 
-    // Logic Analyzer
+    // Slave 2 Interface
+    // .s2_wb_dat_i(),
+    // .s2_wb_ack_i(),
+    // .s2_wb_dat_o(),
+    // .s2_wb_adr_o(),
+    // .s2_wb_sel_o(),
+    // .s2_wb_we_o (),
+    // .s2_wb_cyc_o(),
+    // .s2_wb_stb_o(),
 
-    .la_data_in(la_data_in),
-    .la_data_out(la_data_out),
-    .la_oenb (la_oenb),
+    // Slave 3 Interface
+    // .s3_wb_dat_i(),
+    // .s3_wb_ack_i(),
+    // .s3_wb_dat_o(),
+    // .s3_wb_adr_o(),
+    // .s3_wb_sel_o(),
+    // .s3_wb_we_o (),
+    // .s3_wb_cyc_o(),
+    // .s3_wb_stb_o()
+);
 
-    // IO Pads
+sram_wb_wrapper #(
+`ifndef SYNTHESIS
+    .SRAM_ADDR_WD   (SRAM_ADDR_WD),
+    .SRAM_DATA_WD   (SRAM_DATA_WD) 
+`endif
+    )
+    wb_wrapper0 (
+`ifdef USE_POWER_PINS
+    .vccd1 (vccd1), // User area 1 1.8V supply
+    .vssd1 (vssd1), // User area 1 digital ground
+`endif
+    .rst_n(rst_n),
+    // Wishbone Interface
+    .wb_clk_i(wb_clk_i),     // System clock
+    .wb_cyc_i(s0_wb_cyc_i),  // cycle enable
+    .wb_stb_i(s0_wb_stb_i),  // strobe
+    .wb_adr_i(s0_wb_adr_i),  // address
+    .wb_we_i (s0_wb_we_i),   // write
+    .wb_dat_i(s0_wb_dat_i),  // data output
+    .wb_sel_i(s0_wb_sel_i),  // byte enable
+    // .wb_dat_o(s0_wb_dat_o),  // data input
+    .wb_ack_o(s0_wb_ack_o),  // acknowlegement
+    // SRAM Interface
+    // Port A
+    .sram_csb_a(sram_csb_a),
+    .sram_addr_a(sram_addr_a),
 
-    .io_in (io_in),
-    .io_out(io_out),
-    .io_oeb(io_oeb),
+    // Port B
+    .sram_csb_b(sram_csb_b),
+    .sram_web_b(sram_web_b),
+    .sram_mask_b(sram_mask_b),
+    .sram_addr_b(sram_addr_b),
+    .sram_din_b(sram_din_b)
+);
 
-    // IRQ
-    .irq(user_irq)
+sky130_sram_1kbyte_1rw1r_32x256_8 u_sram1_1kb(
+`ifdef USE_POWER_PINS
+    .vccd1 (vccd1), // User area 1 1.8V supply
+    .vssd1 (vssd1), // User area 1 digital ground
+`endif
+    // Port 0: RW
+    .clk0     (wb_clk_i),
+    .csb0     (sram_csb_b),
+    .web0     (sram_web_b),
+    .wmask0   (sram_mask_b),
+    .addr0    (sram_addr_b),
+    .din0     (sram_din_b),
+    .dout0    (),   // dont read from Port B
+    // Port 1: R
+    .clk1     (wb_clk_i),
+    .csb1     (sram_csb_a),
+    .addr1    (sram_addr_a),
+    .dout1    (sram_dout_a)
 );
 
 endmodule	// user_project_wrapper
diff --git a/verilog/rtl/wb_interconnect/wb_interconnect.sv b/verilog/rtl/wb_interconnect/wb_interconnect.sv
index 05912ce..598322d 100644
--- a/verilog/rtl/wb_interconnect/wb_interconnect.sv
+++ b/verilog/rtl/wb_interconnect/wb_interconnect.sv
@@ -46,7 +46,7 @@
     input	logic [31:0]   s0_wb_dat_i,
     input	logic 	       s0_wb_ack_i,
     output	wire  [31:0]   s0_wb_dat_o,
-    output	wire  [8:0]	   s0_wb_adr_o,
+    output	wire  [7:0]	   s0_wb_adr_o,
     output	wire  [3:0]	   s0_wb_sel_o,
     output	wire  	       s0_wb_we_o,
     output	wire  	       s0_wb_cyc_o,
@@ -121,7 +121,7 @@
 // Slave Mapping
 //---------------------------------------
 assign s0_wb_dat_o = m0_wb_dat_i_reg;
-assign s0_wb_adr_o = m0_wb_adr_reg[8:0];
+assign s0_wb_adr_o = m0_wb_adr_reg[7:0];
 assign s0_wb_sel_o = m0_wb_sel_reg;
 assign s0_wb_we_o  = m0_wb_we_reg;
 assign s0_wb_cyc_o = m0_wb_cyc_reg;