diff --git a/Makefile b/Makefile
index 27947df..1f36a8e 100644
--- a/Makefile
+++ b/Makefile
@@ -65,7 +65,7 @@
 # Openlane
 blocks=$(shell cd openlane && find * -maxdepth 0 -type d)
 .PHONY: $(blocks)
-$(blocks): % :
+$(blocks):
 	export CARAVEL_ROOT=$(CARAVEL_ROOT) && cd openlane && $(MAKE) $*
 
 dv_patterns=$(shell cd verilog/dv && find * -maxdepth 0 -type d)
@@ -92,14 +92,8 @@
 .PHONY: harden
 harden: $(blocks)
 
-.PHONY: verify-all-rtl
-verify-all-rtl: $(dv-targets-rtl)
-
-.PHONY: verify-all-gl
-verify-all-gl: $(dv-targets-gl)
-
-.PHONY: verify-all-gl-sdf
-verify-all-gl-sdf: $(dv-targets-gl-sdf)
+.PHONY: verify
+verify: $(dv-targets)
 
 $(dv-targets-rtl): SIM=RTL
 $(dv-targets-rtl): verify-%-rtl: $(dv_base_dependencies)
@@ -165,7 +159,7 @@
 # Default installs to the user home directory, override by "export PRECHECK_ROOT=<precheck-installation-path>"
 .PHONY: precheck
 precheck:
-	@git clone --depth=1 --branch $(MPW_TAG) https://github.com/efabless/mpw_precheck.git $(PRECHECK_ROOT)
+	@git clone --depth=1 --branch mpw-5a https://github.com/efabless/mpw_precheck.git $(PRECHECK_ROOT)
 	@docker pull efabless/mpw_precheck:latest
 
 .PHONY: run-precheck
@@ -204,3 +198,8 @@
 help:
 	cd $(CARAVEL_ROOT) && $(MAKE) help
 	@$(MAKE) -pRrq -f $(lastword $(MAKEFILE_LIST)) : 2>/dev/null | awk -v RS= -F: '/^# File/,/^# Finished Make data base/ {if ($$1 !~ "^[#.]") {print $$1}}' | sort | egrep -v -e '^[^[:alnum:]]' -e '^$@$$'
+<<<<<<< HEAD
+=======
+
+
+>>>>>>> c8bbbebb7f2e4756c91a6f5fbcd8071567f8f62b
diff --git a/verilog/rtl/Core.v b/verilog/rtl/Core.v
index fd15114..81d18fb 100644
--- a/verilog/rtl/Core.v
+++ b/verilog/rtl/Core.v
@@ -1,18 +1,3 @@
-// SPDX-FileCopyrightText: 2022 EE, UET Lahore
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//      http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Created by Muhammad Tahir <mtahir@uet.edu.pk>
 module CSR( // @[:@3.2]
   input         clock, // @[:@4.4]
   input         reset, // @[:@5.4]
diff --git a/verilog/rtl/DMem.v b/verilog/rtl/DMem.v
index 5e23109..7108a81 100644
--- a/verilog/rtl/DMem.v
+++ b/verilog/rtl/DMem.v
@@ -1,18 +1,3 @@
-// SPDX-FileCopyrightText: 2022 EE, UET Lahore
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//      http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Created by Muhammad Tahir <mtahir@uet.edu.pk>
 module DMem( // @[:@12681.2]
   input         clock, // @[:@12682.4]
   input  [7:0]  io_addr, // @[:@12684.4]
diff --git a/verilog/rtl/IMem.v b/verilog/rtl/IMem.v
index a95100a..daf98dd 100644
--- a/verilog/rtl/IMem.v
+++ b/verilog/rtl/IMem.v
@@ -1,18 +1,3 @@
-// SPDX-FileCopyrightText: 2022 EE, UET Lahore
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//      http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Created by Muhammad Tahir <mtahir@uet.edu.pk>
 module IMem( // @[:@12666.2]
   input         clock, // @[:@12667.4]
   input  [8:0]  io_addr, // @[:@12669.4]
diff --git a/verilog/rtl/Motor_Top.v b/verilog/rtl/Motor_Top.v
index fff906a..af06661 100644
--- a/verilog/rtl/Motor_Top.v
+++ b/verilog/rtl/Motor_Top.v
@@ -1,18 +1,3 @@
-// SPDX-FileCopyrightText: 2022 EE, UET Lahore
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//      http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Created by Muhammad Tahir <mtahir@uet.edu.pk>
 module Interlink_Module( // @[:@4032.2]
   input         clock, // @[:@4033.4]
   input         reset, // @[:@4034.4]
diff --git a/verilog/rtl/Processor_Tile.v b/verilog/rtl/Processor_Tile.v
index 024107b..6bc19e4 100644
--- a/verilog/rtl/Processor_Tile.v
+++ b/verilog/rtl/Processor_Tile.v
@@ -1,18 +1,3 @@
-// SPDX-FileCopyrightText: 2022 EE, UET Lahore
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//      http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Created by Muhammad Tahir <mtahir@uet.edu.pk>
 module Processor_Tile( // @[:@12742.2]
   input   clock, // @[:@12743.4]
   input   reset, // @[:@12744.4]
diff --git a/verilog/rtl/WB_InterConnect.v b/verilog/rtl/WB_InterConnect.v
index c4ff6b8..aa4338a 100644
--- a/verilog/rtl/WB_InterConnect.v
+++ b/verilog/rtl/WB_InterConnect.v
@@ -1,18 +1,3 @@
-// SPDX-FileCopyrightText: 2022 EE, UET Lahore
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//      http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Created by Muhammad Tahir <mtahir@uet.edu.pk>
 module DMem_Interface( // @[:@1882.2]
   input         clock, // @[:@1883.4]
   input         reset, // @[:@1884.4]
diff --git a/verilog/rtl/sky130_sram_1kbyte_1rw1r_32x256_8.v b/verilog/rtl/sky130_sram_1kbyte_1rw1r_32x256_8.v
index fe885ed..1365c9a 100644
--- a/verilog/rtl/sky130_sram_1kbyte_1rw1r_32x256_8.v
+++ b/verilog/rtl/sky130_sram_1kbyte_1rw1r_32x256_8.v
@@ -1,3 +1,18 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
 // OpenRAM SRAM model
 // Words: 256
 // Word size: 32
diff --git a/verilog/rtl/sky130_sram_2kbyte_1rw1r_32x512_8.v b/verilog/rtl/sky130_sram_2kbyte_1rw1r_32x512_8.v
index 7da4327..8c57ab3 100755
--- a/verilog/rtl/sky130_sram_2kbyte_1rw1r_32x512_8.v
+++ b/verilog/rtl/sky130_sram_2kbyte_1rw1r_32x512_8.v
@@ -1,3 +1,18 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
 // OpenRAM SRAM model
 // Words: 512
 // Word size: 32
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 9771a84..0c20895 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: 2020 Efabless Corporation
+// SPDX-FileCopyrightText: 2022 EE, UET Lahore
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -12,6 +12,7 @@
 // See the License for the specific language governing permissions and
 // limitations under the License.
 // SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Muhammad Tahir <mtahir@uet.edu.pk>
 
 `default_nettype none
 /*