diff --git a/verilog/rtl/DMem.v b/verilog/rtl/DMem.v
new file mode 100644
index 0000000..7108a81
--- /dev/null
+++ b/verilog/rtl/DMem.v
@@ -0,0 +1,178 @@
+module DMem( // @[:@12681.2]
+  input         clock, // @[:@12682.4]
+  input  [7:0]  io_addr, // @[:@12684.4]
+  input  [31:0] io_wdata, // @[:@12684.4]
+  output [31:0] io_rdata, // @[:@12684.4]
+  input         io_cs, // @[:@12684.4]
+  input         io_wr_en, // @[:@12684.4]
+  input  [3:0]  io_st_type // @[:@12684.4]
+);
+  reg [7:0] dmem [0:1023]; // @[dmemory.scala 26:26:@12686.4]
+  reg [31:0] _RAND_0;
+  wire [7:0] dmem__T_65_data; // @[dmemory.scala 26:26:@12686.4]
+  wire [9:0] dmem__T_65_addr; // @[dmemory.scala 26:26:@12686.4]
+  wire [7:0] dmem__T_69_data; // @[dmemory.scala 26:26:@12686.4]
+  wire [9:0] dmem__T_69_addr; // @[dmemory.scala 26:26:@12686.4]
+  wire [7:0] dmem__T_73_data; // @[dmemory.scala 26:26:@12686.4]
+  wire [9:0] dmem__T_73_addr; // @[dmemory.scala 26:26:@12686.4]
+  wire [7:0] dmem__T_74_data; // @[dmemory.scala 26:26:@12686.4]
+  wire [9:0] dmem__T_74_addr; // @[dmemory.scala 26:26:@12686.4]
+  wire [7:0] dmem__T_38_data; // @[dmemory.scala 26:26:@12686.4]
+  wire [9:0] dmem__T_38_addr; // @[dmemory.scala 26:26:@12686.4]
+  wire  dmem__T_38_mask; // @[dmemory.scala 26:26:@12686.4]
+  wire  dmem__T_38_en; // @[dmemory.scala 26:26:@12686.4]
+  wire [7:0] dmem__T_45_data; // @[dmemory.scala 26:26:@12686.4]
+  wire [9:0] dmem__T_45_addr; // @[dmemory.scala 26:26:@12686.4]
+  wire  dmem__T_45_mask; // @[dmemory.scala 26:26:@12686.4]
+  wire  dmem__T_45_en; // @[dmemory.scala 26:26:@12686.4]
+  wire [7:0] dmem__T_52_data; // @[dmemory.scala 26:26:@12686.4]
+  wire [9:0] dmem__T_52_addr; // @[dmemory.scala 26:26:@12686.4]
+  wire  dmem__T_52_mask; // @[dmemory.scala 26:26:@12686.4]
+  wire  dmem__T_52_en; // @[dmemory.scala 26:26:@12686.4]
+  wire [7:0] dmem__T_59_data; // @[dmemory.scala 26:26:@12686.4]
+  wire [9:0] dmem__T_59_addr; // @[dmemory.scala 26:26:@12686.4]
+  wire  dmem__T_59_mask; // @[dmemory.scala 26:26:@12686.4]
+  wire  dmem__T_59_en; // @[dmemory.scala 26:26:@12686.4]
+  wire  mem_wr; // @[dmemory.scala 31:27:@12687.4]
+  wire  _T_36; // @[dmemory.scala 40:18:@12690.6]
+  wire  _GEN_3; // @[dmemory.scala 40:30:@12692.6]
+  wire  _T_40; // @[dmemory.scala 43:18:@12697.6]
+  wire [8:0] _T_43; // @[dmemory.scala 44:17:@12700.8]
+  wire [7:0] _T_44; // @[dmemory.scala 44:17:@12701.8]
+  wire  _T_47; // @[dmemory.scala 46:18:@12706.6]
+  wire [8:0] _T_50; // @[dmemory.scala 47:17:@12709.8]
+  wire [7:0] _T_51; // @[dmemory.scala 47:17:@12710.8]
+  wire  _T_54; // @[dmemory.scala 49:18:@12715.6]
+  wire [8:0] _T_57; // @[dmemory.scala 50:17:@12718.8]
+  wire [7:0] _T_58; // @[dmemory.scala 50:17:@12719.8]
+  wire [15:0] _T_75; // @[Cat.scala 30:58:@12736.4]
+  wire [15:0] _T_76; // @[Cat.scala 30:58:@12737.4]
+  wire [9:0] _GEN_41;
+  reg [9:0] dmem__T_65_addr_pipe_0;
+  reg [31:0] _RAND_1;
+  wire [9:0] _GEN_43;
+  reg [9:0] dmem__T_69_addr_pipe_0;
+  reg [31:0] _RAND_2;
+  wire [9:0] _GEN_45;
+  reg [9:0] dmem__T_73_addr_pipe_0;
+  reg [31:0] _RAND_3;
+  wire [9:0] _GEN_47;
+  reg [9:0] dmem__T_74_addr_pipe_0;
+  reg [31:0] _RAND_4;
+  assign dmem__T_65_addr = dmem__T_65_addr_pipe_0;
+  assign dmem__T_65_data = dmem[dmem__T_65_addr]; // @[dmemory.scala 26:26:@12686.4]
+  assign dmem__T_69_addr = dmem__T_69_addr_pipe_0;
+  assign dmem__T_69_data = dmem[dmem__T_69_addr]; // @[dmemory.scala 26:26:@12686.4]
+  assign dmem__T_73_addr = dmem__T_73_addr_pipe_0;
+  assign dmem__T_73_data = dmem[dmem__T_73_addr]; // @[dmemory.scala 26:26:@12686.4]
+  assign dmem__T_74_addr = dmem__T_74_addr_pipe_0;
+  assign dmem__T_74_data = dmem[dmem__T_74_addr]; // @[dmemory.scala 26:26:@12686.4]
+  assign dmem__T_38_data = io_wdata[7:0];
+  assign dmem__T_38_addr = {{2'd0}, io_addr};
+  assign dmem__T_38_mask = 1'h1;
+  assign dmem__T_38_en = mem_wr ? _T_36 : 1'h0;
+  assign dmem__T_45_data = io_wdata[15:8];
+  assign dmem__T_45_addr = {{2'd0}, _T_44};
+  assign dmem__T_45_mask = 1'h1;
+  assign dmem__T_45_en = mem_wr ? _T_40 : 1'h0;
+  assign dmem__T_52_data = io_wdata[23:16];
+  assign dmem__T_52_addr = {{2'd0}, _T_51};
+  assign dmem__T_52_mask = 1'h1;
+  assign dmem__T_52_en = mem_wr ? _T_47 : 1'h0;
+  assign dmem__T_59_data = io_wdata[31:24];
+  assign dmem__T_59_addr = {{2'd0}, _T_58};
+  assign dmem__T_59_mask = 1'h1;
+  assign dmem__T_59_en = mem_wr ? _T_54 : 1'h0;
+  assign mem_wr = io_wr_en & io_cs; // @[dmemory.scala 31:27:@12687.4]
+  assign _T_36 = io_st_type[0]; // @[dmemory.scala 40:18:@12690.6]
+  assign _GEN_3 = 1'h1; // @[dmemory.scala 40:30:@12692.6]
+  assign _T_40 = io_st_type[1]; // @[dmemory.scala 43:18:@12697.6]
+  assign _T_43 = io_addr + 8'h1; // @[dmemory.scala 44:17:@12700.8]
+  assign _T_44 = io_addr + 8'h1; // @[dmemory.scala 44:17:@12701.8]
+  assign _T_47 = io_st_type[2]; // @[dmemory.scala 46:18:@12706.6]
+  assign _T_50 = io_addr + 8'h2; // @[dmemory.scala 47:17:@12709.8]
+  assign _T_51 = io_addr + 8'h2; // @[dmemory.scala 47:17:@12710.8]
+  assign _T_54 = io_st_type[3]; // @[dmemory.scala 49:18:@12715.6]
+  assign _T_57 = io_addr + 8'h3; // @[dmemory.scala 50:17:@12718.8]
+  assign _T_58 = io_addr + 8'h3; // @[dmemory.scala 50:17:@12719.8]
+  assign _T_75 = {dmem__T_73_data,dmem__T_74_data}; // @[Cat.scala 30:58:@12736.4]
+  assign _T_76 = {dmem__T_65_data,dmem__T_69_data}; // @[Cat.scala 30:58:@12737.4]
+  assign io_rdata = {_T_76,_T_75}; // @[dmemory.scala 57:12:@12740.4]
+  assign _GEN_41 = {{2'd0}, _T_58};
+  assign _GEN_43 = {{2'd0}, _T_51};
+  assign _GEN_45 = {{2'd0}, _T_44};
+  assign _GEN_47 = {{2'd0}, io_addr};
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE
+  integer initvar;
+  initial begin
+    `ifdef INIT_RANDOM
+      `INIT_RANDOM
+    `endif
+    `ifndef VERILATOR
+      #0.002 begin end
+    `endif
+  _RAND_0 = {1{`RANDOM}};
+  `ifdef RANDOMIZE_MEM_INIT
+  for (initvar = 0; initvar < 1024; initvar = initvar+1)
+    dmem[initvar] = _RAND_0[7:0];
+  `endif // RANDOMIZE_MEM_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_1 = {1{`RANDOM}};
+  dmem__T_65_addr_pipe_0 = _RAND_1[9:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_2 = {1{`RANDOM}};
+  dmem__T_69_addr_pipe_0 = _RAND_2[9:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_3 = {1{`RANDOM}};
+  dmem__T_73_addr_pipe_0 = _RAND_3[9:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_4 = {1{`RANDOM}};
+  dmem__T_74_addr_pipe_0 = _RAND_4[9:0];
+  `endif // RANDOMIZE_REG_INIT
+  end
+`endif // RANDOMIZE
+  always @(posedge clock) begin
+    if(dmem__T_38_en & dmem__T_38_mask) begin
+      dmem[dmem__T_38_addr] <= dmem__T_38_data; // @[dmemory.scala 26:26:@12686.4]
+    end
+    if(dmem__T_45_en & dmem__T_45_mask) begin
+      dmem[dmem__T_45_addr] <= dmem__T_45_data; // @[dmemory.scala 26:26:@12686.4]
+    end
+    if(dmem__T_52_en & dmem__T_52_mask) begin
+      dmem[dmem__T_52_addr] <= dmem__T_52_data; // @[dmemory.scala 26:26:@12686.4]
+    end
+    if(dmem__T_59_en & dmem__T_59_mask) begin
+      dmem[dmem__T_59_addr] <= dmem__T_59_data; // @[dmemory.scala 26:26:@12686.4]
+    end
+    if (_GEN_3) begin
+      dmem__T_65_addr_pipe_0 <= _GEN_41;
+    end
+    if (_GEN_3) begin
+      dmem__T_69_addr_pipe_0 <= _GEN_43;
+    end
+    if (_GEN_3) begin
+      dmem__T_73_addr_pipe_0 <= _GEN_45;
+    end
+    if (_GEN_3) begin
+      dmem__T_74_addr_pipe_0 <= _GEN_47;
+    end
+  end
+endmodule
diff --git a/verilog/rtl/IMem.v b/verilog/rtl/IMem.v
new file mode 100644
index 0000000..1df1163
--- /dev/null
+++ b/verilog/rtl/IMem.v
@@ -0,0 +1,73 @@
+module IMem( // @[:@12666.2]
+  input         clock, // @[:@12667.4]
+  input  [8:0]  io_addr, // @[:@12669.4]
+  output [31:0] io_rdata, // @[:@12669.4]
+  input  [31:0] io_wdata, // @[:@12669.4]
+  input         io_wr_en, // @[:@12669.4]
+  input         io_cs // @[:@12669.4]
+);
+  reg [31:0] imem [0:2047]; // @[imemory.scala 26:25:@12671.4]
+  reg [31:0] _RAND_0;
+  wire [31:0] imem__T_37_data; // @[imemory.scala 26:25:@12671.4]
+  wire [10:0] imem__T_37_addr; // @[imemory.scala 26:25:@12671.4]
+  wire [31:0] imem__T_36_data; // @[imemory.scala 26:25:@12671.4]
+  wire [10:0] imem__T_36_addr; // @[imemory.scala 26:25:@12671.4]
+  wire  imem__T_36_mask; // @[imemory.scala 26:25:@12671.4]
+  wire  imem__T_36_en; // @[imemory.scala 26:25:@12671.4]
+  wire  _GEN_3; // @[imemory.scala 41:17:@12674.4]
+  wire [10:0] _GEN_6;
+  reg [10:0] imem__T_37_addr_pipe_0;
+  reg [31:0] _RAND_1;
+  assign imem__T_37_addr = imem__T_37_addr_pipe_0;
+  assign imem__T_37_data = imem[imem__T_37_addr]; // @[imemory.scala 26:25:@12671.4]
+  assign imem__T_36_data = io_wdata;
+  assign imem__T_36_addr = {{2'd0}, io_addr};
+  assign imem__T_36_mask = 1'h1;
+  assign imem__T_36_en = io_wr_en & io_cs;
+  assign _GEN_3 = 1'h1; // @[imemory.scala 41:17:@12674.4]
+  assign io_rdata = imem__T_37_data; // @[imemory.scala 45:12:@12679.4]
+  assign _GEN_6 = {{2'd0}, io_addr};
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE
+  integer initvar;
+  initial begin
+    `ifdef INIT_RANDOM
+      `INIT_RANDOM
+    `endif
+    `ifndef VERILATOR
+      #0.002 begin end
+    `endif
+  _RAND_0 = {1{`RANDOM}};
+  `ifdef RANDOMIZE_MEM_INIT
+  for (initvar = 0; initvar < 2048; initvar = initvar+1)
+    imem[initvar] = _RAND_0[31:0];
+  `endif // RANDOMIZE_MEM_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_1 = {1{`RANDOM}};
+  imem__T_37_addr_pipe_0 = _RAND_1[10:0];
+  `endif // RANDOMIZE_REG_INIT
+  end
+`endif // RANDOMIZE
+  always @(posedge clock) begin
+    if(imem__T_36_en & imem__T_36_mask) begin
+      imem[imem__T_36_addr] <= imem__T_36_data; // @[imemory.scala 26:25:@12671.4]
+    end
+    if (_GEN_3) begin
+      imem__T_37_addr_pipe_0 <= _GEN_6;
+    end
+  end
+endmodule
\ No newline at end of file
diff --git a/verilog/rtl/Processor_Tile.v b/verilog/rtl/Processor_Tile.v
new file mode 100644
index 0000000..6bc19e4
--- /dev/null
+++ b/verilog/rtl/Processor_Tile.v
@@ -0,0 +1,244 @@
+module Processor_Tile( // @[:@12742.2]
+  input   clock, // @[:@12743.4]
+  input   reset, // @[:@12744.4]
+  output  io_uart_tx, // @[:@12745.4]
+  input   io_uart_rx, // @[:@12745.4]
+  output  io_spi_cs, // @[:@12745.4]
+  output  io_spi_clk, // @[:@12745.4]
+  output  io_spi_mosi, // @[:@12745.4]
+  input   io_spi_miso, // @[:@12745.4]
+  input   io_qei_ch_a, // @[:@12745.4]
+  input   io_qei_ch_b, // @[:@12745.4]
+  output  io_pwm_high, // @[:@12745.4]
+  output  io_pwm_low // @[:@12745.4]
+);
+  wire  core_clock; // @[processor_tile.scala 52:32:@12747.4]
+  wire  core_reset; // @[processor_tile.scala 52:32:@12747.4]
+  wire  core_io_irq_uart_irq; // @[processor_tile.scala 52:32:@12747.4]
+  wire  core_io_irq_spi_irq; // @[processor_tile.scala 52:32:@12747.4]
+  wire  core_io_irq_motor_irq; // @[processor_tile.scala 52:32:@12747.4]
+  wire [31:0] core_io_ibus_addr; // @[processor_tile.scala 52:32:@12747.4]
+  wire [31:0] core_io_ibus_inst; // @[processor_tile.scala 52:32:@12747.4]
+  wire  core_io_ibus_valid; // @[processor_tile.scala 52:32:@12747.4]
+  wire [31:0] core_io_dbus_addr; // @[processor_tile.scala 52:32:@12747.4]
+  wire [31:0] core_io_dbus_wdata; // @[processor_tile.scala 52:32:@12747.4]
+  wire [31:0] core_io_dbus_rdata; // @[processor_tile.scala 52:32:@12747.4]
+  wire  core_io_dbus_rd_en; // @[processor_tile.scala 52:32:@12747.4]
+  wire  core_io_dbus_wr_en; // @[processor_tile.scala 52:32:@12747.4]
+  wire [1:0] core_io_dbus_st_type; // @[processor_tile.scala 52:32:@12747.4]
+  wire [2:0] core_io_dbus_ld_type; // @[processor_tile.scala 52:32:@12747.4]
+  wire  core_io_dbus_valid; // @[processor_tile.scala 52:32:@12747.4]
+  wire  wb_inter_connect_clock; // @[processor_tile.scala 53:32:@12750.4]
+  wire  wb_inter_connect_reset; // @[processor_tile.scala 53:32:@12750.4]
+  wire [31:0] wb_inter_connect_io_dbus_addr; // @[processor_tile.scala 53:32:@12750.4]
+  wire [31:0] wb_inter_connect_io_dbus_wdata; // @[processor_tile.scala 53:32:@12750.4]
+  wire [31:0] wb_inter_connect_io_dbus_rdata; // @[processor_tile.scala 53:32:@12750.4]
+  wire  wb_inter_connect_io_dbus_rd_en; // @[processor_tile.scala 53:32:@12750.4]
+  wire  wb_inter_connect_io_dbus_wr_en; // @[processor_tile.scala 53:32:@12750.4]
+  wire [1:0] wb_inter_connect_io_dbus_st_type; // @[processor_tile.scala 53:32:@12750.4]
+  wire [2:0] wb_inter_connect_io_dbus_ld_type; // @[processor_tile.scala 53:32:@12750.4]
+  wire  wb_inter_connect_io_dbus_valid; // @[processor_tile.scala 53:32:@12750.4]
+  wire [31:0] wb_inter_connect_io_ibus_addr; // @[processor_tile.scala 53:32:@12750.4]
+  wire [31:0] wb_inter_connect_io_ibus_inst; // @[processor_tile.scala 53:32:@12750.4]
+  wire  wb_inter_connect_io_ibus_valid; // @[processor_tile.scala 53:32:@12750.4]
+  wire [8:0] wb_inter_connect_io_imem_io_addr; // @[processor_tile.scala 53:32:@12750.4]
+  wire [31:0] wb_inter_connect_io_imem_io_rdata; // @[processor_tile.scala 53:32:@12750.4]
+  wire [31:0] wb_inter_connect_io_imem_io_wdata; // @[processor_tile.scala 53:32:@12750.4]
+  wire  wb_inter_connect_io_imem_io_wr_en; // @[processor_tile.scala 53:32:@12750.4]
+  wire  wb_inter_connect_io_imem_io_cs; // @[processor_tile.scala 53:32:@12750.4]
+  wire [7:0] wb_inter_connect_io_dmem_io_addr; // @[processor_tile.scala 53:32:@12750.4]
+  wire [31:0] wb_inter_connect_io_dmem_io_wdata; // @[processor_tile.scala 53:32:@12750.4]
+  wire [31:0] wb_inter_connect_io_dmem_io_rdata; // @[processor_tile.scala 53:32:@12750.4]
+  wire  wb_inter_connect_io_dmem_io_cs; // @[processor_tile.scala 53:32:@12750.4]
+  wire  wb_inter_connect_io_dmem_io_wr_en; // @[processor_tile.scala 53:32:@12750.4]
+  wire [3:0] wb_inter_connect_io_dmem_io_st_type; // @[processor_tile.scala 53:32:@12750.4]
+  wire [15:0] wb_inter_connect_io_wbm_m2s_addr; // @[processor_tile.scala 53:32:@12750.4]
+  wire [31:0] wb_inter_connect_io_wbm_m2s_data; // @[processor_tile.scala 53:32:@12750.4]
+  wire  wb_inter_connect_io_wbm_m2s_we; // @[processor_tile.scala 53:32:@12750.4]
+  wire [3:0] wb_inter_connect_io_wbm_m2s_sel; // @[processor_tile.scala 53:32:@12750.4]
+  wire  wb_inter_connect_io_wbm_m2s_stb; // @[processor_tile.scala 53:32:@12750.4]
+  wire  wb_inter_connect_io_uart_tx; // @[processor_tile.scala 53:32:@12750.4]
+  wire  wb_inter_connect_io_uart_rx; // @[processor_tile.scala 53:32:@12750.4]
+  wire  wb_inter_connect_io_uart_irq; // @[processor_tile.scala 53:32:@12750.4]
+  wire  wb_inter_connect_io_spi_cs; // @[processor_tile.scala 53:32:@12750.4]
+  wire  wb_inter_connect_io_spi_clk; // @[processor_tile.scala 53:32:@12750.4]
+  wire  wb_inter_connect_io_spi_mosi; // @[processor_tile.scala 53:32:@12750.4]
+  wire  wb_inter_connect_io_spi_miso; // @[processor_tile.scala 53:32:@12750.4]
+  wire  wb_inter_connect_io_spi_irq; // @[processor_tile.scala 53:32:@12750.4]
+  wire  wb_inter_connect_io_motor_ack_i; // @[processor_tile.scala 53:32:@12750.4]
+  wire [31:0] wb_inter_connect_io_motor_data_i; // @[processor_tile.scala 53:32:@12750.4]
+  wire  wb_inter_connect_io_motor_addr_sel; // @[processor_tile.scala 53:32:@12750.4]
+  wire  motor_clock; // @[processor_tile.scala 55:32:@12753.4]
+  wire  motor_reset; // @[processor_tile.scala 55:32:@12753.4]
+  wire [15:0] motor_io_wbs_m2s_addr; // @[processor_tile.scala 55:32:@12753.4]
+  wire [31:0] motor_io_wbs_m2s_data; // @[processor_tile.scala 55:32:@12753.4]
+  wire  motor_io_wbs_m2s_we; // @[processor_tile.scala 55:32:@12753.4]
+  wire [3:0] motor_io_wbs_m2s_sel; // @[processor_tile.scala 55:32:@12753.4]
+  wire  motor_io_wbs_m2s_stb; // @[processor_tile.scala 55:32:@12753.4]
+  wire  motor_io_wbs_ack_o; // @[processor_tile.scala 55:32:@12753.4]
+  wire [31:0] motor_io_wbs_data_o; // @[processor_tile.scala 55:32:@12753.4]
+  wire  motor_io_ba_match; // @[processor_tile.scala 55:32:@12753.4]
+  wire  motor_io_motor_irq; // @[processor_tile.scala 55:32:@12753.4]
+  wire  motor_io_qei_ch_a; // @[processor_tile.scala 55:32:@12753.4]
+  wire  motor_io_qei_ch_b; // @[processor_tile.scala 55:32:@12753.4]
+  wire  motor_io_pwm_high; // @[processor_tile.scala 55:32:@12753.4]
+  wire  motor_io_pwm_low; // @[processor_tile.scala 55:32:@12753.4]
+  wire  imem_clock; // @[processor_tile.scala 56:32:@12756.4]
+  wire [8:0] imem_io_addr; // @[processor_tile.scala 56:32:@12756.4]
+  wire [31:0] imem_io_rdata; // @[processor_tile.scala 56:32:@12756.4]
+  wire [31:0] imem_io_wdata; // @[processor_tile.scala 56:32:@12756.4]
+  wire  imem_io_wr_en; // @[processor_tile.scala 56:32:@12756.4]
+  wire  imem_io_cs; // @[processor_tile.scala 56:32:@12756.4]
+  wire  dmem_clock; // @[processor_tile.scala 57:32:@12759.4]
+  wire [7:0] dmem_io_addr; // @[processor_tile.scala 57:32:@12759.4]
+  wire [31:0] dmem_io_wdata; // @[processor_tile.scala 57:32:@12759.4]
+  wire [31:0] dmem_io_rdata; // @[processor_tile.scala 57:32:@12759.4]
+  wire  dmem_io_cs; // @[processor_tile.scala 57:32:@12759.4]
+  wire  dmem_io_wr_en; // @[processor_tile.scala 57:32:@12759.4]
+  wire [3:0] dmem_io_st_type; // @[processor_tile.scala 57:32:@12759.4]
+  Core core ( // @[processor_tile.scala 52:32:@12747.4]
+    .clock(core_clock),
+    .reset(core_reset),
+    .io_irq_uart_irq(core_io_irq_uart_irq),
+    .io_irq_spi_irq(core_io_irq_spi_irq),
+    .io_irq_motor_irq(core_io_irq_motor_irq),
+    .io_ibus_addr(core_io_ibus_addr),
+    .io_ibus_inst(core_io_ibus_inst),
+    .io_ibus_valid(core_io_ibus_valid),
+    .io_dbus_addr(core_io_dbus_addr),
+    .io_dbus_wdata(core_io_dbus_wdata),
+    .io_dbus_rdata(core_io_dbus_rdata),
+    .io_dbus_rd_en(core_io_dbus_rd_en),
+    .io_dbus_wr_en(core_io_dbus_wr_en),
+    .io_dbus_st_type(core_io_dbus_st_type),
+    .io_dbus_ld_type(core_io_dbus_ld_type),
+    .io_dbus_valid(core_io_dbus_valid)
+  );
+  WB_InterConnect wb_inter_connect ( // @[processor_tile.scala 53:32:@12750.4]
+    .clock(wb_inter_connect_clock),
+    .reset(wb_inter_connect_reset),
+    .io_dbus_addr(wb_inter_connect_io_dbus_addr),
+    .io_dbus_wdata(wb_inter_connect_io_dbus_wdata),
+    .io_dbus_rdata(wb_inter_connect_io_dbus_rdata),
+    .io_dbus_rd_en(wb_inter_connect_io_dbus_rd_en),
+    .io_dbus_wr_en(wb_inter_connect_io_dbus_wr_en),
+    .io_dbus_st_type(wb_inter_connect_io_dbus_st_type),
+    .io_dbus_ld_type(wb_inter_connect_io_dbus_ld_type),
+    .io_dbus_valid(wb_inter_connect_io_dbus_valid),
+    .io_ibus_addr(wb_inter_connect_io_ibus_addr),
+    .io_ibus_inst(wb_inter_connect_io_ibus_inst),
+    .io_ibus_valid(wb_inter_connect_io_ibus_valid),
+    .io_imem_io_addr(wb_inter_connect_io_imem_io_addr),
+    .io_imem_io_rdata(wb_inter_connect_io_imem_io_rdata),
+    .io_imem_io_wdata(wb_inter_connect_io_imem_io_wdata),
+    .io_imem_io_wr_en(wb_inter_connect_io_imem_io_wr_en),
+    .io_imem_io_cs(wb_inter_connect_io_imem_io_cs),
+    .io_dmem_io_addr(wb_inter_connect_io_dmem_io_addr),
+    .io_dmem_io_wdata(wb_inter_connect_io_dmem_io_wdata),
+    .io_dmem_io_rdata(wb_inter_connect_io_dmem_io_rdata),
+    .io_dmem_io_cs(wb_inter_connect_io_dmem_io_cs),
+    .io_dmem_io_wr_en(wb_inter_connect_io_dmem_io_wr_en),
+    .io_dmem_io_st_type(wb_inter_connect_io_dmem_io_st_type),
+    .io_wbm_m2s_addr(wb_inter_connect_io_wbm_m2s_addr),
+    .io_wbm_m2s_data(wb_inter_connect_io_wbm_m2s_data),
+    .io_wbm_m2s_we(wb_inter_connect_io_wbm_m2s_we),
+    .io_wbm_m2s_sel(wb_inter_connect_io_wbm_m2s_sel),
+    .io_wbm_m2s_stb(wb_inter_connect_io_wbm_m2s_stb),
+    .io_uart_tx(wb_inter_connect_io_uart_tx),
+    .io_uart_rx(wb_inter_connect_io_uart_rx),
+    .io_uart_irq(wb_inter_connect_io_uart_irq),
+    .io_spi_cs(wb_inter_connect_io_spi_cs),
+    .io_spi_clk(wb_inter_connect_io_spi_clk),
+    .io_spi_mosi(wb_inter_connect_io_spi_mosi),
+    .io_spi_miso(wb_inter_connect_io_spi_miso),
+    .io_spi_irq(wb_inter_connect_io_spi_irq),
+    .io_motor_ack_i(wb_inter_connect_io_motor_ack_i),
+    .io_motor_data_i(wb_inter_connect_io_motor_data_i),
+    .io_motor_addr_sel(wb_inter_connect_io_motor_addr_sel)
+  );
+  Motor_Top motor ( // @[processor_tile.scala 55:32:@12753.4]
+    .clock(motor_clock),
+    .reset(motor_reset),
+    .io_wbs_m2s_addr(motor_io_wbs_m2s_addr),
+    .io_wbs_m2s_data(motor_io_wbs_m2s_data),
+    .io_wbs_m2s_we(motor_io_wbs_m2s_we),
+    .io_wbs_m2s_sel(motor_io_wbs_m2s_sel),
+    .io_wbs_m2s_stb(motor_io_wbs_m2s_stb),
+    .io_wbs_ack_o(motor_io_wbs_ack_o),
+    .io_wbs_data_o(motor_io_wbs_data_o),
+    .io_ba_match(motor_io_ba_match),
+    .io_motor_irq(motor_io_motor_irq),
+    .io_qei_ch_a(motor_io_qei_ch_a),
+    .io_qei_ch_b(motor_io_qei_ch_b),
+    .io_pwm_high(motor_io_pwm_high),
+    .io_pwm_low(motor_io_pwm_low)
+  );
+  IMem imem ( // @[processor_tile.scala 56:32:@12756.4]
+    .clock(imem_clock),
+    .io_addr(imem_io_addr),
+    .io_rdata(imem_io_rdata),
+    .io_wdata(imem_io_wdata),
+    .io_wr_en(imem_io_wr_en),
+    .io_cs(imem_io_cs)
+  );
+  DMem dmem ( // @[processor_tile.scala 57:32:@12759.4]
+    .clock(dmem_clock),
+    .io_addr(dmem_io_addr),
+    .io_wdata(dmem_io_wdata),
+    .io_rdata(dmem_io_rdata),
+    .io_cs(dmem_io_cs),
+    .io_wr_en(dmem_io_wr_en),
+    .io_st_type(dmem_io_st_type)
+  );
+  assign io_uart_tx = wb_inter_connect_io_uart_tx; // @[processor_tile.scala 69:32:@12791.4]
+  assign io_spi_cs = wb_inter_connect_io_spi_cs; // @[processor_tile.scala 74:32:@12794.4]
+  assign io_spi_clk = wb_inter_connect_io_spi_clk; // @[processor_tile.scala 75:32:@12795.4]
+  assign io_spi_mosi = wb_inter_connect_io_spi_mosi; // @[processor_tile.scala 76:32:@12796.4]
+  assign io_pwm_high = motor_io_pwm_high; // @[processor_tile.scala 95:24:@12810.4]
+  assign io_pwm_low = motor_io_pwm_low; // @[processor_tile.scala 96:24:@12811.4]
+  assign core_clock = clock; // @[:@12748.4]
+  assign core_reset = reset; // @[:@12749.4]
+  assign core_io_irq_uart_irq = wb_inter_connect_io_uart_irq; // @[processor_tile.scala 71:32:@12793.4]
+  assign core_io_irq_spi_irq = wb_inter_connect_io_spi_irq; // @[processor_tile.scala 78:32:@12798.4]
+  assign core_io_irq_motor_irq = motor_io_motor_irq; // @[processor_tile.scala 97:25:@12812.4]
+  assign core_io_ibus_inst = wb_inter_connect_io_ibus_inst; // @[processor_tile.scala 65:24:@12781.4]
+  assign core_io_ibus_valid = wb_inter_connect_io_ibus_valid; // @[processor_tile.scala 65:24:@12780.4]
+  assign core_io_dbus_rdata = wb_inter_connect_io_dbus_rdata; // @[processor_tile.scala 66:24:@12788.4]
+  assign core_io_dbus_valid = wb_inter_connect_io_dbus_valid; // @[processor_tile.scala 66:24:@12783.4]
+  assign wb_inter_connect_clock = clock; // @[:@12751.4]
+  assign wb_inter_connect_reset = reset; // @[:@12752.4]
+  assign wb_inter_connect_io_dbus_addr = core_io_dbus_addr; // @[processor_tile.scala 66:24:@12790.4]
+  assign wb_inter_connect_io_dbus_wdata = core_io_dbus_wdata; // @[processor_tile.scala 66:24:@12789.4]
+  assign wb_inter_connect_io_dbus_rd_en = core_io_dbus_rd_en; // @[processor_tile.scala 66:24:@12787.4]
+  assign wb_inter_connect_io_dbus_wr_en = core_io_dbus_wr_en; // @[processor_tile.scala 66:24:@12786.4]
+  assign wb_inter_connect_io_dbus_st_type = core_io_dbus_st_type; // @[processor_tile.scala 66:24:@12785.4]
+  assign wb_inter_connect_io_dbus_ld_type = core_io_dbus_ld_type; // @[processor_tile.scala 66:24:@12784.4]
+  assign wb_inter_connect_io_ibus_addr = core_io_ibus_addr; // @[processor_tile.scala 65:24:@12782.4]
+  assign wb_inter_connect_io_imem_io_rdata = imem_io_rdata; // @[processor_tile.scala 60:11:@12769.4]
+  assign wb_inter_connect_io_dmem_io_rdata = dmem_io_rdata; // @[processor_tile.scala 61:11:@12777.4]
+  assign wb_inter_connect_io_uart_rx = io_uart_rx; // @[processor_tile.scala 70:32:@12792.4]
+  assign wb_inter_connect_io_spi_miso = io_spi_miso; // @[processor_tile.scala 77:32:@12797.4]
+  assign wb_inter_connect_io_motor_ack_i = motor_io_wbs_ack_o; // @[processor_tile.scala 90:35:@12806.4]
+  assign wb_inter_connect_io_motor_data_i = motor_io_wbs_data_o; // @[processor_tile.scala 89:36:@12805.4]
+  assign motor_clock = clock; // @[:@12754.4]
+  assign motor_reset = reset; // @[:@12755.4]
+  assign motor_io_wbs_m2s_addr = wb_inter_connect_io_wbm_m2s_addr; // @[processor_tile.scala 88:28:@12804.4]
+  assign motor_io_wbs_m2s_data = wb_inter_connect_io_wbm_m2s_data; // @[processor_tile.scala 88:28:@12803.4]
+  assign motor_io_wbs_m2s_we = wb_inter_connect_io_wbm_m2s_we; // @[processor_tile.scala 88:28:@12802.4]
+  assign motor_io_wbs_m2s_sel = wb_inter_connect_io_wbm_m2s_sel; // @[processor_tile.scala 88:28:@12801.4]
+  assign motor_io_wbs_m2s_stb = wb_inter_connect_io_wbm_m2s_stb; // @[processor_tile.scala 88:28:@12800.4]
+  assign motor_io_ba_match = wb_inter_connect_io_motor_addr_sel; // @[processor_tile.scala 92:24:@12807.4]
+  assign motor_io_qei_ch_a = io_qei_ch_a; // @[processor_tile.scala 93:24:@12808.4]
+  assign motor_io_qei_ch_b = io_qei_ch_b; // @[processor_tile.scala 94:24:@12809.4]
+  assign imem_clock = clock; // @[:@12757.4]
+  assign imem_io_addr = wb_inter_connect_io_imem_io_addr; // @[processor_tile.scala 60:11:@12770.4]
+  assign imem_io_wdata = wb_inter_connect_io_imem_io_wdata; // @[processor_tile.scala 60:11:@12768.4]
+  assign imem_io_wr_en = wb_inter_connect_io_imem_io_wr_en; // @[processor_tile.scala 60:11:@12767.4]
+  assign imem_io_cs = wb_inter_connect_io_imem_io_cs; // @[processor_tile.scala 60:11:@12766.4]
+  assign dmem_clock = clock; // @[:@12760.4]
+  assign dmem_io_addr = wb_inter_connect_io_dmem_io_addr; // @[processor_tile.scala 61:11:@12779.4]
+  assign dmem_io_wdata = wb_inter_connect_io_dmem_io_wdata; // @[processor_tile.scala 61:11:@12778.4]
+  assign dmem_io_cs = wb_inter_connect_io_dmem_io_cs; // @[processor_tile.scala 61:11:@12776.4]
+  assign dmem_io_wr_en = wb_inter_connect_io_dmem_io_wr_en; // @[processor_tile.scala 61:11:@12775.4]
+  assign dmem_io_st_type = wb_inter_connect_io_dmem_io_st_type; // @[processor_tile.scala 61:11:@12774.4]
+endmodule