diff --git a/openlane/user_project_wrapper/config.json b/openlane/user_project_wrapper/config.json
deleted file mode 100644
index d83d5bb..0000000
--- a/openlane/user_project_wrapper/config.json
+++ /dev/null
@@ -1,58 +0,0 @@
-{
-    "PDK"                             : "sky130A",
-    "STD_CELL_LIBRARY"                : "sky130_fd_sc_hd",
-    "CARAVEL_ROOT"                    : "../../caravel",
-    "CLOCK_NET"                       : "mprj.clk",
-    "CLOCK_PERIOD"                    : "10",
-    "CLOCK_PORT"                      : "user_clock2",
-    "CLOCK_TREE_SYNTH"                : "0",
-    "DESIGN_NAME"                     : "user_project_wrapper",
-    "DIE_AREA"                        : "0 0 2920 3520",
-    "DIODE_INSERTION_STRATEGY"        : "0",
-    "EXTRA_GDS_FILES"                 : "../../gds/user_proj_example.gds",
-    "EXTRA_LEFS"                      : "../../lef/user_proj_example.lef",
-    "FILL_INSERTION"                  : "0",
-    "FP_IO_HEXTEND"                   : "4.8",
-    "FP_IO_HLENGTH"                   : "2.4",
-    "FP_IO_HTHICKNESS_MULT"           : "4",
-    "FP_IO_VEXTEND"                   : "4.8",
-    "FP_IO_VLENGTH"                   : "2.4",
-    "FP_IO_VTHICKNESS_MULT"           : "4",
-    "FP_PDN_CHECK_NODES"              : "0",
-    "FP_PDN_CORE_RING"                : "1",
-    "FP_PDN_CORE_RING_HOFFSET"        : "14",
-    "FP_PDN_CORE_RING_HSPACING"       : "1.7",
-    "FP_PDN_CORE_RING_HWIDTH"         : "3.1",
-    "FP_PDN_CORE_RING_VOFFSET"        : "14",
-    "FP_PDN_CORE_RING_VSPACING"       : "1.7",
-    "FP_PDN_CORE_RING_VWIDTH"         : "3.1",
-    "FP_PDN_ENABLE_RAILS"             : "0",
-    "FP_PDN_HOFFSET"                  : "5",
-    "FP_PDN_HPITCH"                   : "180",
-    "FP_PDN_HSPACING"                 : "15.5",
-    "FP_PDN_HWIDTH"                   : "3.1",
-    "FP_PDN_MACRO_HOOKS"              : "mprj vccd1 vssd1",
-    "FP_PDN_VOFFSET"                  : "5",
-    "FP_PDN_VPITCH"                   : "180",
-    "FP_PDN_VSPACING"                 : "15.5",
-    "FP_PDN_VWIDTH"                   : "3.1",
-    "FP_PIN_ORDER_CFG"                : "../../caravel/openlane/user_project_wrapper_empty/pin_order.cfg",
-    "FP_SIZING"                       : "absolute",
-    "GLB_RT_MAXLAYER"                 : "5",
-    "GND_NETS"                        : "vssd1 vssd2 vssa1 vssa2",
-    "MACRO_PLACEMENT_CFG"             : "macro.cfg",
-    "MAGIC_ZEROIZE_ORIGIN"            : "0",
-    "PL_RANDOM_GLB_PLACEMENT"         : "1",
-    "PL_RESIZER_BUFFER_INPUT_PORTS"   : "0",
-    "PL_RESIZER_BUFFER_OUTPUT_PORTS"  : "0",
-    "PL_RESIZER_DESIGN_OPTIMIZATIONS" : "0",
-    "PL_RESIZER_TIMING_OPTIMIZATIONS" : "0",
-    "RUN_CVC"                         : "0",
-    "SYNTH_TOP_LEVEL"                 : "1",
-    "SYNTH_USE_PG_PINS_DEFINES"       : "USE_POWER_PINS",
-    "TAP_DECAP_INSERTION"             : "0",
-    "VDD_NETS"                        : "vccd1 vccd2 vdda1 vdda2",
-    "VERILOG_FILES"                   : ["../../caravel/verilog/rtl/defines.v","../../verilog/rtl/user_project_wrapper.v"],  
-    "VERILOG_FILES_BLACKBOX"          : ["../../caravel/verilog/rtl/defines.v","../../verilog/rtl/user_proj_example.v"]  
-}
-
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index f720e39..39ef114 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -27,7 +27,7 @@
 
 set script_dir [file dirname [file normalize [info script]]]
 
-set ::env(DESIGN_NAME) user_project_wrapper
+set ::env(DESIGN_NAME) WB_InterConnect
 #section end
 
 # User Configurations
@@ -35,18 +35,14 @@
 ## Source Verilog Files
 set ::env(VERILOG_FILES) "\
 	$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
-	$script_dir/../../verilog/rtl/user_project_wrapper.v"
+	$script_dir/../../verilog/rtl/WB_Interconnect.v"
 
 ## Clock configurations
-set ::env(CLOCK_PORT) "user_clock2"
-set ::env(CLOCK_NET) "mprj.clk"
+set ::env(CLOCK_PORT) "clock"
 
-set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PERIOD) "20"
 
 ## Internal Macros
-### Macro PDN Connections
-set ::env(FP_PDN_MACRO_HOOKS) "\
-	mprj vccd1 vssd1"
 
 ### Macro Placement
 set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro.cfg
@@ -54,33 +50,16 @@
 ### Black-box verilog and views
 set ::env(VERILOG_FILES_BLACKBOX) "\
 	$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
-	$script_dir/../../verilog/rtl/user_proj_example.v"
+	$script_dir/../../verilog/rtl/UART.v"
 
 set ::env(EXTRA_LEFS) "\
-	$script_dir/../../lef/user_proj_example.lef"
+	$script_dir/../../lef/UART.lef"
 
 set ::env(EXTRA_GDS_FILES) "\
-	$script_dir/../../gds/user_proj_example.gds"
+	$script_dir/../../gds/UART.gds"
 
 # set ::env(GLB_RT_MAXLAYER) 5
 set ::env(RT_MAX_LAYER) {met4}
 
 # disable pdn check nodes becuase it hangs with multiple power domains.
 # any issue with pdn connections will be flagged with LVS so it is not a critical check.
-set ::env(FP_PDN_CHECK_NODES) 0
-
-# The following is because there are no std cells in the example wrapper project.
-set ::env(SYNTH_TOP_LEVEL) 1
-set ::env(PL_RANDOM_GLB_PLACEMENT) 1
-
-set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
-set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
-set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 0
-set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0
-
-set ::env(FP_PDN_ENABLE_RAILS) 0
-
-set ::env(DIODE_INSERTION_STRATEGY) 0
-set ::env(FILL_INSERTION) 0
-set ::env(TAP_DECAP_INSERTION) 0
-set ::env(CLOCK_TREE_SYNTH) 0
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index a7365ab..a5e558b 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1 +1 @@
-mprj 1175 1690 N
+uart 1175 1690 N
diff --git a/verilog/rtl/WB_Interconnect.v b/verilog/rtl/WB_Interconnect.v
index ea76e46..277b8f5 100644
--- a/verilog/rtl/WB_Interconnect.v
+++ b/verilog/rtl/WB_Interconnect.v
@@ -127,48 +127,7 @@
   wire  _T_71; // @[wb_interconnect.scala 117:39:@12660.4]
   wire  _T_72; // @[wb_interconnect.scala 116:37:@12661.4]
   wire  _T_73; // @[wb_interconnect.scala 115:35:@12662.4]
-  DMem_Interface dmem ( // @[wb_interconnect.scala 61:24:@12573.4]
-    .clock(dmem_clock),
-    .reset(dmem_reset),
-    .io_wbs_m2s_addr(dmem_io_wbs_m2s_addr),
-    .io_wbs_m2s_data(dmem_io_wbs_m2s_data),
-    .io_wbs_m2s_we(dmem_io_wbs_m2s_we),
-    .io_wbs_m2s_sel(dmem_io_wbs_m2s_sel),
-    .io_wbs_m2s_stb(dmem_io_wbs_m2s_stb),
-    .io_wbs_ack_o(dmem_io_wbs_ack_o),
-    .io_wbs_data_o(dmem_io_wbs_data_o)
-  );
-  IMem_Interface imem ( // @[wb_interconnect.scala 62:24:@12576.4]
-    .clock(imem_clock),
-    .reset(imem_reset),
-    .io_ibus_addr(imem_io_ibus_addr),
-    .io_ibus_inst(imem_io_ibus_inst),
-    .io_ibus_valid(imem_io_ibus_valid),
-    .io_wbs_m2s_addr(imem_io_wbs_m2s_addr),
-    .io_wbs_m2s_data(imem_io_wbs_m2s_data),
-    .io_wbs_m2s_we(imem_io_wbs_m2s_we),
-    .io_wbs_m2s_sel(imem_io_wbs_m2s_sel),
-    .io_wbs_m2s_stb(imem_io_wbs_m2s_stb),
-    .io_wbs_ack_o(imem_io_wbs_ack_o),
-    .io_wbs_data_o(imem_io_wbs_data_o)
-  );
-  WBM_DBus wbm_dbus ( // @[wb_interconnect.scala 63:24:@12579.4]
-    .io_dbus_addr(wbm_dbus_io_dbus_addr),
-    .io_dbus_wdata(wbm_dbus_io_dbus_wdata),
-    .io_dbus_rdata(wbm_dbus_io_dbus_rdata),
-    .io_dbus_rd_en(wbm_dbus_io_dbus_rd_en),
-    .io_dbus_wr_en(wbm_dbus_io_dbus_wr_en),
-    .io_dbus_st_type(wbm_dbus_io_dbus_st_type),
-    .io_dbus_ld_type(wbm_dbus_io_dbus_ld_type),
-    .io_dbus_valid(wbm_dbus_io_dbus_valid),
-    .io_wbm_m2s_addr(wbm_dbus_io_wbm_m2s_addr),
-    .io_wbm_m2s_data(wbm_dbus_io_wbm_m2s_data),
-    .io_wbm_m2s_we(wbm_dbus_io_wbm_m2s_we),
-    .io_wbm_m2s_sel(wbm_dbus_io_wbm_m2s_sel),
-    .io_wbm_m2s_stb(wbm_dbus_io_wbm_m2s_stb),
-    .io_wbm_ack_i(wbm_dbus_io_wbm_ack_i),
-    .io_wbm_data_i(wbm_dbus_io_wbm_data_i)
-  );
+
   UART uart ( // @[wb_interconnect.scala 64:24:@12582.4]
     .clock(uart_clock),
     .reset(uart_reset),
@@ -183,39 +142,8 @@
     .io_wbs_ack_o(uart_io_wbs_ack_o),
     .io_wbs_data_o(uart_io_wbs_data_o)
   );
-  SPI spi ( // @[wb_interconnect.scala 65:24:@12585.4]
-    .clock(spi_clock),
-    .reset(spi_reset),
-    .io_spi_select(spi_io_spi_select),
-    .io_spi_cs(spi_io_spi_cs),
-    .io_spi_clk(spi_io_spi_clk),
-    .io_spi_mosi(spi_io_spi_mosi),
-    .io_spi_miso(spi_io_spi_miso),
-    .io_spi_intr(spi_io_spi_intr),
-    .io_wbs_m2s_addr(spi_io_wbs_m2s_addr),
-    .io_wbs_m2s_data(spi_io_wbs_m2s_data),
-    .io_wbs_m2s_we(spi_io_wbs_m2s_we),
-    .io_wbs_m2s_stb(spi_io_wbs_m2s_stb),
-    .io_wbs_ack_o(spi_io_wbs_ack_o),
-    .io_wbs_data_o(spi_io_wbs_data_o)
-  );
-  Motor_Top motor ( // @[wb_interconnect.scala 66:24:@12588.4]
-    .clock(motor_clock),
-    .reset(motor_reset),
-    .io_wbs_m2s_addr(motor_io_wbs_m2s_addr),
-    .io_wbs_m2s_data(motor_io_wbs_m2s_data),
-    .io_wbs_m2s_we(motor_io_wbs_m2s_we),
-    .io_wbs_m2s_sel(motor_io_wbs_m2s_sel),
-    .io_wbs_m2s_stb(motor_io_wbs_m2s_stb),
-    .io_wbs_ack_o(motor_io_wbs_ack_o),
-    .io_wbs_data_o(motor_io_wbs_data_o),
-    .io_ba_match(motor_io_ba_match),
-    .io_motor_irq(motor_io_motor_irq),
-    .io_qei_ch_a(motor_io_qei_ch_a),
-    .io_qei_ch_b(motor_io_qei_ch_b),
-    .io_pwm_high(motor_io_pwm_high),
-    .io_pwm_low(motor_io_pwm_low)
-  );
+  
+
   assign address = wbm_dbus_io_wbm_m2s_addr[15:12]; // @[wb_interconnect.scala 73:50:@12602.4]
   assign imem_addr_match = address == 4'h0; // @[wb_interconnect.scala 74:35:@12603.4]
   assign dmem_addr_match = address == 4'h1; // @[wb_interconnect.scala 75:35:@12604.4]