diff --git a/verilog/rtl/Core.v b/verilog/rtl/Core.v
new file mode 100644
index 0000000..81d18fb
--- /dev/null
+++ b/verilog/rtl/Core.v
@@ -0,0 +1,3793 @@
+module CSR( // @[:@3.2]
+  input         clock, // @[:@4.4]
+  input         reset, // @[:@5.4]
+  input         io_stall, // @[:@6.4]
+  input  [2:0]  io_cmd, // @[:@6.4]
+  input  [31:0] io_in, // @[:@6.4]
+  output [31:0] io_out, // @[:@6.4]
+  input  [31:0] io_pc, // @[:@6.4]
+  input  [31:0] io_addr, // @[:@6.4]
+  input  [31:0] io_inst, // @[:@6.4]
+  input         io_illegal, // @[:@6.4]
+  input  [1:0]  io_st_type, // @[:@6.4]
+  input  [2:0]  io_ld_type, // @[:@6.4]
+  input         io_pc_check, // @[:@6.4]
+  output        io_expt, // @[:@6.4]
+  output [31:0] io_evec, // @[:@6.4]
+  output [31:0] io_epc, // @[:@6.4]
+  input         io_irq_uart_irq, // @[:@6.4]
+  input         io_irq_spi_irq, // @[:@6.4]
+  input         io_irq_motor_irq, // @[:@6.4]
+  input         io_br_taken // @[:@6.4]
+);
+  wire [11:0] csr_addr; // @[csr.scala 106:27:@8.4]
+  wire [4:0] rs1_addr; // @[csr.scala 107:27:@9.4]
+  reg [31:0] time$; // @[csr.scala 110:27:@10.4]
+  reg [31:0] _RAND_0;
+  reg [31:0] timeh; // @[csr.scala 111:27:@11.4]
+  reg [31:0] _RAND_1;
+  reg [31:0] cycle; // @[csr.scala 112:27:@12.4]
+  reg [31:0] _RAND_2;
+  reg [31:0] cycleh; // @[csr.scala 113:27:@13.4]
+  reg [31:0] _RAND_3;
+  reg [31:0] instret; // @[csr.scala 114:27:@14.4]
+  reg [31:0] _RAND_4;
+  reg [31:0] instreth; // @[csr.scala 115:27:@15.4]
+  reg [31:0] _RAND_5;
+  reg [1:0] mstatus_prv; // @[csr.scala 129:23:@16.4]
+  reg [31:0] _RAND_6;
+  reg [1:0] mstatus_mpp; // @[csr.scala 129:23:@16.4]
+  reg [31:0] _RAND_7;
+  reg  mstatus_mpie; // @[csr.scala 129:23:@16.4]
+  reg [31:0] _RAND_8;
+  reg  mstatus_mie; // @[csr.scala 129:23:@16.4]
+  reg [31:0] _RAND_9;
+  reg  mie_motorie; // @[csr.scala 130:23:@17.4]
+  reg [31:0] _RAND_10;
+  reg  mie_spiie; // @[csr.scala 130:23:@17.4]
+  reg [31:0] _RAND_11;
+  reg  mie_uartie; // @[csr.scala 130:23:@17.4]
+  reg [31:0] _RAND_12;
+  reg  mie_mtie; // @[csr.scala 130:23:@17.4]
+  reg [31:0] _RAND_13;
+  reg  mie_msie; // @[csr.scala 130:23:@17.4]
+  reg [31:0] _RAND_14;
+  reg  mip_motorip; // @[csr.scala 132:27:@19.4]
+  reg [31:0] _RAND_15;
+  reg  mip_spiip; // @[csr.scala 132:27:@19.4]
+  reg [31:0] _RAND_16;
+  reg  mip_uartip; // @[csr.scala 132:27:@19.4]
+  reg [31:0] _RAND_17;
+  reg  mip_mtip; // @[csr.scala 132:27:@19.4]
+  reg [31:0] _RAND_18;
+  reg  mip_msip; // @[csr.scala 132:27:@19.4]
+  reg [31:0] _RAND_19;
+  reg [31:0] mtvec; // @[csr.scala 136:27:@20.4]
+  reg [31:0] _RAND_20;
+  reg [31:0] mscratch; // @[csr.scala 139:23:@21.4]
+  reg [31:0] _RAND_21;
+  reg [31:0] mepc; // @[csr.scala 140:23:@22.4]
+  reg [31:0] _RAND_22;
+  reg [31:0] mcause; // @[csr.scala 141:23:@23.4]
+  reg [31:0] _RAND_23;
+  reg [31:0] mtval; // @[csr.scala 142:23:@24.4]
+  reg [31:0] _RAND_24;
+  wire  _GEN_0; // @[csr.scala 146:3:@26.4]
+  wire  _GEN_1; // @[csr.scala 146:3:@26.4]
+  wire  _GEN_2; // @[csr.scala 146:3:@26.4]
+  wire  _GEN_3; // @[csr.scala 146:3:@26.4]
+  wire [1:0] _GEN_4; // @[csr.scala 146:3:@26.4]
+  wire [1:0] _GEN_5; // @[csr.scala 146:3:@26.4]
+  wire [7:0] _T_147; // @[csr.scala 164:34:@40.4]
+  wire [31:0] _T_156; // @[csr.scala 164:34:@49.4]
+  wire [7:0] _T_163; // @[csr.scala 169:34:@56.4]
+  wire [31:0] _T_172; // @[csr.scala 169:34:@65.4]
+  wire [12:0] _T_182; // @[csr.scala 170:38:@75.4]
+  wire [31:0] _T_193; // @[csr.scala 170:38:@86.4]
+  wire  _T_198; // @[Lookup.scala 9:38:@88.4]
+  wire  _T_202; // @[Lookup.scala 9:38:@90.4]
+  wire  _T_206; // @[Lookup.scala 9:38:@92.4]
+  wire  _T_210; // @[Lookup.scala 9:38:@94.4]
+  wire  _T_214; // @[Lookup.scala 9:38:@96.4]
+  wire  _T_218; // @[Lookup.scala 9:38:@98.4]
+  wire  _T_222; // @[Lookup.scala 9:38:@100.4]
+  wire  _T_226; // @[Lookup.scala 9:38:@102.4]
+  wire  _T_230; // @[Lookup.scala 9:38:@104.4]
+  wire  _T_234; // @[Lookup.scala 9:38:@106.4]
+  wire  _T_238; // @[Lookup.scala 9:38:@108.4]
+  wire  _T_242; // @[Lookup.scala 9:38:@110.4]
+  wire  _T_246; // @[Lookup.scala 9:38:@112.4]
+  wire  _T_250; // @[Lookup.scala 9:38:@114.4]
+  wire  _T_254; // @[Lookup.scala 9:38:@116.4]
+  wire [31:0] _T_255; // @[Lookup.scala 11:37:@117.4]
+  wire [31:0] _T_256; // @[Lookup.scala 11:37:@118.4]
+  wire [31:0] _T_257; // @[Lookup.scala 11:37:@119.4]
+  wire [31:0] _T_258; // @[Lookup.scala 11:37:@120.4]
+  wire [31:0] _T_259; // @[Lookup.scala 11:37:@121.4]
+  wire [31:0] _T_260; // @[Lookup.scala 11:37:@122.4]
+  wire [31:0] _T_261; // @[Lookup.scala 11:37:@123.4]
+  wire [31:0] _T_262; // @[Lookup.scala 11:37:@124.4]
+  wire [31:0] _T_263; // @[Lookup.scala 11:37:@125.4]
+  wire [31:0] _T_264; // @[Lookup.scala 11:37:@126.4]
+  wire [31:0] _T_265; // @[Lookup.scala 11:37:@127.4]
+  wire [31:0] _T_266; // @[Lookup.scala 11:37:@128.4]
+  wire [31:0] _T_267; // @[Lookup.scala 11:37:@129.4]
+  wire [31:0] _T_268; // @[Lookup.scala 11:37:@130.4]
+  wire [1:0] _T_270; // @[csr.scala 178:31:@133.4]
+  wire  privValid; // @[csr.scala 178:38:@134.4]
+  wire  privInst; // @[csr.scala 179:30:@135.4]
+  wire  _T_271; // @[csr.scala 180:44:@136.4]
+  wire  _T_273; // @[csr.scala 180:35:@137.4]
+  wire  _T_274; // @[csr.scala 180:32:@138.4]
+  wire  _T_275; // @[csr.scala 180:60:@139.4]
+  wire  _T_277; // @[csr.scala 180:51:@140.4]
+  wire  isEcall; // @[csr.scala 180:48:@141.4]
+  wire  _T_279; // @[csr.scala 181:32:@143.4]
+  wire  isEbreak; // @[csr.scala 181:48:@146.4]
+  wire  isEret; // @[csr.scala 182:48:@151.4]
+  wire  _T_288; // @[csr.scala 183:45:@152.4]
+  wire  iaddrInvalid; // @[csr.scala 183:35:@153.4]
+  wire [1:0] _T_290; // @[csr.scala 185:49:@154.4]
+  wire  _T_292; // @[csr.scala 185:56:@155.4]
+  wire  _T_293; // @[csr.scala 185:77:@156.4]
+  wire  _T_295; // @[Mux.scala 46:19:@158.4]
+  wire  _T_296; // @[Mux.scala 46:16:@159.4]
+  wire  _T_297; // @[Mux.scala 46:19:@160.4]
+  wire  _T_298; // @[Mux.scala 46:16:@161.4]
+  wire  _T_299; // @[Mux.scala 46:19:@162.4]
+  wire  laddrInvalid; // @[Mux.scala 46:16:@163.4]
+  wire  _T_305; // @[Mux.scala 46:19:@167.4]
+  wire  _T_306; // @[Mux.scala 46:16:@168.4]
+  wire  _T_307; // @[Mux.scala 46:19:@169.4]
+  wire  saddrInvalid; // @[Mux.scala 46:16:@170.4]
+  wire  isMotor; // @[csr.scala 189:36:@171.4]
+  wire  isSpi; // @[csr.scala 190:35:@172.4]
+  wire  isUart; // @[csr.scala 191:36:@173.4]
+  wire  isTimer; // @[csr.scala 192:36:@174.4]
+  wire  isSoftware; // @[csr.scala 194:36:@176.4]
+  wire  _T_368; // @[csr.scala 197:65:@207.4]
+  wire  _T_369; // @[csr.scala 197:65:@208.4]
+  wire  _T_370; // @[csr.scala 197:65:@209.4]
+  wire  _T_371; // @[csr.scala 197:65:@210.4]
+  wire  _T_372; // @[csr.scala 197:65:@211.4]
+  wire  _T_373; // @[csr.scala 197:65:@212.4]
+  wire  _T_374; // @[csr.scala 197:65:@213.4]
+  wire  _T_375; // @[csr.scala 197:65:@214.4]
+  wire  _T_376; // @[csr.scala 197:65:@215.4]
+  wire  _T_377; // @[csr.scala 197:65:@216.4]
+  wire  _T_378; // @[csr.scala 197:65:@217.4]
+  wire  _T_379; // @[csr.scala 197:65:@218.4]
+  wire  _T_380; // @[csr.scala 197:65:@219.4]
+  wire  csrValid; // @[csr.scala 197:65:@220.4]
+  wire [1:0] _T_381; // @[csr.scala 198:31:@221.4]
+  wire [1:0] _T_382; // @[csr.scala 198:40:@222.4]
+  wire  csrRO; // @[csr.scala 198:40:@223.4]
+  wire  _T_384; // @[csr.scala 199:30:@224.4]
+  wire  _T_385; // @[csr.scala 199:49:@225.4]
+  wire  _T_387; // @[csr.scala 199:65:@226.4]
+  wire  _T_388; // @[csr.scala 199:53:@227.4]
+  wire  wen; // @[csr.scala 199:40:@228.4]
+  wire [31:0] _T_390; // @[csr.scala 201:68:@229.4]
+  wire [31:0] _T_391; // @[csr.scala 202:70:@230.4]
+  wire [31:0] _T_392; // @[csr.scala 202:68:@231.4]
+  wire  _T_393; // @[Mux.scala 46:19:@232.4]
+  wire [31:0] _T_394; // @[Mux.scala 46:16:@233.4]
+  wire  _T_395; // @[Mux.scala 46:19:@234.4]
+  wire [31:0] _T_396; // @[Mux.scala 46:16:@235.4]
+  wire  _T_397; // @[Mux.scala 46:19:@236.4]
+  wire [31:0] wdata; // @[Mux.scala 46:16:@237.4]
+  wire [29:0] _GEN_147; // @[csr.scala 208:50:@238.4]
+  wire [30:0] _T_410; // @[csr.scala 208:50:@238.4]
+  wire [29:0] _T_411; // @[csr.scala 208:50:@239.4]
+  wire [29:0] _T_412; // @[csr.scala 209:22:@240.4]
+  wire [29:0] _T_413; // @[csr.scala 208:22:@241.4]
+  wire [29:0] _T_414; // @[csr.scala 207:22:@242.4]
+  wire [29:0] _T_415; // @[csr.scala 206:22:@243.4]
+  wire [29:0] causeExpt; // @[csr.scala 205:22:@244.4]
+  wire [29:0] _T_416; // @[csr.scala 215:22:@245.4]
+  wire [29:0] _T_417; // @[csr.scala 214:22:@246.4]
+  wire [29:0] _T_418; // @[csr.scala 213:22:@247.4]
+  wire [29:0] causeInt; // @[csr.scala 211:22:@249.4]
+  wire  _T_420; // @[csr.scala 218:29:@250.4]
+  wire  _T_421; // @[csr.scala 218:38:@251.4]
+  wire  _T_422; // @[csr.scala 218:48:@252.4]
+  wire  _T_424; // @[csr.scala 218:73:@254.4]
+  wire  isInt; // @[csr.scala 218:88:@255.4]
+  wire [29:0] cause; // @[csr.scala 219:23:@256.4]
+  wire [29:0] _T_425; // @[csr.scala 222:26:@257.4]
+  wire [31:0] _GEN_148; // @[csr.scala 222:31:@258.4]
+  wire [31:0] base; // @[csr.scala 222:31:@258.4]
+  wire [1:0] mode; // @[csr.scala 223:25:@259.4]
+  wire  _T_426; // @[csr.scala 224:38:@260.4]
+  wire  _T_427; // @[csr.scala 224:31:@261.4]
+  wire [31:0] _GEN_149; // @[csr.scala 224:57:@262.4]
+  wire [31:0] _T_428; // @[csr.scala 224:57:@262.4]
+  wire [32:0] _T_429; // @[csr.scala 224:48:@263.4]
+  wire [31:0] _T_430; // @[csr.scala 224:48:@264.4]
+  wire  _T_432; // @[csr.scala 227:33:@267.4]
+  wire  _T_433; // @[csr.scala 227:49:@268.4]
+  wire  _T_434; // @[csr.scala 227:65:@269.4]
+  wire [1:0] _T_435; // @[csr.scala 228:28:@270.4]
+  wire  _T_437; // @[csr.scala 228:35:@271.4]
+  wire  _T_439; // @[csr.scala 228:43:@272.4]
+  wire  _T_441; // @[csr.scala 228:56:@273.4]
+  wire  _T_442; // @[csr.scala 228:53:@274.4]
+  wire  _T_443; // @[csr.scala 228:39:@275.4]
+  wire  _T_444; // @[csr.scala 227:81:@276.4]
+  wire  _T_445; // @[csr.scala 228:75:@277.4]
+  wire  _T_446; // @[csr.scala 228:68:@278.4]
+  wire  _T_449; // @[csr.scala 229:32:@280.4]
+  wire  _T_450; // @[csr.scala 228:84:@281.4]
+  wire  _T_451; // @[csr.scala 229:47:@282.4]
+  wire  _T_452; // @[csr.scala 229:58:@283.4]
+  wire [32:0] _T_455; // @[csr.scala 233:26:@287.4]
+  wire [31:0] _T_456; // @[csr.scala 233:26:@288.4]
+  wire [31:0] _T_457; // @[csr.scala 234:13:@290.4]
+  wire  _T_459; // @[csr.scala 234:13:@291.4]
+  wire [32:0] _T_461; // @[csr.scala 235:27:@293.6]
+  wire [31:0] _T_462; // @[csr.scala 235:27:@294.6]
+  wire [31:0] _GEN_6; // @[csr.scala 234:19:@292.4]
+  wire [32:0] _T_464; // @[csr.scala 237:27:@297.4]
+  wire [31:0] _T_465; // @[csr.scala 237:27:@298.4]
+  wire [31:0] _T_466; // @[csr.scala 238:14:@300.4]
+  wire  _T_468; // @[csr.scala 238:14:@301.4]
+  wire [32:0] _T_470; // @[csr.scala 239:28:@303.6]
+  wire [31:0] _T_471; // @[csr.scala 239:28:@304.6]
+  wire [31:0] _GEN_7; // @[csr.scala 238:20:@302.4]
+  wire  _T_473; // @[csr.scala 241:28:@307.4]
+  wire  _T_475; // @[csr.scala 241:53:@308.4]
+  wire  _T_476; // @[csr.scala 241:62:@309.4]
+  wire  _T_477; // @[csr.scala 241:73:@310.4]
+  wire  _T_478; // @[csr.scala 241:49:@311.4]
+  wire  _T_480; // @[csr.scala 241:89:@312.4]
+  wire  isInstRet; // @[csr.scala 241:86:@313.4]
+  wire [32:0] _T_482; // @[csr.scala 244:29:@315.6]
+  wire [31:0] _T_483; // @[csr.scala 244:29:@316.6]
+  wire [31:0] _GEN_8; // @[csr.scala 243:19:@314.4]
+  wire [31:0] _T_484; // @[csr.scala 246:29:@319.4]
+  wire  _T_486; // @[csr.scala 246:29:@320.4]
+  wire  _T_487; // @[csr.scala 246:18:@321.4]
+  wire [32:0] _T_489; // @[csr.scala 247:30:@323.6]
+  wire [31:0] _T_490; // @[csr.scala 247:30:@324.6]
+  wire [31:0] _GEN_9; // @[csr.scala 246:35:@322.4]
+  reg  wasEret; // @[csr.scala 251:28:@327.4]
+  reg [31:0] _RAND_25;
+  reg  br_taken; // @[csr.scala 255:30:@329.4]
+  reg [31:0] _RAND_26;
+  reg  br_taken_delayed; // @[csr.scala 256:30:@330.4]
+  reg [31:0] _RAND_27;
+  wire  _T_498; // @[csr.scala 265:12:@336.8]
+  wire [32:0] _T_500; // @[csr.scala 266:54:@338.10]
+  wire [32:0] _T_501; // @[csr.scala 266:54:@339.10]
+  wire [31:0] _T_502; // @[csr.scala 266:54:@340.10]
+  wire [31:0] _T_503; // @[csr.scala 266:29:@341.10]
+  wire [29:0] _T_504; // @[csr.scala 266:69:@342.10]
+  wire [31:0] _GEN_150; // @[csr.scala 266:74:@343.10]
+  wire [31:0] _T_505; // @[csr.scala 266:74:@343.10]
+  wire [31:0] _GEN_10; // @[csr.scala 266:7:@337.8]
+  wire [31:0] _T_511; // @[Cat.scala 30:58:@348.8]
+  wire  _T_513; // @[csr.scala 274:25:@354.8]
+  wire  _T_514; // @[csr.scala 274:41:@355.8]
+  wire [31:0] _GEN_11; // @[csr.scala 274:58:@356.8]
+  wire  _T_516; // @[csr.scala 281:21:@369.12]
+  wire [1:0] _T_517; // @[csr.scala 282:30:@371.14]
+  wire  _T_518; // @[csr.scala 283:30:@373.14]
+  wire [1:0] _T_519; // @[csr.scala 284:30:@375.14]
+  wire  _T_520; // @[csr.scala 285:30:@377.14]
+  wire  _T_521; // @[csr.scala 287:26:@381.14]
+  wire  _T_522; // @[csr.scala 288:30:@383.16]
+  wire  _T_523; // @[csr.scala 289:29:@385.16]
+  wire  _T_524; // @[csr.scala 290:30:@387.16]
+  wire  _T_527; // @[csr.scala 294:26:@395.16]
+  wire  _T_533; // @[csr.scala 301:26:@409.18]
+  wire  _T_534; // @[csr.scala 302:26:@414.20]
+  wire  _T_535; // @[csr.scala 303:26:@419.22]
+  wire [31:0] _T_537; // @[csr.scala 303:56:@421.24]
+  wire [34:0] _GEN_151; // @[csr.scala 303:63:@422.24]
+  wire [34:0] _T_539; // @[csr.scala 303:63:@422.24]
+  wire  _T_540; // @[csr.scala 304:26:@426.24]
+  wire [31:0] _T_542; // @[csr.scala 304:60:@428.26]
+  wire  _T_543; // @[csr.scala 305:26:@432.26]
+  wire [31:0] _GEN_12; // @[csr.scala 305:41:@433.26]
+  wire [31:0] _GEN_13; // @[csr.scala 304:42:@427.24]
+  wire [31:0] _GEN_14; // @[csr.scala 304:42:@427.24]
+  wire [34:0] _GEN_15; // @[csr.scala 303:40:@420.22]
+  wire [31:0] _GEN_16; // @[csr.scala 303:40:@420.22]
+  wire [31:0] _GEN_17; // @[csr.scala 303:40:@420.22]
+  wire [31:0] _GEN_18; // @[csr.scala 302:44:@415.20]
+  wire [34:0] _GEN_19; // @[csr.scala 302:44:@415.20]
+  wire [31:0] _GEN_20; // @[csr.scala 302:44:@415.20]
+  wire [31:0] _GEN_21; // @[csr.scala 302:44:@415.20]
+  wire [31:0] _GEN_22; // @[csr.scala 301:41:@410.18]
+  wire [31:0] _GEN_23; // @[csr.scala 301:41:@410.18]
+  wire [34:0] _GEN_24; // @[csr.scala 301:41:@410.18]
+  wire [31:0] _GEN_25; // @[csr.scala 301:41:@410.18]
+  wire [31:0] _GEN_26; // @[csr.scala 301:41:@410.18]
+  wire  _GEN_27; // @[csr.scala 294:39:@396.16]
+  wire  _GEN_28; // @[csr.scala 294:39:@396.16]
+  wire  _GEN_29; // @[csr.scala 294:39:@396.16]
+  wire  _GEN_30; // @[csr.scala 294:39:@396.16]
+  wire  _GEN_31; // @[csr.scala 294:39:@396.16]
+  wire [31:0] _GEN_32; // @[csr.scala 294:39:@396.16]
+  wire [31:0] _GEN_33; // @[csr.scala 294:39:@396.16]
+  wire [34:0] _GEN_34; // @[csr.scala 294:39:@396.16]
+  wire [31:0] _GEN_35; // @[csr.scala 294:39:@396.16]
+  wire [31:0] _GEN_36; // @[csr.scala 294:39:@396.16]
+  wire  _GEN_40; // @[csr.scala 287:39:@382.14]
+  wire  _GEN_41; // @[csr.scala 287:39:@382.14]
+  wire  _GEN_42; // @[csr.scala 287:39:@382.14]
+  wire  _GEN_43; // @[csr.scala 287:39:@382.14]
+  wire  _GEN_44; // @[csr.scala 287:39:@382.14]
+  wire  _GEN_45; // @[csr.scala 287:39:@382.14]
+  wire  _GEN_46; // @[csr.scala 287:39:@382.14]
+  wire [31:0] _GEN_47; // @[csr.scala 287:39:@382.14]
+  wire [31:0] _GEN_48; // @[csr.scala 287:39:@382.14]
+  wire [34:0] _GEN_49; // @[csr.scala 287:39:@382.14]
+  wire [31:0] _GEN_50; // @[csr.scala 287:39:@382.14]
+  wire [31:0] _GEN_51; // @[csr.scala 287:39:@382.14]
+  wire [1:0] _GEN_52; // @[csr.scala 281:38:@370.12]
+  wire  _GEN_53; // @[csr.scala 281:38:@370.12]
+  wire [1:0] _GEN_54; // @[csr.scala 281:38:@370.12]
+  wire  _GEN_55; // @[csr.scala 281:38:@370.12]
+  wire  _GEN_59; // @[csr.scala 281:38:@370.12]
+  wire  _GEN_60; // @[csr.scala 281:38:@370.12]
+  wire  _GEN_61; // @[csr.scala 281:38:@370.12]
+  wire  _GEN_62; // @[csr.scala 281:38:@370.12]
+  wire  _GEN_63; // @[csr.scala 281:38:@370.12]
+  wire  _GEN_64; // @[csr.scala 281:38:@370.12]
+  wire  _GEN_65; // @[csr.scala 281:38:@370.12]
+  wire [31:0] _GEN_66; // @[csr.scala 281:38:@370.12]
+  wire [31:0] _GEN_67; // @[csr.scala 281:38:@370.12]
+  wire [34:0] _GEN_68; // @[csr.scala 281:38:@370.12]
+  wire [31:0] _GEN_69; // @[csr.scala 281:38:@370.12]
+  wire [31:0] _GEN_70; // @[csr.scala 281:38:@370.12]
+  wire [1:0] _GEN_71; // @[csr.scala 280:21:@368.10]
+  wire  _GEN_72; // @[csr.scala 280:21:@368.10]
+  wire [1:0] _GEN_73; // @[csr.scala 280:21:@368.10]
+  wire  _GEN_74; // @[csr.scala 280:21:@368.10]
+  wire  _GEN_78; // @[csr.scala 280:21:@368.10]
+  wire  _GEN_79; // @[csr.scala 280:21:@368.10]
+  wire  _GEN_80; // @[csr.scala 280:21:@368.10]
+  wire  _GEN_81; // @[csr.scala 280:21:@368.10]
+  wire  _GEN_82; // @[csr.scala 280:21:@368.10]
+  wire  _GEN_83; // @[csr.scala 280:21:@368.10]
+  wire  _GEN_84; // @[csr.scala 280:21:@368.10]
+  wire [31:0] _GEN_85; // @[csr.scala 280:21:@368.10]
+  wire [31:0] _GEN_86; // @[csr.scala 280:21:@368.10]
+  wire [34:0] _GEN_87; // @[csr.scala 280:21:@368.10]
+  wire [31:0] _GEN_88; // @[csr.scala 280:21:@368.10]
+  wire [31:0] _GEN_89; // @[csr.scala 280:21:@368.10]
+  wire [1:0] _GEN_90; // @[csr.scala 275:24:@361.8]
+  wire  _GEN_91; // @[csr.scala 275:24:@361.8]
+  wire [1:0] _GEN_92; // @[csr.scala 275:24:@361.8]
+  wire  _GEN_93; // @[csr.scala 275:24:@361.8]
+  wire  _GEN_97; // @[csr.scala 275:24:@361.8]
+  wire  _GEN_98; // @[csr.scala 275:24:@361.8]
+  wire  _GEN_99; // @[csr.scala 275:24:@361.8]
+  wire  _GEN_100; // @[csr.scala 275:24:@361.8]
+  wire  _GEN_101; // @[csr.scala 275:24:@361.8]
+  wire  _GEN_102; // @[csr.scala 275:24:@361.8]
+  wire  _GEN_103; // @[csr.scala 275:24:@361.8]
+  wire [31:0] _GEN_104; // @[csr.scala 275:24:@361.8]
+  wire [31:0] _GEN_105; // @[csr.scala 275:24:@361.8]
+  wire [34:0] _GEN_106; // @[csr.scala 275:24:@361.8]
+  wire [31:0] _GEN_107; // @[csr.scala 275:24:@361.8]
+  wire [31:0] _GEN_108; // @[csr.scala 275:24:@361.8]
+  wire [34:0] _GEN_109; // @[csr.scala 261:19:@335.6]
+  wire [31:0] _GEN_110; // @[csr.scala 261:19:@335.6]
+  wire [1:0] _GEN_111; // @[csr.scala 261:19:@335.6]
+  wire  _GEN_112; // @[csr.scala 261:19:@335.6]
+  wire [1:0] _GEN_113; // @[csr.scala 261:19:@335.6]
+  wire  _GEN_114; // @[csr.scala 261:19:@335.6]
+  wire [31:0] _GEN_115; // @[csr.scala 261:19:@335.6]
+  wire  _GEN_119; // @[csr.scala 261:19:@335.6]
+  wire  _GEN_120; // @[csr.scala 261:19:@335.6]
+  wire  _GEN_121; // @[csr.scala 261:19:@335.6]
+  wire  _GEN_122; // @[csr.scala 261:19:@335.6]
+  wire  _GEN_123; // @[csr.scala 261:19:@335.6]
+  wire  _GEN_124; // @[csr.scala 261:19:@335.6]
+  wire  _GEN_125; // @[csr.scala 261:19:@335.6]
+  wire [31:0] _GEN_126; // @[csr.scala 261:19:@335.6]
+  wire [31:0] _GEN_127; // @[csr.scala 261:19:@335.6]
+  wire [34:0] _GEN_128; // @[csr.scala 260:20:@334.4]
+  wire  _GEN_135; // @[csr.scala 260:20:@334.4]
+  wire  _GEN_136; // @[csr.scala 260:20:@334.4]
+  wire  _GEN_137; // @[csr.scala 260:20:@334.4]
+  wire  _GEN_138; // @[csr.scala 260:20:@334.4]
+  wire  _GEN_139; // @[csr.scala 260:20:@334.4]
+  wire [31:0] _GEN_145; // @[csr.scala 260:20:@334.4]
+  assign csr_addr = io_inst[31:20]; // @[csr.scala 106:27:@8.4]
+  assign rs1_addr = io_inst[19:15]; // @[csr.scala 107:27:@9.4]
+  assign _GEN_0 = reset ? 1'h0 : mie_motorie; // @[csr.scala 146:3:@26.4]
+  assign _GEN_1 = reset ? 1'h0 : mie_spiie; // @[csr.scala 146:3:@26.4]
+  assign _GEN_2 = reset ? 1'h1 : mie_uartie; // @[csr.scala 146:3:@26.4]
+  assign _GEN_3 = reset ? 1'h1 : mstatus_mie; // @[csr.scala 146:3:@26.4]
+  assign _GEN_4 = reset ? 2'h3 : mstatus_prv; // @[csr.scala 146:3:@26.4]
+  assign _GEN_5 = reset ? 2'h3 : mstatus_mpp; // @[csr.scala 146:3:@26.4]
+  assign _T_147 = {mie_mtie,1'h0,2'h0,mie_msie,1'h0,2'h0}; // @[csr.scala 164:34:@40.4]
+  assign _T_156 = {13'h0,mie_motorie,mie_spiie,mie_uartie,4'h0,4'h0,_T_147}; // @[csr.scala 164:34:@49.4]
+  assign _T_163 = {mip_mtip,1'h0,2'h0,mip_msip,1'h0,2'h0}; // @[csr.scala 169:34:@56.4]
+  assign _T_172 = {13'h0,mip_motorip,mip_spiip,mip_uartip,4'h0,4'h0,_T_163}; // @[csr.scala 169:34:@65.4]
+  assign _T_182 = {mstatus_mpp,2'h0,1'h0,mstatus_mpie,1'h0,1'h0,1'h0,mstatus_mie,1'h0,2'h0}; // @[csr.scala 170:38:@75.4]
+  assign _T_193 = {7'h0,mstatus_prv,3'h0,7'h0,_T_182}; // @[csr.scala 170:38:@86.4]
+  assign _T_198 = 12'hc00 == csr_addr; // @[Lookup.scala 9:38:@88.4]
+  assign _T_202 = 12'hc01 == csr_addr; // @[Lookup.scala 9:38:@90.4]
+  assign _T_206 = 12'hc02 == csr_addr; // @[Lookup.scala 9:38:@92.4]
+  assign _T_210 = 12'hc80 == csr_addr; // @[Lookup.scala 9:38:@94.4]
+  assign _T_214 = 12'hc81 == csr_addr; // @[Lookup.scala 9:38:@96.4]
+  assign _T_218 = 12'hc82 == csr_addr; // @[Lookup.scala 9:38:@98.4]
+  assign _T_222 = 12'h305 == csr_addr; // @[Lookup.scala 9:38:@100.4]
+  assign _T_226 = 12'h304 == csr_addr; // @[Lookup.scala 9:38:@102.4]
+  assign _T_230 = 12'h340 == csr_addr; // @[Lookup.scala 9:38:@104.4]
+  assign _T_234 = 12'h341 == csr_addr; // @[Lookup.scala 9:38:@106.4]
+  assign _T_238 = 12'h342 == csr_addr; // @[Lookup.scala 9:38:@108.4]
+  assign _T_242 = 12'h343 == csr_addr; // @[Lookup.scala 9:38:@110.4]
+  assign _T_246 = 12'h344 == csr_addr; // @[Lookup.scala 9:38:@112.4]
+  assign _T_250 = 12'h300 == csr_addr; // @[Lookup.scala 9:38:@114.4]
+  assign _T_254 = 12'h301 == csr_addr; // @[Lookup.scala 9:38:@116.4]
+  assign _T_255 = _T_254 ? 32'h40000100 : 32'h0; // @[Lookup.scala 11:37:@117.4]
+  assign _T_256 = _T_250 ? _T_193 : _T_255; // @[Lookup.scala 11:37:@118.4]
+  assign _T_257 = _T_246 ? _T_172 : _T_256; // @[Lookup.scala 11:37:@119.4]
+  assign _T_258 = _T_242 ? mtval : _T_257; // @[Lookup.scala 11:37:@120.4]
+  assign _T_259 = _T_238 ? mcause : _T_258; // @[Lookup.scala 11:37:@121.4]
+  assign _T_260 = _T_234 ? mepc : _T_259; // @[Lookup.scala 11:37:@122.4]
+  assign _T_261 = _T_230 ? mscratch : _T_260; // @[Lookup.scala 11:37:@123.4]
+  assign _T_262 = _T_226 ? _T_156 : _T_261; // @[Lookup.scala 11:37:@124.4]
+  assign _T_263 = _T_222 ? mtvec : _T_262; // @[Lookup.scala 11:37:@125.4]
+  assign _T_264 = _T_218 ? instreth : _T_263; // @[Lookup.scala 11:37:@126.4]
+  assign _T_265 = _T_214 ? timeh : _T_264; // @[Lookup.scala 11:37:@127.4]
+  assign _T_266 = _T_210 ? cycleh : _T_265; // @[Lookup.scala 11:37:@128.4]
+  assign _T_267 = _T_206 ? instret : _T_266; // @[Lookup.scala 11:37:@129.4]
+  assign _T_268 = _T_202 ? time$ : _T_267; // @[Lookup.scala 11:37:@130.4]
+  assign _T_270 = csr_addr[9:8]; // @[csr.scala 178:31:@133.4]
+  assign privValid = _T_270 <= mstatus_prv; // @[csr.scala 178:38:@134.4]
+  assign privInst = io_cmd == 3'h4; // @[csr.scala 179:30:@135.4]
+  assign _T_271 = csr_addr[0]; // @[csr.scala 180:44:@136.4]
+  assign _T_273 = _T_271 == 1'h0; // @[csr.scala 180:35:@137.4]
+  assign _T_274 = privInst & _T_273; // @[csr.scala 180:32:@138.4]
+  assign _T_275 = csr_addr[8]; // @[csr.scala 180:60:@139.4]
+  assign _T_277 = _T_275 == 1'h0; // @[csr.scala 180:51:@140.4]
+  assign isEcall = _T_274 & _T_277; // @[csr.scala 180:48:@141.4]
+  assign _T_279 = privInst & _T_271; // @[csr.scala 181:32:@143.4]
+  assign isEbreak = _T_279 & _T_277; // @[csr.scala 181:48:@146.4]
+  assign isEret = _T_274 & _T_275; // @[csr.scala 182:48:@151.4]
+  assign _T_288 = io_addr[1]; // @[csr.scala 183:45:@152.4]
+  assign iaddrInvalid = io_pc_check & _T_288; // @[csr.scala 183:35:@153.4]
+  assign _T_290 = io_addr[1:0]; // @[csr.scala 185:49:@154.4]
+  assign _T_292 = _T_290 != 2'h0; // @[csr.scala 185:56:@155.4]
+  assign _T_293 = io_addr[0]; // @[csr.scala 185:77:@156.4]
+  assign _T_295 = 3'h4 == io_ld_type; // @[Mux.scala 46:19:@158.4]
+  assign _T_296 = _T_295 ? _T_293 : 1'h0; // @[Mux.scala 46:16:@159.4]
+  assign _T_297 = 3'h2 == io_ld_type; // @[Mux.scala 46:19:@160.4]
+  assign _T_298 = _T_297 ? _T_293 : _T_296; // @[Mux.scala 46:16:@161.4]
+  assign _T_299 = 3'h1 == io_ld_type; // @[Mux.scala 46:19:@162.4]
+  assign laddrInvalid = _T_299 ? _T_292 : _T_298; // @[Mux.scala 46:16:@163.4]
+  assign _T_305 = 2'h2 == io_st_type; // @[Mux.scala 46:19:@167.4]
+  assign _T_306 = _T_305 ? _T_293 : 1'h0; // @[Mux.scala 46:16:@168.4]
+  assign _T_307 = 2'h1 == io_st_type; // @[Mux.scala 46:19:@169.4]
+  assign saddrInvalid = _T_307 ? _T_292 : _T_306; // @[Mux.scala 46:16:@170.4]
+  assign isMotor = mip_motorip & mie_motorie; // @[csr.scala 189:36:@171.4]
+  assign isSpi = mip_spiip & mie_spiie; // @[csr.scala 190:35:@172.4]
+  assign isUart = mip_uartip & mie_uartie; // @[csr.scala 191:36:@173.4]
+  assign isTimer = mip_mtip & mie_mtie; // @[csr.scala 192:36:@174.4]
+  assign isSoftware = mip_msip & mie_msie; // @[csr.scala 194:36:@176.4]
+  assign _T_368 = _T_198 | _T_202; // @[csr.scala 197:65:@207.4]
+  assign _T_369 = _T_368 | _T_206; // @[csr.scala 197:65:@208.4]
+  assign _T_370 = _T_369 | _T_210; // @[csr.scala 197:65:@209.4]
+  assign _T_371 = _T_370 | _T_214; // @[csr.scala 197:65:@210.4]
+  assign _T_372 = _T_371 | _T_218; // @[csr.scala 197:65:@211.4]
+  assign _T_373 = _T_372 | _T_222; // @[csr.scala 197:65:@212.4]
+  assign _T_374 = _T_373 | _T_226; // @[csr.scala 197:65:@213.4]
+  assign _T_375 = _T_374 | _T_230; // @[csr.scala 197:65:@214.4]
+  assign _T_376 = _T_375 | _T_234; // @[csr.scala 197:65:@215.4]
+  assign _T_377 = _T_376 | _T_238; // @[csr.scala 197:65:@216.4]
+  assign _T_378 = _T_377 | _T_242; // @[csr.scala 197:65:@217.4]
+  assign _T_379 = _T_378 | _T_246; // @[csr.scala 197:65:@218.4]
+  assign _T_380 = _T_379 | _T_250; // @[csr.scala 197:65:@219.4]
+  assign csrValid = _T_380 | _T_254; // @[csr.scala 197:65:@220.4]
+  assign _T_381 = csr_addr[11:10]; // @[csr.scala 198:31:@221.4]
+  assign _T_382 = ~ _T_381; // @[csr.scala 198:40:@222.4]
+  assign csrRO = _T_382 == 2'h0; // @[csr.scala 198:40:@223.4]
+  assign _T_384 = io_cmd == 3'h1; // @[csr.scala 199:30:@224.4]
+  assign _T_385 = io_cmd[1]; // @[csr.scala 199:49:@225.4]
+  assign _T_387 = rs1_addr != 5'h0; // @[csr.scala 199:65:@226.4]
+  assign _T_388 = _T_385 & _T_387; // @[csr.scala 199:53:@227.4]
+  assign wen = _T_384 | _T_388; // @[csr.scala 199:40:@228.4]
+  assign _T_390 = io_out | io_in; // @[csr.scala 201:68:@229.4]
+  assign _T_391 = ~ io_in; // @[csr.scala 202:70:@230.4]
+  assign _T_392 = io_out & _T_391; // @[csr.scala 202:68:@231.4]
+  assign _T_393 = 3'h3 == io_cmd; // @[Mux.scala 46:19:@232.4]
+  assign _T_394 = _T_393 ? _T_392 : 32'h0; // @[Mux.scala 46:16:@233.4]
+  assign _T_395 = 3'h2 == io_cmd; // @[Mux.scala 46:19:@234.4]
+  assign _T_396 = _T_395 ? _T_390 : _T_394; // @[Mux.scala 46:16:@235.4]
+  assign _T_397 = 3'h1 == io_cmd; // @[Mux.scala 46:19:@236.4]
+  assign wdata = _T_397 ? io_in : _T_396; // @[Mux.scala 46:16:@237.4]
+  assign _GEN_147 = {{28'd0}, mstatus_prv}; // @[csr.scala 208:50:@238.4]
+  assign _T_410 = 30'h8 + _GEN_147; // @[csr.scala 208:50:@238.4]
+  assign _T_411 = 30'h8 + _GEN_147; // @[csr.scala 208:50:@239.4]
+  assign _T_412 = isEbreak ? 30'h3 : 30'h2; // @[csr.scala 209:22:@240.4]
+  assign _T_413 = isEcall ? _T_411 : _T_412; // @[csr.scala 208:22:@241.4]
+  assign _T_414 = saddrInvalid ? 30'h6 : _T_413; // @[csr.scala 207:22:@242.4]
+  assign _T_415 = laddrInvalid ? 30'h4 : _T_414; // @[csr.scala 206:22:@243.4]
+  assign causeExpt = iaddrInvalid ? 30'h0 : _T_415; // @[csr.scala 205:22:@244.4]
+  assign _T_416 = isSpi ? 30'h11 : 30'h12; // @[csr.scala 215:22:@245.4]
+  assign _T_417 = isUart ? 30'h10 : _T_416; // @[csr.scala 214:22:@246.4]
+  assign _T_418 = isTimer ? 30'h7 : _T_417; // @[csr.scala 213:22:@247.4]
+  assign causeInt = isSoftware ? 30'h3 : _T_418; // @[csr.scala 211:22:@249.4]
+  assign _T_420 = isMotor | isSpi; // @[csr.scala 218:29:@250.4]
+  assign _T_421 = _T_420 | isUart; // @[csr.scala 218:38:@251.4]
+  assign _T_422 = _T_421 | isTimer; // @[csr.scala 218:48:@252.4]
+  assign _T_424 = _T_422 | isSoftware; // @[csr.scala 218:73:@254.4]
+  assign isInt = _T_424 & mstatus_mie; // @[csr.scala 218:88:@255.4]
+  assign cause = isInt ? causeInt : causeExpt; // @[csr.scala 219:23:@256.4]
+  assign _T_425 = mtvec[31:2]; // @[csr.scala 222:26:@257.4]
+  assign _GEN_148 = {{2'd0}, _T_425}; // @[csr.scala 222:31:@258.4]
+  assign base = _GEN_148 << 2; // @[csr.scala 222:31:@258.4]
+  assign mode = mtvec[1:0]; // @[csr.scala 223:25:@259.4]
+  assign _T_426 = mode[0]; // @[csr.scala 224:38:@260.4]
+  assign _T_427 = isInt & _T_426; // @[csr.scala 224:31:@261.4]
+  assign _GEN_149 = {{2'd0}, cause}; // @[csr.scala 224:57:@262.4]
+  assign _T_428 = _GEN_149 << 2; // @[csr.scala 224:57:@262.4]
+  assign _T_429 = base + _T_428; // @[csr.scala 224:48:@263.4]
+  assign _T_430 = base + _T_428; // @[csr.scala 224:48:@264.4]
+  assign _T_432 = io_illegal | iaddrInvalid; // @[csr.scala 227:33:@267.4]
+  assign _T_433 = _T_432 | laddrInvalid; // @[csr.scala 227:49:@268.4]
+  assign _T_434 = _T_433 | saddrInvalid; // @[csr.scala 227:65:@269.4]
+  assign _T_435 = io_cmd[1:0]; // @[csr.scala 228:28:@270.4]
+  assign _T_437 = _T_435 != 2'h0; // @[csr.scala 228:35:@271.4]
+  assign _T_439 = csrValid == 1'h0; // @[csr.scala 228:43:@272.4]
+  assign _T_441 = privValid == 1'h0; // @[csr.scala 228:56:@273.4]
+  assign _T_442 = _T_439 | _T_441; // @[csr.scala 228:53:@274.4]
+  assign _T_443 = _T_437 & _T_442; // @[csr.scala 228:39:@275.4]
+  assign _T_444 = _T_434 | _T_443; // @[csr.scala 227:81:@276.4]
+  assign _T_445 = wen & csrRO; // @[csr.scala 228:75:@277.4]
+  assign _T_446 = _T_444 | _T_445; // @[csr.scala 228:68:@278.4]
+  assign _T_449 = privInst & _T_441; // @[csr.scala 229:32:@280.4]
+  assign _T_450 = _T_446 | _T_449; // @[csr.scala 228:84:@281.4]
+  assign _T_451 = _T_450 | isEcall; // @[csr.scala 229:47:@282.4]
+  assign _T_452 = _T_451 | isEbreak; // @[csr.scala 229:58:@283.4]
+  assign _T_455 = time$ + 32'h1; // @[csr.scala 233:26:@287.4]
+  assign _T_456 = time$ + 32'h1; // @[csr.scala 233:26:@288.4]
+  assign _T_457 = ~ time$; // @[csr.scala 234:13:@290.4]
+  assign _T_459 = _T_457 == 32'h0; // @[csr.scala 234:13:@291.4]
+  assign _T_461 = timeh + 32'h1; // @[csr.scala 235:27:@293.6]
+  assign _T_462 = timeh + 32'h1; // @[csr.scala 235:27:@294.6]
+  assign _GEN_6 = _T_459 ? _T_462 : timeh; // @[csr.scala 234:19:@292.4]
+  assign _T_464 = cycle + 32'h1; // @[csr.scala 237:27:@297.4]
+  assign _T_465 = cycle + 32'h1; // @[csr.scala 237:27:@298.4]
+  assign _T_466 = ~ cycle; // @[csr.scala 238:14:@300.4]
+  assign _T_468 = _T_466 == 32'h0; // @[csr.scala 238:14:@301.4]
+  assign _T_470 = cycleh + 32'h1; // @[csr.scala 239:28:@303.6]
+  assign _T_471 = cycleh + 32'h1; // @[csr.scala 239:28:@304.6]
+  assign _GEN_7 = _T_468 ? _T_471 : cycleh; // @[csr.scala 238:20:@302.4]
+  assign _T_473 = io_inst != 32'h13; // @[csr.scala 241:28:@307.4]
+  assign _T_475 = io_expt == 1'h0; // @[csr.scala 241:53:@308.4]
+  assign _T_476 = _T_475 | isEcall; // @[csr.scala 241:62:@309.4]
+  assign _T_477 = _T_476 | isEbreak; // @[csr.scala 241:73:@310.4]
+  assign _T_478 = _T_473 & _T_477; // @[csr.scala 241:49:@311.4]
+  assign _T_480 = io_stall == 1'h0; // @[csr.scala 241:89:@312.4]
+  assign isInstRet = _T_478 & _T_480; // @[csr.scala 241:86:@313.4]
+  assign _T_482 = instret + 32'h1; // @[csr.scala 244:29:@315.6]
+  assign _T_483 = instret + 32'h1; // @[csr.scala 244:29:@316.6]
+  assign _GEN_8 = isInstRet ? _T_483 : instret; // @[csr.scala 243:19:@314.4]
+  assign _T_484 = ~ instret; // @[csr.scala 246:29:@319.4]
+  assign _T_486 = _T_484 == 32'h0; // @[csr.scala 246:29:@320.4]
+  assign _T_487 = isInstRet & _T_486; // @[csr.scala 246:18:@321.4]
+  assign _T_489 = instreth + 32'h1; // @[csr.scala 247:30:@323.6]
+  assign _T_490 = instreth + 32'h1; // @[csr.scala 247:30:@324.6]
+  assign _GEN_9 = _T_487 ? _T_490 : instreth; // @[csr.scala 246:35:@322.4]
+  assign _T_498 = wasEret == 1'h0; // @[csr.scala 265:12:@336.8]
+  assign _T_500 = io_pc - 32'h4; // @[csr.scala 266:54:@338.10]
+  assign _T_501 = $unsigned(_T_500); // @[csr.scala 266:54:@339.10]
+  assign _T_502 = _T_501[31:0]; // @[csr.scala 266:54:@340.10]
+  assign _T_503 = br_taken_delayed ? _T_502 : io_pc; // @[csr.scala 266:29:@341.10]
+  assign _T_504 = _T_503[31:2]; // @[csr.scala 266:69:@342.10]
+  assign _GEN_150 = {{2'd0}, _T_504}; // @[csr.scala 266:74:@343.10]
+  assign _T_505 = _GEN_150 << 2; // @[csr.scala 266:74:@343.10]
+  assign _GEN_10 = _T_498 ? _T_505 : mepc; // @[csr.scala 266:7:@337.8]
+  assign _T_511 = {isInt,1'h0,cause}; // @[Cat.scala 30:58:@348.8]
+  assign _T_513 = iaddrInvalid | laddrInvalid; // @[csr.scala 274:25:@354.8]
+  assign _T_514 = _T_513 | saddrInvalid; // @[csr.scala 274:41:@355.8]
+  assign _GEN_11 = _T_514 ? io_addr : mtval; // @[csr.scala 274:58:@356.8]
+  assign _T_516 = csr_addr == 12'h300; // @[csr.scala 281:21:@369.12]
+  assign _T_517 = wdata[12:11]; // @[csr.scala 282:30:@371.14]
+  assign _T_518 = wdata[7]; // @[csr.scala 283:30:@373.14]
+  assign _T_519 = wdata[24:23]; // @[csr.scala 284:30:@375.14]
+  assign _T_520 = wdata[3]; // @[csr.scala 285:30:@377.14]
+  assign _T_521 = csr_addr == 12'h344; // @[csr.scala 287:26:@381.14]
+  assign _T_522 = wdata[18]; // @[csr.scala 288:30:@383.16]
+  assign _T_523 = wdata[17]; // @[csr.scala 289:29:@385.16]
+  assign _T_524 = wdata[16]; // @[csr.scala 290:30:@387.16]
+  assign _T_527 = csr_addr == 12'h304; // @[csr.scala 294:26:@395.16]
+  assign _T_533 = csr_addr == 12'h305; // @[csr.scala 301:26:@409.18]
+  assign _T_534 = csr_addr == 12'h340; // @[csr.scala 302:26:@414.20]
+  assign _T_535 = csr_addr == 12'h341; // @[csr.scala 303:26:@419.22]
+  assign _T_537 = wdata >> 2'h2; // @[csr.scala 303:56:@421.24]
+  assign _GEN_151 = {{3'd0}, _T_537}; // @[csr.scala 303:63:@422.24]
+  assign _T_539 = _GEN_151 << 2'h2; // @[csr.scala 303:63:@422.24]
+  assign _T_540 = csr_addr == 12'h342; // @[csr.scala 304:26:@426.24]
+  assign _T_542 = wdata & 32'h8000000f; // @[csr.scala 304:60:@428.26]
+  assign _T_543 = csr_addr == 12'h343; // @[csr.scala 305:26:@432.26]
+  assign _GEN_12 = _T_543 ? wdata : mtval; // @[csr.scala 305:41:@433.26]
+  assign _GEN_13 = _T_540 ? _T_542 : mcause; // @[csr.scala 304:42:@427.24]
+  assign _GEN_14 = _T_540 ? mtval : _GEN_12; // @[csr.scala 304:42:@427.24]
+  assign _GEN_15 = _T_535 ? _T_539 : {{3'd0}, mepc}; // @[csr.scala 303:40:@420.22]
+  assign _GEN_16 = _T_535 ? mcause : _GEN_13; // @[csr.scala 303:40:@420.22]
+  assign _GEN_17 = _T_535 ? mtval : _GEN_14; // @[csr.scala 303:40:@420.22]
+  assign _GEN_18 = _T_534 ? wdata : mscratch; // @[csr.scala 302:44:@415.20]
+  assign _GEN_19 = _T_534 ? {{3'd0}, mepc} : _GEN_15; // @[csr.scala 302:44:@415.20]
+  assign _GEN_20 = _T_534 ? mcause : _GEN_16; // @[csr.scala 302:44:@415.20]
+  assign _GEN_21 = _T_534 ? mtval : _GEN_17; // @[csr.scala 302:44:@415.20]
+  assign _GEN_22 = _T_533 ? wdata : mtvec; // @[csr.scala 301:41:@410.18]
+  assign _GEN_23 = _T_533 ? mscratch : _GEN_18; // @[csr.scala 301:41:@410.18]
+  assign _GEN_24 = _T_533 ? {{3'd0}, mepc} : _GEN_19; // @[csr.scala 301:41:@410.18]
+  assign _GEN_25 = _T_533 ? mcause : _GEN_20; // @[csr.scala 301:41:@410.18]
+  assign _GEN_26 = _T_533 ? mtval : _GEN_21; // @[csr.scala 301:41:@410.18]
+  assign _GEN_27 = _T_527 ? _T_522 : _GEN_0; // @[csr.scala 294:39:@396.16]
+  assign _GEN_28 = _T_527 ? _T_523 : _GEN_1; // @[csr.scala 294:39:@396.16]
+  assign _GEN_29 = _T_527 ? _T_524 : _GEN_2; // @[csr.scala 294:39:@396.16]
+  assign _GEN_30 = _T_527 ? _T_518 : mie_mtie; // @[csr.scala 294:39:@396.16]
+  assign _GEN_31 = _T_527 ? _T_520 : mie_msie; // @[csr.scala 294:39:@396.16]
+  assign _GEN_32 = _T_527 ? mtvec : _GEN_22; // @[csr.scala 294:39:@396.16]
+  assign _GEN_33 = _T_527 ? mscratch : _GEN_23; // @[csr.scala 294:39:@396.16]
+  assign _GEN_34 = _T_527 ? {{3'd0}, mepc} : _GEN_24; // @[csr.scala 294:39:@396.16]
+  assign _GEN_35 = _T_527 ? mcause : _GEN_25; // @[csr.scala 294:39:@396.16]
+  assign _GEN_36 = _T_527 ? mtval : _GEN_26; // @[csr.scala 294:39:@396.16]
+  assign _GEN_40 = _T_521 ? _T_518 : mip_mtip; // @[csr.scala 287:39:@382.14]
+  assign _GEN_41 = _T_521 ? _T_520 : mip_msip; // @[csr.scala 287:39:@382.14]
+  assign _GEN_42 = _T_521 ? _GEN_0 : _GEN_27; // @[csr.scala 287:39:@382.14]
+  assign _GEN_43 = _T_521 ? _GEN_1 : _GEN_28; // @[csr.scala 287:39:@382.14]
+  assign _GEN_44 = _T_521 ? _GEN_2 : _GEN_29; // @[csr.scala 287:39:@382.14]
+  assign _GEN_45 = _T_521 ? mie_mtie : _GEN_30; // @[csr.scala 287:39:@382.14]
+  assign _GEN_46 = _T_521 ? mie_msie : _GEN_31; // @[csr.scala 287:39:@382.14]
+  assign _GEN_47 = _T_521 ? mtvec : _GEN_32; // @[csr.scala 287:39:@382.14]
+  assign _GEN_48 = _T_521 ? mscratch : _GEN_33; // @[csr.scala 287:39:@382.14]
+  assign _GEN_49 = _T_521 ? {{3'd0}, mepc} : _GEN_34; // @[csr.scala 287:39:@382.14]
+  assign _GEN_50 = _T_521 ? mcause : _GEN_35; // @[csr.scala 287:39:@382.14]
+  assign _GEN_51 = _T_521 ? mtval : _GEN_36; // @[csr.scala 287:39:@382.14]
+  assign _GEN_52 = _T_516 ? _T_517 : _GEN_5; // @[csr.scala 281:38:@370.12]
+  assign _GEN_53 = _T_516 ? _T_518 : mstatus_mpie; // @[csr.scala 281:38:@370.12]
+  assign _GEN_54 = _T_516 ? _T_519 : _GEN_4; // @[csr.scala 281:38:@370.12]
+  assign _GEN_55 = _T_516 ? _T_520 : _GEN_3; // @[csr.scala 281:38:@370.12]
+  assign _GEN_59 = _T_516 ? mip_mtip : _GEN_40; // @[csr.scala 281:38:@370.12]
+  assign _GEN_60 = _T_516 ? mip_msip : _GEN_41; // @[csr.scala 281:38:@370.12]
+  assign _GEN_61 = _T_516 ? _GEN_0 : _GEN_42; // @[csr.scala 281:38:@370.12]
+  assign _GEN_62 = _T_516 ? _GEN_1 : _GEN_43; // @[csr.scala 281:38:@370.12]
+  assign _GEN_63 = _T_516 ? _GEN_2 : _GEN_44; // @[csr.scala 281:38:@370.12]
+  assign _GEN_64 = _T_516 ? mie_mtie : _GEN_45; // @[csr.scala 281:38:@370.12]
+  assign _GEN_65 = _T_516 ? mie_msie : _GEN_46; // @[csr.scala 281:38:@370.12]
+  assign _GEN_66 = _T_516 ? mtvec : _GEN_47; // @[csr.scala 281:38:@370.12]
+  assign _GEN_67 = _T_516 ? mscratch : _GEN_48; // @[csr.scala 281:38:@370.12]
+  assign _GEN_68 = _T_516 ? {{3'd0}, mepc} : _GEN_49; // @[csr.scala 281:38:@370.12]
+  assign _GEN_69 = _T_516 ? mcause : _GEN_50; // @[csr.scala 281:38:@370.12]
+  assign _GEN_70 = _T_516 ? mtval : _GEN_51; // @[csr.scala 281:38:@370.12]
+  assign _GEN_71 = wen ? _GEN_52 : _GEN_5; // @[csr.scala 280:21:@368.10]
+  assign _GEN_72 = wen ? _GEN_53 : mstatus_mpie; // @[csr.scala 280:21:@368.10]
+  assign _GEN_73 = wen ? _GEN_54 : _GEN_4; // @[csr.scala 280:21:@368.10]
+  assign _GEN_74 = wen ? _GEN_55 : _GEN_3; // @[csr.scala 280:21:@368.10]
+  assign _GEN_78 = wen ? _GEN_59 : mip_mtip; // @[csr.scala 280:21:@368.10]
+  assign _GEN_79 = wen ? _GEN_60 : mip_msip; // @[csr.scala 280:21:@368.10]
+  assign _GEN_80 = wen ? _GEN_61 : _GEN_0; // @[csr.scala 280:21:@368.10]
+  assign _GEN_81 = wen ? _GEN_62 : _GEN_1; // @[csr.scala 280:21:@368.10]
+  assign _GEN_82 = wen ? _GEN_63 : _GEN_2; // @[csr.scala 280:21:@368.10]
+  assign _GEN_83 = wen ? _GEN_64 : mie_mtie; // @[csr.scala 280:21:@368.10]
+  assign _GEN_84 = wen ? _GEN_65 : mie_msie; // @[csr.scala 280:21:@368.10]
+  assign _GEN_85 = wen ? _GEN_66 : mtvec; // @[csr.scala 280:21:@368.10]
+  assign _GEN_86 = wen ? _GEN_67 : mscratch; // @[csr.scala 280:21:@368.10]
+  assign _GEN_87 = wen ? _GEN_68 : {{3'd0}, mepc}; // @[csr.scala 280:21:@368.10]
+  assign _GEN_88 = wen ? _GEN_69 : mcause; // @[csr.scala 280:21:@368.10]
+  assign _GEN_89 = wen ? _GEN_70 : mtval; // @[csr.scala 280:21:@368.10]
+  assign _GEN_90 = isEret ? mstatus_mpp : _GEN_73; // @[csr.scala 275:24:@361.8]
+  assign _GEN_91 = isEret ? mstatus_mpie : _GEN_74; // @[csr.scala 275:24:@361.8]
+  assign _GEN_92 = isEret ? 2'h3 : _GEN_71; // @[csr.scala 275:24:@361.8]
+  assign _GEN_93 = isEret ? 1'h1 : _GEN_72; // @[csr.scala 275:24:@361.8]
+  assign _GEN_97 = isEret ? mip_mtip : _GEN_78; // @[csr.scala 275:24:@361.8]
+  assign _GEN_98 = isEret ? mip_msip : _GEN_79; // @[csr.scala 275:24:@361.8]
+  assign _GEN_99 = isEret ? _GEN_0 : _GEN_80; // @[csr.scala 275:24:@361.8]
+  assign _GEN_100 = isEret ? _GEN_1 : _GEN_81; // @[csr.scala 275:24:@361.8]
+  assign _GEN_101 = isEret ? _GEN_2 : _GEN_82; // @[csr.scala 275:24:@361.8]
+  assign _GEN_102 = isEret ? mie_mtie : _GEN_83; // @[csr.scala 275:24:@361.8]
+  assign _GEN_103 = isEret ? mie_msie : _GEN_84; // @[csr.scala 275:24:@361.8]
+  assign _GEN_104 = isEret ? mtvec : _GEN_85; // @[csr.scala 275:24:@361.8]
+  assign _GEN_105 = isEret ? mscratch : _GEN_86; // @[csr.scala 275:24:@361.8]
+  assign _GEN_106 = isEret ? {{3'd0}, mepc} : _GEN_87; // @[csr.scala 275:24:@361.8]
+  assign _GEN_107 = isEret ? mcause : _GEN_88; // @[csr.scala 275:24:@361.8]
+  assign _GEN_108 = isEret ? mtval : _GEN_89; // @[csr.scala 275:24:@361.8]
+  assign _GEN_109 = io_expt ? {{3'd0}, _GEN_10} : _GEN_106; // @[csr.scala 261:19:@335.6]
+  assign _GEN_110 = io_expt ? _T_511 : _GEN_107; // @[csr.scala 261:19:@335.6]
+  assign _GEN_111 = io_expt ? 2'h3 : _GEN_90; // @[csr.scala 261:19:@335.6]
+  assign _GEN_112 = io_expt ? 1'h0 : _GEN_91; // @[csr.scala 261:19:@335.6]
+  assign _GEN_113 = io_expt ? mstatus_prv : _GEN_92; // @[csr.scala 261:19:@335.6]
+  assign _GEN_114 = io_expt ? mstatus_mie : _GEN_93; // @[csr.scala 261:19:@335.6]
+  assign _GEN_115 = io_expt ? _GEN_11 : _GEN_108; // @[csr.scala 261:19:@335.6]
+  assign _GEN_119 = io_expt ? mip_mtip : _GEN_97; // @[csr.scala 261:19:@335.6]
+  assign _GEN_120 = io_expt ? mip_msip : _GEN_98; // @[csr.scala 261:19:@335.6]
+  assign _GEN_121 = io_expt ? _GEN_0 : _GEN_99; // @[csr.scala 261:19:@335.6]
+  assign _GEN_122 = io_expt ? _GEN_1 : _GEN_100; // @[csr.scala 261:19:@335.6]
+  assign _GEN_123 = io_expt ? _GEN_2 : _GEN_101; // @[csr.scala 261:19:@335.6]
+  assign _GEN_124 = io_expt ? mie_mtie : _GEN_102; // @[csr.scala 261:19:@335.6]
+  assign _GEN_125 = io_expt ? mie_msie : _GEN_103; // @[csr.scala 261:19:@335.6]
+  assign _GEN_126 = io_expt ? mtvec : _GEN_104; // @[csr.scala 261:19:@335.6]
+  assign _GEN_127 = io_expt ? mscratch : _GEN_105; // @[csr.scala 261:19:@335.6]
+  assign _GEN_128 = _T_480 ? _GEN_109 : {{3'd0}, mepc}; // @[csr.scala 260:20:@334.4]
+  assign _GEN_135 = _T_480 ? io_irq_motor_irq : mip_motorip; // @[csr.scala 260:20:@334.4]
+  assign _GEN_136 = _T_480 ? io_irq_spi_irq : mip_spiip; // @[csr.scala 260:20:@334.4]
+  assign _GEN_137 = _T_480 ? io_irq_uart_irq : mip_uartip; // @[csr.scala 260:20:@334.4]
+  assign _GEN_138 = _T_480 ? _GEN_119 : mip_mtip; // @[csr.scala 260:20:@334.4]
+  assign _GEN_139 = _T_480 ? _GEN_120 : mip_msip; // @[csr.scala 260:20:@334.4]
+  assign _GEN_145 = _T_480 ? _GEN_126 : mtvec; // @[csr.scala 260:20:@334.4]
+  assign io_out = _T_198 ? cycle : _T_268; // @[csr.scala 175:10:@132.4]
+  assign io_expt = _T_452 | isInt; // @[csr.scala 227:18:@285.4]
+  assign io_evec = _T_427 ? _T_430 : base; // @[csr.scala 224:18:@266.4]
+  assign io_epc = mepc; // @[csr.scala 230:18:@286.4]
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE
+  integer initvar;
+  initial begin
+    `ifdef INIT_RANDOM
+      `INIT_RANDOM
+    `endif
+    `ifndef VERILATOR
+      #0.002 begin end
+    `endif
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_0 = {1{`RANDOM}};
+  time$ = _RAND_0[31:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_1 = {1{`RANDOM}};
+  timeh = _RAND_1[31:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_2 = {1{`RANDOM}};
+  cycle = _RAND_2[31:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_3 = {1{`RANDOM}};
+  cycleh = _RAND_3[31:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_4 = {1{`RANDOM}};
+  instret = _RAND_4[31:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_5 = {1{`RANDOM}};
+  instreth = _RAND_5[31:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_6 = {1{`RANDOM}};
+  mstatus_prv = _RAND_6[1:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_7 = {1{`RANDOM}};
+  mstatus_mpp = _RAND_7[1:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_8 = {1{`RANDOM}};
+  mstatus_mpie = _RAND_8[0:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_9 = {1{`RANDOM}};
+  mstatus_mie = _RAND_9[0:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_10 = {1{`RANDOM}};
+  mie_motorie = _RAND_10[0:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_11 = {1{`RANDOM}};
+  mie_spiie = _RAND_11[0:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_12 = {1{`RANDOM}};
+  mie_uartie = _RAND_12[0:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_13 = {1{`RANDOM}};
+  mie_mtie = _RAND_13[0:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_14 = {1{`RANDOM}};
+  mie_msie = _RAND_14[0:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_15 = {1{`RANDOM}};
+  mip_motorip = _RAND_15[0:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_16 = {1{`RANDOM}};
+  mip_spiip = _RAND_16[0:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_17 = {1{`RANDOM}};
+  mip_uartip = _RAND_17[0:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_18 = {1{`RANDOM}};
+  mip_mtip = _RAND_18[0:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_19 = {1{`RANDOM}};
+  mip_msip = _RAND_19[0:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_20 = {1{`RANDOM}};
+  mtvec = _RAND_20[31:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_21 = {1{`RANDOM}};
+  mscratch = _RAND_21[31:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_22 = {1{`RANDOM}};
+  mepc = _RAND_22[31:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_23 = {1{`RANDOM}};
+  mcause = _RAND_23[31:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_24 = {1{`RANDOM}};
+  mtval = _RAND_24[31:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_25 = {1{`RANDOM}};
+  wasEret = _RAND_25[0:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_26 = {1{`RANDOM}};
+  br_taken = _RAND_26[0:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_27 = {1{`RANDOM}};
+  br_taken_delayed = _RAND_27[0:0];
+  `endif // RANDOMIZE_REG_INIT
+  end
+`endif // RANDOMIZE
+  always @(posedge clock) begin
+    if (reset) begin
+      time$ <= 32'h0;
+    end else begin
+      time$ <= _T_456;
+    end
+    if (reset) begin
+      timeh <= 32'h0;
+    end else begin
+      if (_T_459) begin
+        timeh <= _T_462;
+      end
+    end
+    if (reset) begin
+      cycle <= 32'h0;
+    end else begin
+      cycle <= _T_465;
+    end
+    if (reset) begin
+      cycleh <= 32'h0;
+    end else begin
+      if (_T_468) begin
+        cycleh <= _T_471;
+      end
+    end
+    if (reset) begin
+      instret <= 32'h0;
+    end else begin
+      if (isInstRet) begin
+        instret <= _T_483;
+      end
+    end
+    if (reset) begin
+      instreth <= 32'h0;
+    end else begin
+      if (_T_487) begin
+        instreth <= _T_490;
+      end
+    end
+    if (_T_480) begin
+      if (io_expt) begin
+        mstatus_prv <= 2'h3;
+      end else begin
+        if (isEret) begin
+          mstatus_prv <= mstatus_mpp;
+        end else begin
+          if (wen) begin
+            if (_T_516) begin
+              mstatus_prv <= _T_519;
+            end else begin
+              if (reset) begin
+                mstatus_prv <= 2'h3;
+              end
+            end
+          end else begin
+            if (reset) begin
+              mstatus_prv <= 2'h3;
+            end
+          end
+        end
+      end
+    end else begin
+      if (reset) begin
+        mstatus_prv <= 2'h3;
+      end
+    end
+    if (_T_480) begin
+      if (io_expt) begin
+        mstatus_mpp <= mstatus_prv;
+      end else begin
+        if (isEret) begin
+          mstatus_mpp <= 2'h3;
+        end else begin
+          if (wen) begin
+            if (_T_516) begin
+              mstatus_mpp <= _T_517;
+            end else begin
+              if (reset) begin
+                mstatus_mpp <= 2'h3;
+              end
+            end
+          end else begin
+            if (reset) begin
+              mstatus_mpp <= 2'h3;
+            end
+          end
+        end
+      end
+    end else begin
+      if (reset) begin
+        mstatus_mpp <= 2'h3;
+      end
+    end
+    if (_T_480) begin
+      if (io_expt) begin
+        mstatus_mpie <= mstatus_mie;
+      end else begin
+        if (isEret) begin
+          mstatus_mpie <= 1'h1;
+        end else begin
+          if (wen) begin
+            if (_T_516) begin
+              mstatus_mpie <= _T_518;
+            end
+          end
+        end
+      end
+    end
+    if (_T_480) begin
+      if (io_expt) begin
+        mstatus_mie <= 1'h0;
+      end else begin
+        if (isEret) begin
+          mstatus_mie <= mstatus_mpie;
+        end else begin
+          if (wen) begin
+            if (_T_516) begin
+              mstatus_mie <= _T_520;
+            end else begin
+              if (reset) begin
+                mstatus_mie <= 1'h1;
+              end
+            end
+          end else begin
+            if (reset) begin
+              mstatus_mie <= 1'h1;
+            end
+          end
+        end
+      end
+    end else begin
+      if (reset) begin
+        mstatus_mie <= 1'h1;
+      end
+    end
+    if (_T_480) begin
+      if (io_expt) begin
+        if (reset) begin
+          mie_motorie <= 1'h0;
+        end
+      end else begin
+        if (isEret) begin
+          if (reset) begin
+            mie_motorie <= 1'h0;
+          end
+        end else begin
+          if (wen) begin
+            if (_T_516) begin
+              if (reset) begin
+                mie_motorie <= 1'h0;
+              end
+            end else begin
+              if (_T_521) begin
+                if (reset) begin
+                  mie_motorie <= 1'h0;
+                end
+              end else begin
+                if (_T_527) begin
+                  mie_motorie <= _T_522;
+                end else begin
+                  mie_motorie <= _GEN_0;
+                end
+              end
+            end
+          end else begin
+            mie_motorie <= _GEN_0;
+          end
+        end
+      end
+    end else begin
+      mie_motorie <= _GEN_0;
+    end
+    if (_T_480) begin
+      if (io_expt) begin
+        if (reset) begin
+          mie_spiie <= 1'h0;
+        end
+      end else begin
+        if (isEret) begin
+          if (reset) begin
+            mie_spiie <= 1'h0;
+          end
+        end else begin
+          if (wen) begin
+            if (_T_516) begin
+              if (reset) begin
+                mie_spiie <= 1'h0;
+              end
+            end else begin
+              if (_T_521) begin
+                if (reset) begin
+                  mie_spiie <= 1'h0;
+                end
+              end else begin
+                if (_T_527) begin
+                  mie_spiie <= _T_523;
+                end else begin
+                  mie_spiie <= _GEN_1;
+                end
+              end
+            end
+          end else begin
+            mie_spiie <= _GEN_1;
+          end
+        end
+      end
+    end else begin
+      mie_spiie <= _GEN_1;
+    end
+    if (_T_480) begin
+      if (io_expt) begin
+        if (reset) begin
+          mie_uartie <= 1'h1;
+        end
+      end else begin
+        if (isEret) begin
+          if (reset) begin
+            mie_uartie <= 1'h1;
+          end
+        end else begin
+          if (wen) begin
+            if (_T_516) begin
+              if (reset) begin
+                mie_uartie <= 1'h1;
+              end
+            end else begin
+              if (_T_521) begin
+                if (reset) begin
+                  mie_uartie <= 1'h1;
+                end
+              end else begin
+                if (_T_527) begin
+                  mie_uartie <= _T_524;
+                end else begin
+                  mie_uartie <= _GEN_2;
+                end
+              end
+            end
+          end else begin
+            mie_uartie <= _GEN_2;
+          end
+        end
+      end
+    end else begin
+      mie_uartie <= _GEN_2;
+    end
+    if (_T_480) begin
+      if (!(io_expt)) begin
+        if (!(isEret)) begin
+          if (wen) begin
+            if (!(_T_516)) begin
+              if (!(_T_521)) begin
+                if (_T_527) begin
+                  mie_mtie <= _T_518;
+                end
+              end
+            end
+          end
+        end
+      end
+    end
+    if (_T_480) begin
+      if (!(io_expt)) begin
+        if (!(isEret)) begin
+          if (wen) begin
+            if (!(_T_516)) begin
+              if (!(_T_521)) begin
+                if (_T_527) begin
+                  mie_msie <= _T_520;
+                end
+              end
+            end
+          end
+        end
+      end
+    end
+    if (reset) begin
+      mip_motorip <= 1'h0;
+    end else begin
+      if (_T_480) begin
+        mip_motorip <= io_irq_motor_irq;
+      end
+    end
+    if (reset) begin
+      mip_spiip <= 1'h0;
+    end else begin
+      if (_T_480) begin
+        mip_spiip <= io_irq_spi_irq;
+      end
+    end
+    if (reset) begin
+      mip_uartip <= 1'h0;
+    end else begin
+      if (_T_480) begin
+        mip_uartip <= io_irq_uart_irq;
+      end
+    end
+    if (reset) begin
+      mip_mtip <= 1'h0;
+    end else begin
+      if (_T_480) begin
+        if (!(io_expt)) begin
+          if (!(isEret)) begin
+            if (wen) begin
+              if (!(_T_516)) begin
+                if (_T_521) begin
+                  mip_mtip <= _T_518;
+                end
+              end
+            end
+          end
+        end
+      end
+    end
+    if (reset) begin
+      mip_msip <= 1'h0;
+    end else begin
+      if (_T_480) begin
+        if (!(io_expt)) begin
+          if (!(isEret)) begin
+            if (wen) begin
+              if (!(_T_516)) begin
+                if (_T_521) begin
+                  mip_msip <= _T_520;
+                end
+              end
+            end
+          end
+        end
+      end
+    end
+    if (reset) begin
+      mtvec <= 32'h9;
+    end else begin
+      if (_T_480) begin
+        if (!(io_expt)) begin
+          if (!(isEret)) begin
+            if (wen) begin
+              if (!(_T_516)) begin
+                if (!(_T_521)) begin
+                  if (!(_T_527)) begin
+                    if (_T_533) begin
+                      if (_T_397) begin
+                        mtvec <= io_in;
+                      end else begin
+                        if (_T_395) begin
+                          mtvec <= _T_390;
+                        end else begin
+                          if (_T_393) begin
+                            mtvec <= _T_392;
+                          end else begin
+                            mtvec <= 32'h0;
+                          end
+                        end
+                      end
+                    end
+                  end
+                end
+              end
+            end
+          end
+        end
+      end
+    end
+    if (_T_480) begin
+      if (!(io_expt)) begin
+        if (!(isEret)) begin
+          if (wen) begin
+            if (!(_T_516)) begin
+              if (!(_T_521)) begin
+                if (!(_T_527)) begin
+                  if (!(_T_533)) begin
+                    if (_T_534) begin
+                      if (_T_397) begin
+                        mscratch <= io_in;
+                      end else begin
+                        if (_T_395) begin
+                          mscratch <= _T_390;
+                        end else begin
+                          if (_T_393) begin
+                            mscratch <= _T_392;
+                          end else begin
+                            mscratch <= 32'h0;
+                          end
+                        end
+                      end
+                    end
+                  end
+                end
+              end
+            end
+          end
+        end
+      end
+    end
+    mepc <= _GEN_128[31:0];
+    if (_T_480) begin
+      if (io_expt) begin
+        mcause <= _T_511;
+      end else begin
+        if (!(isEret)) begin
+          if (wen) begin
+            if (!(_T_516)) begin
+              if (!(_T_521)) begin
+                if (!(_T_527)) begin
+                  if (!(_T_533)) begin
+                    if (!(_T_534)) begin
+                      if (!(_T_535)) begin
+                        if (_T_540) begin
+                          mcause <= _T_542;
+                        end
+                      end
+                    end
+                  end
+                end
+              end
+            end
+          end
+        end
+      end
+    end
+    if (_T_480) begin
+      if (io_expt) begin
+        if (_T_514) begin
+          mtval <= io_addr;
+        end
+      end else begin
+        if (!(isEret)) begin
+          if (wen) begin
+            if (!(_T_516)) begin
+              if (!(_T_521)) begin
+                if (!(_T_527)) begin
+                  if (!(_T_533)) begin
+                    if (!(_T_534)) begin
+                      if (!(_T_535)) begin
+                        if (!(_T_540)) begin
+                          if (_T_543) begin
+                            if (_T_397) begin
+                              mtval <= io_in;
+                            end else begin
+                              if (_T_395) begin
+                                mtval <= _T_390;
+                              end else begin
+                                if (_T_393) begin
+                                  mtval <= _T_392;
+                                end else begin
+                                  mtval <= 32'h0;
+                                end
+                              end
+                            end
+                          end
+                        end
+                      end
+                    end
+                  end
+                end
+              end
+            end
+          end
+        end
+      end
+    end
+    if (reset) begin
+      wasEret <= 1'h0;
+    end else begin
+      wasEret <= isEret;
+    end
+    br_taken <= io_br_taken;
+    br_taken_delayed <= br_taken;
+  end
+endmodule
+module RegFile( // @[:@442.2]
+  input         clock, // @[:@443.4]
+  input  [4:0]  io_raddr1, // @[:@445.4]
+  input  [4:0]  io_raddr2, // @[:@445.4]
+  output [31:0] io_rdata1, // @[:@445.4]
+  output [31:0] io_rdata2, // @[:@445.4]
+  input         io_wen, // @[:@445.4]
+  input  [4:0]  io_waddr, // @[:@445.4]
+  input  [31:0] io_wdata // @[:@445.4]
+);
+  reg [31:0] regs [0:31]; // @[reg_file.scala 30:17:@447.4]
+  reg [31:0] _RAND_0;
+  wire [31:0] regs__T_23_data; // @[reg_file.scala 30:17:@447.4]
+  wire [4:0] regs__T_23_addr; // @[reg_file.scala 30:17:@447.4]
+  wire [31:0] regs__T_28_data; // @[reg_file.scala 30:17:@447.4]
+  wire [4:0] regs__T_28_addr; // @[reg_file.scala 30:17:@447.4]
+  wire [31:0] regs__T_34_data; // @[reg_file.scala 30:17:@447.4]
+  wire [4:0] regs__T_34_addr; // @[reg_file.scala 30:17:@447.4]
+  wire  regs__T_34_mask; // @[reg_file.scala 30:17:@447.4]
+  wire  regs__T_34_en; // @[reg_file.scala 30:17:@447.4]
+  wire  _T_22; // @[reg_file.scala 32:31:@448.4]
+  wire  _T_27; // @[reg_file.scala 33:31:@452.4]
+  wire  _T_32; // @[reg_file.scala 35:26:@456.4]
+  assign regs__T_23_addr = io_raddr1;
+  assign regs__T_23_data = regs[regs__T_23_addr]; // @[reg_file.scala 30:17:@447.4]
+  assign regs__T_28_addr = io_raddr2;
+  assign regs__T_28_data = regs[regs__T_28_addr]; // @[reg_file.scala 30:17:@447.4]
+  assign regs__T_34_data = io_wdata;
+  assign regs__T_34_addr = io_waddr;
+  assign regs__T_34_mask = 1'h1;
+  assign regs__T_34_en = io_wen & _T_32;
+  assign _T_22 = io_raddr1 != 5'h0; // @[reg_file.scala 32:31:@448.4]
+  assign _T_27 = io_raddr2 != 5'h0; // @[reg_file.scala 33:31:@452.4]
+  assign _T_32 = io_waddr != 5'h0; // @[reg_file.scala 35:26:@456.4]
+  assign io_rdata1 = _T_22 ? regs__T_23_data : 32'h0; // @[reg_file.scala 32:13:@451.4]
+  assign io_rdata2 = _T_27 ? regs__T_28_data : 32'h0; // @[reg_file.scala 33:13:@455.4]
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE
+  integer initvar;
+  initial begin
+    `ifdef INIT_RANDOM
+      `INIT_RANDOM
+    `endif
+    `ifndef VERILATOR
+      #0.002 begin end
+    `endif
+  _RAND_0 = {1{`RANDOM}};
+  `ifdef RANDOMIZE_MEM_INIT
+  for (initvar = 0; initvar < 32; initvar = initvar+1)
+    regs[initvar] = _RAND_0[31:0];
+  `endif // RANDOMIZE_MEM_INIT
+  end
+`endif // RANDOMIZE
+  always @(posedge clock) begin
+    if(regs__T_34_en & regs__T_34_mask) begin
+      regs[regs__T_34_addr] <= regs__T_34_data; // @[reg_file.scala 30:17:@447.4]
+    end
+  end
+endmodule
+module ALU( // @[:@463.2]
+  input  [31:0] io_in_a, // @[:@466.4]
+  input  [31:0] io_in_b, // @[:@466.4]
+  input  [3:0]  io_alu_op, // @[:@466.4]
+  output [31:0] io_out, // @[:@466.4]
+  output [31:0] io_sum // @[:@466.4]
+);
+  wire  _T_15; // @[alu.scala 46:39:@468.4]
+  wire [32:0] _T_17; // @[alu.scala 46:44:@469.4]
+  wire [32:0] _T_18; // @[alu.scala 46:44:@470.4]
+  wire [31:0] _T_19; // @[alu.scala 46:44:@471.4]
+  wire [31:0] _T_20; // @[alu.scala 46:29:@472.4]
+  wire [32:0] _T_21; // @[alu.scala 46:24:@473.4]
+  wire [31:0] sum; // @[alu.scala 46:24:@474.4]
+  wire  _T_22; // @[alu.scala 47:28:@475.4]
+  wire  _T_23; // @[alu.scala 47:48:@476.4]
+  wire  _T_24; // @[alu.scala 47:37:@477.4]
+  wire  _T_25; // @[alu.scala 47:61:@478.4]
+  wire  _T_26; // @[alu.scala 48:33:@479.4]
+  wire  _T_29; // @[alu.scala 48:23:@482.4]
+  wire  cmp; // @[alu.scala 47:19:@483.4]
+  wire [4:0] shamt; // @[alu.scala 49:23:@484.4]
+  wire  _T_30; // @[alu.scala 50:29:@485.4]
+  wire [15:0] _T_35; // @[Bitwise.scala 103:21:@488.4]
+  wire [31:0] _T_36; // @[Bitwise.scala 103:31:@489.4]
+  wire [15:0] _T_37; // @[Bitwise.scala 103:46:@490.4]
+  wire [31:0] _GEN_0; // @[Bitwise.scala 103:65:@491.4]
+  wire [31:0] _T_38; // @[Bitwise.scala 103:65:@491.4]
+  wire [31:0] _T_40; // @[Bitwise.scala 103:75:@493.4]
+  wire [31:0] _T_41; // @[Bitwise.scala 103:39:@494.4]
+  wire [23:0] _T_45; // @[Bitwise.scala 103:21:@498.4]
+  wire [31:0] _GEN_1; // @[Bitwise.scala 103:31:@499.4]
+  wire [31:0] _T_46; // @[Bitwise.scala 103:31:@499.4]
+  wire [23:0] _T_47; // @[Bitwise.scala 103:46:@500.4]
+  wire [31:0] _GEN_2; // @[Bitwise.scala 103:65:@501.4]
+  wire [31:0] _T_48; // @[Bitwise.scala 103:65:@501.4]
+  wire [31:0] _T_50; // @[Bitwise.scala 103:75:@503.4]
+  wire [31:0] _T_51; // @[Bitwise.scala 103:39:@504.4]
+  wire [27:0] _T_55; // @[Bitwise.scala 103:21:@508.4]
+  wire [31:0] _GEN_3; // @[Bitwise.scala 103:31:@509.4]
+  wire [31:0] _T_56; // @[Bitwise.scala 103:31:@509.4]
+  wire [27:0] _T_57; // @[Bitwise.scala 103:46:@510.4]
+  wire [31:0] _GEN_4; // @[Bitwise.scala 103:65:@511.4]
+  wire [31:0] _T_58; // @[Bitwise.scala 103:65:@511.4]
+  wire [31:0] _T_60; // @[Bitwise.scala 103:75:@513.4]
+  wire [31:0] _T_61; // @[Bitwise.scala 103:39:@514.4]
+  wire [29:0] _T_65; // @[Bitwise.scala 103:21:@518.4]
+  wire [31:0] _GEN_5; // @[Bitwise.scala 103:31:@519.4]
+  wire [31:0] _T_66; // @[Bitwise.scala 103:31:@519.4]
+  wire [29:0] _T_67; // @[Bitwise.scala 103:46:@520.4]
+  wire [31:0] _GEN_6; // @[Bitwise.scala 103:65:@521.4]
+  wire [31:0] _T_68; // @[Bitwise.scala 103:65:@521.4]
+  wire [31:0] _T_70; // @[Bitwise.scala 103:75:@523.4]
+  wire [31:0] _T_71; // @[Bitwise.scala 103:39:@524.4]
+  wire [30:0] _T_75; // @[Bitwise.scala 103:21:@528.4]
+  wire [31:0] _GEN_7; // @[Bitwise.scala 103:31:@529.4]
+  wire [31:0] _T_76; // @[Bitwise.scala 103:31:@529.4]
+  wire [30:0] _T_77; // @[Bitwise.scala 103:46:@530.4]
+  wire [31:0] _GEN_8; // @[Bitwise.scala 103:65:@531.4]
+  wire [31:0] _T_78; // @[Bitwise.scala 103:65:@531.4]
+  wire [31:0] _T_80; // @[Bitwise.scala 103:75:@533.4]
+  wire [31:0] _T_81; // @[Bitwise.scala 103:39:@534.4]
+  wire [31:0] shin; // @[alu.scala 50:19:@535.4]
+  wire  _T_83; // @[alu.scala 51:41:@537.4]
+  wire  _T_84; // @[alu.scala 51:34:@538.4]
+  wire [32:0] _T_85; // @[Cat.scala 30:58:@539.4]
+  wire [32:0] _T_86; // @[alu.scala 51:57:@540.4]
+  wire [32:0] _T_87; // @[alu.scala 51:64:@541.4]
+  wire [31:0] shiftr; // @[alu.scala 51:73:@542.4]
+  wire [15:0] _T_92; // @[Bitwise.scala 103:21:@545.4]
+  wire [31:0] _T_93; // @[Bitwise.scala 103:31:@546.4]
+  wire [15:0] _T_94; // @[Bitwise.scala 103:46:@547.4]
+  wire [31:0] _GEN_9; // @[Bitwise.scala 103:65:@548.4]
+  wire [31:0] _T_95; // @[Bitwise.scala 103:65:@548.4]
+  wire [31:0] _T_97; // @[Bitwise.scala 103:75:@550.4]
+  wire [31:0] _T_98; // @[Bitwise.scala 103:39:@551.4]
+  wire [23:0] _T_102; // @[Bitwise.scala 103:21:@555.4]
+  wire [31:0] _GEN_10; // @[Bitwise.scala 103:31:@556.4]
+  wire [31:0] _T_103; // @[Bitwise.scala 103:31:@556.4]
+  wire [23:0] _T_104; // @[Bitwise.scala 103:46:@557.4]
+  wire [31:0] _GEN_11; // @[Bitwise.scala 103:65:@558.4]
+  wire [31:0] _T_105; // @[Bitwise.scala 103:65:@558.4]
+  wire [31:0] _T_107; // @[Bitwise.scala 103:75:@560.4]
+  wire [31:0] _T_108; // @[Bitwise.scala 103:39:@561.4]
+  wire [27:0] _T_112; // @[Bitwise.scala 103:21:@565.4]
+  wire [31:0] _GEN_12; // @[Bitwise.scala 103:31:@566.4]
+  wire [31:0] _T_113; // @[Bitwise.scala 103:31:@566.4]
+  wire [27:0] _T_114; // @[Bitwise.scala 103:46:@567.4]
+  wire [31:0] _GEN_13; // @[Bitwise.scala 103:65:@568.4]
+  wire [31:0] _T_115; // @[Bitwise.scala 103:65:@568.4]
+  wire [31:0] _T_117; // @[Bitwise.scala 103:75:@570.4]
+  wire [31:0] _T_118; // @[Bitwise.scala 103:39:@571.4]
+  wire [29:0] _T_122; // @[Bitwise.scala 103:21:@575.4]
+  wire [31:0] _GEN_14; // @[Bitwise.scala 103:31:@576.4]
+  wire [31:0] _T_123; // @[Bitwise.scala 103:31:@576.4]
+  wire [29:0] _T_124; // @[Bitwise.scala 103:46:@577.4]
+  wire [31:0] _GEN_15; // @[Bitwise.scala 103:65:@578.4]
+  wire [31:0] _T_125; // @[Bitwise.scala 103:65:@578.4]
+  wire [31:0] _T_127; // @[Bitwise.scala 103:75:@580.4]
+  wire [31:0] _T_128; // @[Bitwise.scala 103:39:@581.4]
+  wire [30:0] _T_132; // @[Bitwise.scala 103:21:@585.4]
+  wire [31:0] _GEN_16; // @[Bitwise.scala 103:31:@586.4]
+  wire [31:0] _T_133; // @[Bitwise.scala 103:31:@586.4]
+  wire [30:0] _T_134; // @[Bitwise.scala 103:46:@587.4]
+  wire [31:0] _GEN_17; // @[Bitwise.scala 103:65:@588.4]
+  wire [31:0] _T_135; // @[Bitwise.scala 103:65:@588.4]
+  wire [31:0] _T_137; // @[Bitwise.scala 103:75:@590.4]
+  wire [31:0] shiftl; // @[Bitwise.scala 103:39:@591.4]
+  wire  _T_151; // @[alu.scala 55:19:@592.4]
+  wire  _T_152; // @[alu.scala 55:44:@593.4]
+  wire  _T_153; // @[alu.scala 55:31:@594.4]
+  wire  _T_154; // @[alu.scala 56:19:@595.4]
+  wire  _T_155; // @[alu.scala 56:44:@596.4]
+  wire  _T_156; // @[alu.scala 56:31:@597.4]
+  wire  _T_157; // @[alu.scala 57:19:@598.4]
+  wire  _T_158; // @[alu.scala 57:44:@599.4]
+  wire  _T_159; // @[alu.scala 57:31:@600.4]
+  wire  _T_160; // @[alu.scala 58:19:@601.4]
+  wire  _T_161; // @[alu.scala 59:19:@602.4]
+  wire [31:0] _T_162; // @[alu.scala 59:41:@603.4]
+  wire  _T_163; // @[alu.scala 60:19:@604.4]
+  wire [31:0] _T_164; // @[alu.scala 60:41:@605.4]
+  wire  _T_165; // @[alu.scala 61:19:@606.4]
+  wire [31:0] _T_166; // @[alu.scala 61:41:@607.4]
+  wire  _T_167; // @[alu.scala 62:19:@608.4]
+  wire [31:0] _T_168; // @[alu.scala 62:8:@609.4]
+  wire [31:0] _T_169; // @[alu.scala 61:8:@610.4]
+  wire [31:0] _T_170; // @[alu.scala 60:8:@611.4]
+  wire [31:0] _T_171; // @[alu.scala 59:8:@612.4]
+  wire [31:0] _T_172; // @[alu.scala 58:8:@613.4]
+  wire [31:0] _T_173; // @[alu.scala 57:8:@614.4]
+  wire [31:0] _T_174; // @[alu.scala 56:8:@615.4]
+  assign _T_15 = io_alu_op[0]; // @[alu.scala 46:39:@468.4]
+  assign _T_17 = 32'h0 - io_in_b; // @[alu.scala 46:44:@469.4]
+  assign _T_18 = $unsigned(_T_17); // @[alu.scala 46:44:@470.4]
+  assign _T_19 = _T_18[31:0]; // @[alu.scala 46:44:@471.4]
+  assign _T_20 = _T_15 ? _T_19 : io_in_b; // @[alu.scala 46:29:@472.4]
+  assign _T_21 = io_in_a + _T_20; // @[alu.scala 46:24:@473.4]
+  assign sum = io_in_a + _T_20; // @[alu.scala 46:24:@474.4]
+  assign _T_22 = io_in_a[31]; // @[alu.scala 47:28:@475.4]
+  assign _T_23 = io_in_b[31]; // @[alu.scala 47:48:@476.4]
+  assign _T_24 = _T_22 == _T_23; // @[alu.scala 47:37:@477.4]
+  assign _T_25 = sum[31]; // @[alu.scala 47:61:@478.4]
+  assign _T_26 = io_alu_op[1]; // @[alu.scala 48:33:@479.4]
+  assign _T_29 = _T_26 ? _T_23 : _T_22; // @[alu.scala 48:23:@482.4]
+  assign cmp = _T_24 ? _T_25 : _T_29; // @[alu.scala 47:19:@483.4]
+  assign shamt = io_in_b[4:0]; // @[alu.scala 49:23:@484.4]
+  assign _T_30 = io_alu_op[3]; // @[alu.scala 50:29:@485.4]
+  assign _T_35 = io_in_a[31:16]; // @[Bitwise.scala 103:21:@488.4]
+  assign _T_36 = {{16'd0}, _T_35}; // @[Bitwise.scala 103:31:@489.4]
+  assign _T_37 = io_in_a[15:0]; // @[Bitwise.scala 103:46:@490.4]
+  assign _GEN_0 = {{16'd0}, _T_37}; // @[Bitwise.scala 103:65:@491.4]
+  assign _T_38 = _GEN_0 << 16; // @[Bitwise.scala 103:65:@491.4]
+  assign _T_40 = _T_38 & 32'hffff0000; // @[Bitwise.scala 103:75:@493.4]
+  assign _T_41 = _T_36 | _T_40; // @[Bitwise.scala 103:39:@494.4]
+  assign _T_45 = _T_41[31:8]; // @[Bitwise.scala 103:21:@498.4]
+  assign _GEN_1 = {{8'd0}, _T_45}; // @[Bitwise.scala 103:31:@499.4]
+  assign _T_46 = _GEN_1 & 32'hff00ff; // @[Bitwise.scala 103:31:@499.4]
+  assign _T_47 = _T_41[23:0]; // @[Bitwise.scala 103:46:@500.4]
+  assign _GEN_2 = {{8'd0}, _T_47}; // @[Bitwise.scala 103:65:@501.4]
+  assign _T_48 = _GEN_2 << 8; // @[Bitwise.scala 103:65:@501.4]
+  assign _T_50 = _T_48 & 32'hff00ff00; // @[Bitwise.scala 103:75:@503.4]
+  assign _T_51 = _T_46 | _T_50; // @[Bitwise.scala 103:39:@504.4]
+  assign _T_55 = _T_51[31:4]; // @[Bitwise.scala 103:21:@508.4]
+  assign _GEN_3 = {{4'd0}, _T_55}; // @[Bitwise.scala 103:31:@509.4]
+  assign _T_56 = _GEN_3 & 32'hf0f0f0f; // @[Bitwise.scala 103:31:@509.4]
+  assign _T_57 = _T_51[27:0]; // @[Bitwise.scala 103:46:@510.4]
+  assign _GEN_4 = {{4'd0}, _T_57}; // @[Bitwise.scala 103:65:@511.4]
+  assign _T_58 = _GEN_4 << 4; // @[Bitwise.scala 103:65:@511.4]
+  assign _T_60 = _T_58 & 32'hf0f0f0f0; // @[Bitwise.scala 103:75:@513.4]
+  assign _T_61 = _T_56 | _T_60; // @[Bitwise.scala 103:39:@514.4]
+  assign _T_65 = _T_61[31:2]; // @[Bitwise.scala 103:21:@518.4]
+  assign _GEN_5 = {{2'd0}, _T_65}; // @[Bitwise.scala 103:31:@519.4]
+  assign _T_66 = _GEN_5 & 32'h33333333; // @[Bitwise.scala 103:31:@519.4]
+  assign _T_67 = _T_61[29:0]; // @[Bitwise.scala 103:46:@520.4]
+  assign _GEN_6 = {{2'd0}, _T_67}; // @[Bitwise.scala 103:65:@521.4]
+  assign _T_68 = _GEN_6 << 2; // @[Bitwise.scala 103:65:@521.4]
+  assign _T_70 = _T_68 & 32'hcccccccc; // @[Bitwise.scala 103:75:@523.4]
+  assign _T_71 = _T_66 | _T_70; // @[Bitwise.scala 103:39:@524.4]
+  assign _T_75 = _T_71[31:1]; // @[Bitwise.scala 103:21:@528.4]
+  assign _GEN_7 = {{1'd0}, _T_75}; // @[Bitwise.scala 103:31:@529.4]
+  assign _T_76 = _GEN_7 & 32'h55555555; // @[Bitwise.scala 103:31:@529.4]
+  assign _T_77 = _T_71[30:0]; // @[Bitwise.scala 103:46:@530.4]
+  assign _GEN_8 = {{1'd0}, _T_77}; // @[Bitwise.scala 103:65:@531.4]
+  assign _T_78 = _GEN_8 << 1; // @[Bitwise.scala 103:65:@531.4]
+  assign _T_80 = _T_78 & 32'haaaaaaaa; // @[Bitwise.scala 103:75:@533.4]
+  assign _T_81 = _T_76 | _T_80; // @[Bitwise.scala 103:39:@534.4]
+  assign shin = _T_30 ? io_in_a : _T_81; // @[alu.scala 50:19:@535.4]
+  assign _T_83 = shin[31]; // @[alu.scala 51:41:@537.4]
+  assign _T_84 = _T_15 & _T_83; // @[alu.scala 51:34:@538.4]
+  assign _T_85 = {_T_84,shin}; // @[Cat.scala 30:58:@539.4]
+  assign _T_86 = $signed(_T_85); // @[alu.scala 51:57:@540.4]
+  assign _T_87 = $signed(_T_86) >>> shamt; // @[alu.scala 51:64:@541.4]
+  assign shiftr = _T_87[31:0]; // @[alu.scala 51:73:@542.4]
+  assign _T_92 = shiftr[31:16]; // @[Bitwise.scala 103:21:@545.4]
+  assign _T_93 = {{16'd0}, _T_92}; // @[Bitwise.scala 103:31:@546.4]
+  assign _T_94 = shiftr[15:0]; // @[Bitwise.scala 103:46:@547.4]
+  assign _GEN_9 = {{16'd0}, _T_94}; // @[Bitwise.scala 103:65:@548.4]
+  assign _T_95 = _GEN_9 << 16; // @[Bitwise.scala 103:65:@548.4]
+  assign _T_97 = _T_95 & 32'hffff0000; // @[Bitwise.scala 103:75:@550.4]
+  assign _T_98 = _T_93 | _T_97; // @[Bitwise.scala 103:39:@551.4]
+  assign _T_102 = _T_98[31:8]; // @[Bitwise.scala 103:21:@555.4]
+  assign _GEN_10 = {{8'd0}, _T_102}; // @[Bitwise.scala 103:31:@556.4]
+  assign _T_103 = _GEN_10 & 32'hff00ff; // @[Bitwise.scala 103:31:@556.4]
+  assign _T_104 = _T_98[23:0]; // @[Bitwise.scala 103:46:@557.4]
+  assign _GEN_11 = {{8'd0}, _T_104}; // @[Bitwise.scala 103:65:@558.4]
+  assign _T_105 = _GEN_11 << 8; // @[Bitwise.scala 103:65:@558.4]
+  assign _T_107 = _T_105 & 32'hff00ff00; // @[Bitwise.scala 103:75:@560.4]
+  assign _T_108 = _T_103 | _T_107; // @[Bitwise.scala 103:39:@561.4]
+  assign _T_112 = _T_108[31:4]; // @[Bitwise.scala 103:21:@565.4]
+  assign _GEN_12 = {{4'd0}, _T_112}; // @[Bitwise.scala 103:31:@566.4]
+  assign _T_113 = _GEN_12 & 32'hf0f0f0f; // @[Bitwise.scala 103:31:@566.4]
+  assign _T_114 = _T_108[27:0]; // @[Bitwise.scala 103:46:@567.4]
+  assign _GEN_13 = {{4'd0}, _T_114}; // @[Bitwise.scala 103:65:@568.4]
+  assign _T_115 = _GEN_13 << 4; // @[Bitwise.scala 103:65:@568.4]
+  assign _T_117 = _T_115 & 32'hf0f0f0f0; // @[Bitwise.scala 103:75:@570.4]
+  assign _T_118 = _T_113 | _T_117; // @[Bitwise.scala 103:39:@571.4]
+  assign _T_122 = _T_118[31:2]; // @[Bitwise.scala 103:21:@575.4]
+  assign _GEN_14 = {{2'd0}, _T_122}; // @[Bitwise.scala 103:31:@576.4]
+  assign _T_123 = _GEN_14 & 32'h33333333; // @[Bitwise.scala 103:31:@576.4]
+  assign _T_124 = _T_118[29:0]; // @[Bitwise.scala 103:46:@577.4]
+  assign _GEN_15 = {{2'd0}, _T_124}; // @[Bitwise.scala 103:65:@578.4]
+  assign _T_125 = _GEN_15 << 2; // @[Bitwise.scala 103:65:@578.4]
+  assign _T_127 = _T_125 & 32'hcccccccc; // @[Bitwise.scala 103:75:@580.4]
+  assign _T_128 = _T_123 | _T_127; // @[Bitwise.scala 103:39:@581.4]
+  assign _T_132 = _T_128[31:1]; // @[Bitwise.scala 103:21:@585.4]
+  assign _GEN_16 = {{1'd0}, _T_132}; // @[Bitwise.scala 103:31:@586.4]
+  assign _T_133 = _GEN_16 & 32'h55555555; // @[Bitwise.scala 103:31:@586.4]
+  assign _T_134 = _T_128[30:0]; // @[Bitwise.scala 103:46:@587.4]
+  assign _GEN_17 = {{1'd0}, _T_134}; // @[Bitwise.scala 103:65:@588.4]
+  assign _T_135 = _GEN_17 << 1; // @[Bitwise.scala 103:65:@588.4]
+  assign _T_137 = _T_135 & 32'haaaaaaaa; // @[Bitwise.scala 103:75:@590.4]
+  assign shiftl = _T_133 | _T_137; // @[Bitwise.scala 103:39:@591.4]
+  assign _T_151 = io_alu_op == 4'h0; // @[alu.scala 55:19:@592.4]
+  assign _T_152 = io_alu_op == 4'h1; // @[alu.scala 55:44:@593.4]
+  assign _T_153 = _T_151 | _T_152; // @[alu.scala 55:31:@594.4]
+  assign _T_154 = io_alu_op == 4'h5; // @[alu.scala 56:19:@595.4]
+  assign _T_155 = io_alu_op == 4'h7; // @[alu.scala 56:44:@596.4]
+  assign _T_156 = _T_154 | _T_155; // @[alu.scala 56:31:@597.4]
+  assign _T_157 = io_alu_op == 4'h9; // @[alu.scala 57:19:@598.4]
+  assign _T_158 = io_alu_op == 4'h8; // @[alu.scala 57:44:@599.4]
+  assign _T_159 = _T_157 | _T_158; // @[alu.scala 57:31:@600.4]
+  assign _T_160 = io_alu_op == 4'h6; // @[alu.scala 58:19:@601.4]
+  assign _T_161 = io_alu_op == 4'h2; // @[alu.scala 59:19:@602.4]
+  assign _T_162 = io_in_a & io_in_b; // @[alu.scala 59:41:@603.4]
+  assign _T_163 = io_alu_op == 4'h3; // @[alu.scala 60:19:@604.4]
+  assign _T_164 = io_in_a | io_in_b; // @[alu.scala 60:41:@605.4]
+  assign _T_165 = io_alu_op == 4'h4; // @[alu.scala 61:19:@606.4]
+  assign _T_166 = io_in_a ^ io_in_b; // @[alu.scala 61:41:@607.4]
+  assign _T_167 = io_alu_op == 4'ha; // @[alu.scala 62:19:@608.4]
+  assign _T_168 = _T_167 ? io_in_a : io_in_b; // @[alu.scala 62:8:@609.4]
+  assign _T_169 = _T_165 ? _T_166 : _T_168; // @[alu.scala 61:8:@610.4]
+  assign _T_170 = _T_163 ? _T_164 : _T_169; // @[alu.scala 60:8:@611.4]
+  assign _T_171 = _T_161 ? _T_162 : _T_170; // @[alu.scala 59:8:@612.4]
+  assign _T_172 = _T_160 ? shiftl : _T_171; // @[alu.scala 58:8:@613.4]
+  assign _T_173 = _T_159 ? shiftr : _T_172; // @[alu.scala 57:8:@614.4]
+  assign _T_174 = _T_156 ? {{31'd0}, cmp} : _T_173; // @[alu.scala 56:8:@615.4]
+  assign io_out = _T_153 ? sum : _T_174; // @[alu.scala 64:10:@617.4]
+  assign io_sum = io_in_a + _T_20; // @[alu.scala 65:10:@618.4]
+endmodule
+module ImmGen( // @[:@620.2]
+  input  [31:0] io_inst, // @[:@623.4]
+  input  [2:0]  io_sel, // @[:@623.4]
+  output [31:0] io_out // @[:@623.4]
+);
+  wire  _T_11; // @[imm_gen.scala 26:25:@625.4]
+  wire  _T_13; // @[imm_gen.scala 26:48:@626.4]
+  wire  _T_14; // @[imm_gen.scala 26:53:@627.4]
+  wire  sign; // @[imm_gen.scala 26:17:@628.4]
+  wire  _T_15; // @[imm_gen.scala 27:27:@629.4]
+  wire [10:0] _T_16; // @[imm_gen.scala 27:45:@630.4]
+  wire [10:0] _T_17; // @[imm_gen.scala 27:53:@631.4]
+  wire [10:0] b30_20; // @[imm_gen.scala 27:19:@632.4]
+  wire  _T_18; // @[imm_gen.scala 28:27:@633.4]
+  wire  _T_19; // @[imm_gen.scala 28:47:@634.4]
+  wire  _T_20; // @[imm_gen.scala 28:37:@635.4]
+  wire [7:0] _T_21; // @[imm_gen.scala 28:71:@636.4]
+  wire [7:0] _T_22; // @[imm_gen.scala 28:79:@637.4]
+  wire [7:0] b19_12; // @[imm_gen.scala 28:19:@638.4]
+  wire  _T_25; // @[imm_gen.scala 29:34:@641.4]
+  wire  _T_27; // @[imm_gen.scala 30:24:@642.4]
+  wire  _T_28; // @[imm_gen.scala 30:42:@643.4]
+  wire  _T_29; // @[imm_gen.scala 30:47:@644.4]
+  wire  _T_30; // @[imm_gen.scala 31:24:@645.4]
+  wire  _T_31; // @[imm_gen.scala 31:42:@646.4]
+  wire  _T_32; // @[imm_gen.scala 31:46:@647.4]
+  wire  _T_33; // @[imm_gen.scala 31:16:@648.4]
+  wire  _T_34; // @[imm_gen.scala 30:16:@649.4]
+  wire  b11; // @[imm_gen.scala 29:16:@650.4]
+  wire [5:0] _T_39; // @[imm_gen.scala 32:69:@654.4]
+  wire [5:0] b10_5; // @[imm_gen.scala 32:18:@655.4]
+  wire  _T_42; // @[imm_gen.scala 34:25:@657.4]
+  wire  _T_44; // @[imm_gen.scala 34:35:@659.4]
+  wire [3:0] _T_45; // @[imm_gen.scala 34:63:@660.4]
+  wire [3:0] _T_47; // @[imm_gen.scala 35:43:@662.4]
+  wire [3:0] _T_48; // @[imm_gen.scala 35:59:@663.4]
+  wire [3:0] _T_49; // @[imm_gen.scala 35:17:@664.4]
+  wire [3:0] _T_50; // @[imm_gen.scala 34:17:@665.4]
+  wire [3:0] b4_1; // @[imm_gen.scala 33:17:@666.4]
+  wire  _T_53; // @[imm_gen.scala 37:23:@669.4]
+  wire  _T_56; // @[imm_gen.scala 38:41:@672.4]
+  wire  _T_58; // @[imm_gen.scala 38:15:@673.4]
+  wire  _T_59; // @[imm_gen.scala 37:15:@674.4]
+  wire  b0; // @[imm_gen.scala 36:15:@675.4]
+  wire  _T_62; // @[Cat.scala 30:58:@678.4]
+  wire [7:0] _T_63; // @[Cat.scala 30:58:@679.4]
+  wire [10:0] _T_65; // @[Cat.scala 30:58:@681.4]
+  wire  _T_66; // @[Cat.scala 30:58:@682.4]
+  wire [31:0] _T_69; // @[Cat.scala 30:58:@685.4]
+  wire [31:0] _T_70; // @[imm_gen.scala 40:61:@686.4]
+  assign _T_11 = io_sel == 3'h6; // @[imm_gen.scala 26:25:@625.4]
+  assign _T_13 = io_inst[31]; // @[imm_gen.scala 26:48:@626.4]
+  assign _T_14 = $signed(_T_13); // @[imm_gen.scala 26:53:@627.4]
+  assign sign = _T_11 ? $signed(1'sh0) : $signed(_T_14); // @[imm_gen.scala 26:17:@628.4]
+  assign _T_15 = io_sel == 3'h3; // @[imm_gen.scala 27:27:@629.4]
+  assign _T_16 = io_inst[30:20]; // @[imm_gen.scala 27:45:@630.4]
+  assign _T_17 = $signed(_T_16); // @[imm_gen.scala 27:53:@631.4]
+  assign b30_20 = _T_15 ? $signed(_T_17) : $signed({11{sign}}); // @[imm_gen.scala 27:19:@632.4]
+  assign _T_18 = io_sel != 3'h3; // @[imm_gen.scala 28:27:@633.4]
+  assign _T_19 = io_sel != 3'h4; // @[imm_gen.scala 28:47:@634.4]
+  assign _T_20 = _T_18 & _T_19; // @[imm_gen.scala 28:37:@635.4]
+  assign _T_21 = io_inst[19:12]; // @[imm_gen.scala 28:71:@636.4]
+  assign _T_22 = $signed(_T_21); // @[imm_gen.scala 28:79:@637.4]
+  assign b19_12 = _T_20 ? $signed({8{sign}}) : $signed(_T_22); // @[imm_gen.scala 28:19:@638.4]
+  assign _T_25 = _T_15 | _T_11; // @[imm_gen.scala 29:34:@641.4]
+  assign _T_27 = io_sel == 3'h4; // @[imm_gen.scala 30:24:@642.4]
+  assign _T_28 = io_inst[20]; // @[imm_gen.scala 30:42:@643.4]
+  assign _T_29 = $signed(_T_28); // @[imm_gen.scala 30:47:@644.4]
+  assign _T_30 = io_sel == 3'h5; // @[imm_gen.scala 31:24:@645.4]
+  assign _T_31 = io_inst[7]; // @[imm_gen.scala 31:42:@646.4]
+  assign _T_32 = $signed(_T_31); // @[imm_gen.scala 31:46:@647.4]
+  assign _T_33 = _T_30 ? $signed(_T_32) : $signed(sign); // @[imm_gen.scala 31:16:@648.4]
+  assign _T_34 = _T_27 ? $signed(_T_29) : $signed(_T_33); // @[imm_gen.scala 30:16:@649.4]
+  assign b11 = _T_25 ? $signed(1'sh0) : $signed(_T_34); // @[imm_gen.scala 29:16:@650.4]
+  assign _T_39 = io_inst[30:25]; // @[imm_gen.scala 32:69:@654.4]
+  assign b10_5 = _T_25 ? 6'h0 : _T_39; // @[imm_gen.scala 32:18:@655.4]
+  assign _T_42 = io_sel == 3'h2; // @[imm_gen.scala 34:25:@657.4]
+  assign _T_44 = _T_42 | _T_30; // @[imm_gen.scala 34:35:@659.4]
+  assign _T_45 = io_inst[11:8]; // @[imm_gen.scala 34:63:@660.4]
+  assign _T_47 = io_inst[19:16]; // @[imm_gen.scala 35:43:@662.4]
+  assign _T_48 = io_inst[24:21]; // @[imm_gen.scala 35:59:@663.4]
+  assign _T_49 = _T_11 ? _T_47 : _T_48; // @[imm_gen.scala 35:17:@664.4]
+  assign _T_50 = _T_44 ? _T_45 : _T_49; // @[imm_gen.scala 34:17:@665.4]
+  assign b4_1 = _T_15 ? 4'h0 : _T_50; // @[imm_gen.scala 33:17:@666.4]
+  assign _T_53 = io_sel == 3'h1; // @[imm_gen.scala 37:23:@669.4]
+  assign _T_56 = io_inst[15]; // @[imm_gen.scala 38:41:@672.4]
+  assign _T_58 = _T_11 ? _T_56 : 1'h0; // @[imm_gen.scala 38:15:@673.4]
+  assign _T_59 = _T_53 ? _T_28 : _T_58; // @[imm_gen.scala 37:15:@674.4]
+  assign b0 = _T_42 ? _T_31 : _T_59; // @[imm_gen.scala 36:15:@675.4]
+  assign _T_62 = $unsigned(b11); // @[Cat.scala 30:58:@678.4]
+  assign _T_63 = $unsigned(b19_12); // @[Cat.scala 30:58:@679.4]
+  assign _T_65 = $unsigned(b30_20); // @[Cat.scala 30:58:@681.4]
+  assign _T_66 = $unsigned(sign); // @[Cat.scala 30:58:@682.4]
+  assign _T_69 = {_T_66,_T_65,_T_63,_T_62,b10_5,b4_1,b0}; // @[Cat.scala 30:58:@685.4]
+  assign _T_70 = $signed(_T_69); // @[imm_gen.scala 40:61:@686.4]
+  assign io_out = $unsigned(_T_70); // @[imm_gen.scala 40:10:@688.4]
+endmodule
+module Branch( // @[:@690.2]
+  input  [31:0] io_rs1, // @[:@693.4]
+  input  [31:0] io_rs2, // @[:@693.4]
+  input  [2:0]  io_br_type, // @[:@693.4]
+  output        io_taken // @[:@693.4]
+);
+  wire [32:0] _T_13; // @[branch.scala 24:29:@695.4]
+  wire [32:0] _T_14; // @[branch.scala 24:29:@696.4]
+  wire [31:0] diff; // @[branch.scala 24:29:@697.4]
+  wire  neq; // @[branch.scala 25:27:@698.4]
+  wire  eq; // @[branch.scala 26:22:@699.4]
+  wire  _T_17; // @[branch.scala 27:28:@700.4]
+  wire  _T_18; // @[branch.scala 27:47:@701.4]
+  wire  is_same_sign; // @[branch.scala 27:37:@702.4]
+  wire  _T_19; // @[branch.scala 28:44:@703.4]
+  wire  lt; // @[branch.scala 28:25:@705.4]
+  wire  ltu; // @[branch.scala 29:25:@708.4]
+  wire  ge; // @[branch.scala 30:22:@709.4]
+  wire  geu; // @[branch.scala 31:22:@710.4]
+  wire  _T_25; // @[branch.scala 35:18:@711.4]
+  wire  _T_26; // @[branch.scala 35:29:@712.4]
+  wire  _T_27; // @[branch.scala 36:18:@713.4]
+  wire  _T_28; // @[branch.scala 36:29:@714.4]
+  wire  _T_29; // @[branch.scala 35:36:@715.4]
+  wire  _T_30; // @[branch.scala 37:18:@716.4]
+  wire  _T_31; // @[branch.scala 37:29:@717.4]
+  wire  _T_32; // @[branch.scala 36:37:@718.4]
+  wire  _T_33; // @[branch.scala 38:18:@719.4]
+  wire  _T_34; // @[branch.scala 38:29:@720.4]
+  wire  _T_35; // @[branch.scala 37:36:@721.4]
+  wire  _T_36; // @[branch.scala 39:18:@722.4]
+  wire  _T_37; // @[branch.scala 39:30:@723.4]
+  wire  _T_38; // @[branch.scala 38:36:@724.4]
+  wire  _T_39; // @[branch.scala 40:18:@725.4]
+  wire  _T_40; // @[branch.scala 40:30:@726.4]
+  assign _T_13 = io_rs1 - io_rs2; // @[branch.scala 24:29:@695.4]
+  assign _T_14 = $unsigned(_T_13); // @[branch.scala 24:29:@696.4]
+  assign diff = _T_14[31:0]; // @[branch.scala 24:29:@697.4]
+  assign neq = diff != 32'h0; // @[branch.scala 25:27:@698.4]
+  assign eq = neq == 1'h0; // @[branch.scala 26:22:@699.4]
+  assign _T_17 = io_rs1[31]; // @[branch.scala 27:28:@700.4]
+  assign _T_18 = io_rs2[31]; // @[branch.scala 27:47:@701.4]
+  assign is_same_sign = _T_17 == _T_18; // @[branch.scala 27:37:@702.4]
+  assign _T_19 = diff[31]; // @[branch.scala 28:44:@703.4]
+  assign lt = is_same_sign ? _T_19 : _T_17; // @[branch.scala 28:25:@705.4]
+  assign ltu = is_same_sign ? _T_19 : _T_18; // @[branch.scala 29:25:@708.4]
+  assign ge = lt == 1'h0; // @[branch.scala 30:22:@709.4]
+  assign geu = ltu == 1'h0; // @[branch.scala 31:22:@710.4]
+  assign _T_25 = io_br_type == 3'h3; // @[branch.scala 35:18:@711.4]
+  assign _T_26 = _T_25 & eq; // @[branch.scala 35:29:@712.4]
+  assign _T_27 = io_br_type == 3'h6; // @[branch.scala 36:18:@713.4]
+  assign _T_28 = _T_27 & neq; // @[branch.scala 36:29:@714.4]
+  assign _T_29 = _T_26 | _T_28; // @[branch.scala 35:36:@715.4]
+  assign _T_30 = io_br_type == 3'h2; // @[branch.scala 37:18:@716.4]
+  assign _T_31 = _T_30 & lt; // @[branch.scala 37:29:@717.4]
+  assign _T_32 = _T_29 | _T_31; // @[branch.scala 36:37:@718.4]
+  assign _T_33 = io_br_type == 3'h5; // @[branch.scala 38:18:@719.4]
+  assign _T_34 = _T_33 & ge; // @[branch.scala 38:29:@720.4]
+  assign _T_35 = _T_32 | _T_34; // @[branch.scala 37:36:@721.4]
+  assign _T_36 = io_br_type == 3'h1; // @[branch.scala 39:18:@722.4]
+  assign _T_37 = _T_36 & ltu; // @[branch.scala 39:30:@723.4]
+  assign _T_38 = _T_35 | _T_37; // @[branch.scala 38:36:@724.4]
+  assign _T_39 = io_br_type == 3'h4; // @[branch.scala 40:18:@725.4]
+  assign _T_40 = _T_39 & geu; // @[branch.scala 40:30:@726.4]
+  assign io_taken = _T_38 | _T_40; // @[branch.scala 34:12:@728.4]
+endmodule
+module LS_Unit( // @[:@730.2]
+  input  [1:0]  io_lsu_st_type, // @[:@733.4]
+  input  [31:0] io_lsu_wdata_in, // @[:@733.4]
+  output [31:0] io_lsu_wdata_out, // @[:@733.4]
+  input  [31:0] io_lsu_rdata_in, // @[:@733.4]
+  output [31:0] io_lsu_rdata_out, // @[:@733.4]
+  input  [2:0]  io_lsu_ld_type // @[:@733.4]
+);
+  wire [15:0] _T_18; // @[ls_unit.scala 34:31:@735.4]
+  wire [7:0] _T_19; // @[ls_unit.scala 35:31:@736.4]
+  wire  _T_20; // @[Mux.scala 46:19:@737.4]
+  wire [7:0] _T_21; // @[Mux.scala 46:16:@738.4]
+  wire  _T_22; // @[Mux.scala 46:19:@739.4]
+  wire [15:0] _T_23; // @[Mux.scala 46:16:@740.4]
+  wire  _T_24; // @[Mux.scala 46:19:@741.4]
+  wire [32:0] _T_27; // @[ls_unit.scala 40:29:@744.4]
+  wire [15:0] _T_28; // @[ls_unit.scala 41:28:@745.4]
+  wire [15:0] _T_29; // @[ls_unit.scala 41:36:@746.4]
+  wire [7:0] _T_30; // @[ls_unit.scala 42:28:@747.4]
+  wire [7:0] _T_31; // @[ls_unit.scala 42:35:@748.4]
+  wire [16:0] _T_33; // @[ls_unit.scala 43:36:@750.4]
+  wire [8:0] _T_35; // @[ls_unit.scala 44:35:@752.4]
+  wire  _T_36; // @[Mux.scala 46:19:@753.4]
+  wire [8:0] _T_37; // @[Mux.scala 46:16:@754.4]
+  wire  _T_38; // @[Mux.scala 46:19:@755.4]
+  wire [16:0] _T_39; // @[Mux.scala 46:16:@756.4]
+  wire  _T_40; // @[Mux.scala 46:19:@757.4]
+  wire [16:0] _T_41; // @[Mux.scala 46:16:@758.4]
+  wire  _T_42; // @[Mux.scala 46:19:@759.4]
+  wire [16:0] _T_43; // @[Mux.scala 46:16:@760.4]
+  wire  _T_44; // @[Mux.scala 46:19:@761.4]
+  wire [32:0] _T_45; // @[Mux.scala 46:16:@762.4]
+  wire [31:0] _GEN_0; // @[ls_unit.scala 39:21:@763.4]
+  assign _T_18 = io_lsu_wdata_in[15:0]; // @[ls_unit.scala 34:31:@735.4]
+  assign _T_19 = io_lsu_wdata_in[7:0]; // @[ls_unit.scala 35:31:@736.4]
+  assign _T_20 = 2'h3 == io_lsu_st_type; // @[Mux.scala 46:19:@737.4]
+  assign _T_21 = _T_20 ? _T_19 : 8'h0; // @[Mux.scala 46:16:@738.4]
+  assign _T_22 = 2'h2 == io_lsu_st_type; // @[Mux.scala 46:19:@739.4]
+  assign _T_23 = _T_22 ? _T_18 : {{8'd0}, _T_21}; // @[Mux.scala 46:16:@740.4]
+  assign _T_24 = 2'h1 == io_lsu_st_type; // @[Mux.scala 46:19:@741.4]
+  assign _T_27 = {1'b0,$signed(io_lsu_rdata_in)}; // @[ls_unit.scala 40:29:@744.4]
+  assign _T_28 = io_lsu_rdata_in[15:0]; // @[ls_unit.scala 41:28:@745.4]
+  assign _T_29 = $signed(_T_28); // @[ls_unit.scala 41:36:@746.4]
+  assign _T_30 = io_lsu_rdata_in[7:0]; // @[ls_unit.scala 42:28:@747.4]
+  assign _T_31 = $signed(_T_30); // @[ls_unit.scala 42:35:@748.4]
+  assign _T_33 = {1'b0,$signed(_T_28)}; // @[ls_unit.scala 43:36:@750.4]
+  assign _T_35 = {1'b0,$signed(_T_30)}; // @[ls_unit.scala 44:35:@752.4]
+  assign _T_36 = 3'h5 == io_lsu_ld_type; // @[Mux.scala 46:19:@753.4]
+  assign _T_37 = _T_36 ? $signed(_T_35) : $signed(9'sh0); // @[Mux.scala 46:16:@754.4]
+  assign _T_38 = 3'h4 == io_lsu_ld_type; // @[Mux.scala 46:19:@755.4]
+  assign _T_39 = _T_38 ? $signed(_T_33) : $signed({{8{_T_37[8]}},_T_37}); // @[Mux.scala 46:16:@756.4]
+  assign _T_40 = 3'h3 == io_lsu_ld_type; // @[Mux.scala 46:19:@757.4]
+  assign _T_41 = _T_40 ? $signed({{9{_T_31[7]}},_T_31}) : $signed(_T_39); // @[Mux.scala 46:16:@758.4]
+  assign _T_42 = 3'h2 == io_lsu_ld_type; // @[Mux.scala 46:19:@759.4]
+  assign _T_43 = _T_42 ? $signed({{1{_T_29[15]}},_T_29}) : $signed(_T_41); // @[Mux.scala 46:16:@760.4]
+  assign _T_44 = 3'h1 == io_lsu_ld_type; // @[Mux.scala 46:19:@761.4]
+  assign _T_45 = _T_44 ? $signed(_T_27) : $signed({{16{_T_43[16]}},_T_43}); // @[Mux.scala 46:16:@762.4]
+  assign io_lsu_wdata_out = _T_24 ? io_lsu_wdata_in : {{16'd0}, _T_23}; // @[ls_unit.scala 32:20:@743.4]
+  assign _GEN_0 = _T_45[31:0]; // @[ls_unit.scala 39:21:@763.4]
+  assign io_lsu_rdata_out = $signed(_GEN_0); // @[ls_unit.scala 39:21:@763.4]
+endmodule
+module Datapath( // @[:@765.2]
+  input         clock, // @[:@766.4]
+  input         reset, // @[:@767.4]
+  input         io_irq_uart_irq, // @[:@768.4]
+  input         io_irq_spi_irq, // @[:@768.4]
+  input         io_irq_motor_irq, // @[:@768.4]
+  output [31:0] io_ibus_addr, // @[:@768.4]
+  input  [31:0] io_ibus_inst, // @[:@768.4]
+  input         io_ibus_valid, // @[:@768.4]
+  output [31:0] io_dbus_addr, // @[:@768.4]
+  output [31:0] io_dbus_wdata, // @[:@768.4]
+  input  [31:0] io_dbus_rdata, // @[:@768.4]
+  output        io_dbus_rd_en, // @[:@768.4]
+  output        io_dbus_wr_en, // @[:@768.4]
+  output [1:0]  io_dbus_st_type, // @[:@768.4]
+  output [2:0]  io_dbus_ld_type, // @[:@768.4]
+  input         io_dbus_valid, // @[:@768.4]
+  output [31:0] io_ctrl_inst, // @[:@768.4]
+  input  [1:0]  io_ctrl_pc_sel, // @[:@768.4]
+  input         io_ctrl_inst_kill, // @[:@768.4]
+  input         io_ctrl_a_sel, // @[:@768.4]
+  input         io_ctrl_b_sel, // @[:@768.4]
+  input  [2:0]  io_ctrl_imm_sel, // @[:@768.4]
+  input  [4:0]  io_ctrl_alu_op, // @[:@768.4]
+  input  [2:0]  io_ctrl_br_type, // @[:@768.4]
+  input  [1:0]  io_ctrl_st_type, // @[:@768.4]
+  input  [2:0]  io_ctrl_ld_type, // @[:@768.4]
+  input  [1:0]  io_ctrl_wb_mux_sel, // @[:@768.4]
+  input         io_ctrl_wb_en, // @[:@768.4]
+  input  [2:0]  io_ctrl_csr_cmd, // @[:@768.4]
+  input         io_ctrl_illegal, // @[:@768.4]
+  input         io_ctrl_en_rs1, // @[:@768.4]
+  input         io_ctrl_en_rs2 // @[:@768.4]
+);
+  wire  csr_clock; // @[datapath.scala 34:26:@770.4]
+  wire  csr_reset; // @[datapath.scala 34:26:@770.4]
+  wire  csr_io_stall; // @[datapath.scala 34:26:@770.4]
+  wire [2:0] csr_io_cmd; // @[datapath.scala 34:26:@770.4]
+  wire [31:0] csr_io_in; // @[datapath.scala 34:26:@770.4]
+  wire [31:0] csr_io_out; // @[datapath.scala 34:26:@770.4]
+  wire [31:0] csr_io_pc; // @[datapath.scala 34:26:@770.4]
+  wire [31:0] csr_io_addr; // @[datapath.scala 34:26:@770.4]
+  wire [31:0] csr_io_inst; // @[datapath.scala 34:26:@770.4]
+  wire  csr_io_illegal; // @[datapath.scala 34:26:@770.4]
+  wire [1:0] csr_io_st_type; // @[datapath.scala 34:26:@770.4]
+  wire [2:0] csr_io_ld_type; // @[datapath.scala 34:26:@770.4]
+  wire  csr_io_pc_check; // @[datapath.scala 34:26:@770.4]
+  wire  csr_io_expt; // @[datapath.scala 34:26:@770.4]
+  wire [31:0] csr_io_evec; // @[datapath.scala 34:26:@770.4]
+  wire [31:0] csr_io_epc; // @[datapath.scala 34:26:@770.4]
+  wire  csr_io_irq_uart_irq; // @[datapath.scala 34:26:@770.4]
+  wire  csr_io_irq_spi_irq; // @[datapath.scala 34:26:@770.4]
+  wire  csr_io_irq_motor_irq; // @[datapath.scala 34:26:@770.4]
+  wire  csr_io_br_taken; // @[datapath.scala 34:26:@770.4]
+  wire  reg_file_clock; // @[datapath.scala 35:26:@773.4]
+  wire [4:0] reg_file_io_raddr1; // @[datapath.scala 35:26:@773.4]
+  wire [4:0] reg_file_io_raddr2; // @[datapath.scala 35:26:@773.4]
+  wire [31:0] reg_file_io_rdata1; // @[datapath.scala 35:26:@773.4]
+  wire [31:0] reg_file_io_rdata2; // @[datapath.scala 35:26:@773.4]
+  wire  reg_file_io_wen; // @[datapath.scala 35:26:@773.4]
+  wire [4:0] reg_file_io_waddr; // @[datapath.scala 35:26:@773.4]
+  wire [31:0] reg_file_io_wdata; // @[datapath.scala 35:26:@773.4]
+  wire [31:0] alu_io_in_a; // @[datapath.scala 36:26:@776.4]
+  wire [31:0] alu_io_in_b; // @[datapath.scala 36:26:@776.4]
+  wire [3:0] alu_io_alu_op; // @[datapath.scala 36:26:@776.4]
+  wire [31:0] alu_io_out; // @[datapath.scala 36:26:@776.4]
+  wire [31:0] alu_io_sum; // @[datapath.scala 36:26:@776.4]
+  wire [31:0] gen_imm_io_inst; // @[datapath.scala 37:26:@779.4]
+  wire [2:0] gen_imm_io_sel; // @[datapath.scala 37:26:@779.4]
+  wire [31:0] gen_imm_io_out; // @[datapath.scala 37:26:@779.4]
+  wire [31:0] cond_br_io_rs1; // @[datapath.scala 38:26:@782.4]
+  wire [31:0] cond_br_io_rs2; // @[datapath.scala 38:26:@782.4]
+  wire [2:0] cond_br_io_br_type; // @[datapath.scala 38:26:@782.4]
+  wire  cond_br_io_taken; // @[datapath.scala 38:26:@782.4]
+  wire [1:0] lsu_io_lsu_st_type; // @[datapath.scala 137:19:@901.4]
+  wire [31:0] lsu_io_lsu_wdata_in; // @[datapath.scala 137:19:@901.4]
+  wire [31:0] lsu_io_lsu_wdata_out; // @[datapath.scala 137:19:@901.4]
+  wire [31:0] lsu_io_lsu_rdata_in; // @[datapath.scala 137:19:@901.4]
+  wire [31:0] lsu_io_lsu_rdata_out; // @[datapath.scala 137:19:@901.4]
+  wire [2:0] lsu_io_lsu_ld_type; // @[datapath.scala 137:19:@901.4]
+  reg [31:0] fet_exe_inst; // @[datapath.scala 42:30:@785.4]
+  reg [31:0] _RAND_0;
+  reg [31:0] fet_exe_pc; // @[datapath.scala 43:26:@786.4]
+  reg [31:0] _RAND_1;
+  reg [31:0] exe_wb_inst; // @[datapath.scala 46:33:@787.4]
+  reg [31:0] _RAND_2;
+  reg [31:0] exe_wb_pc; // @[datapath.scala 47:29:@788.4]
+  reg [31:0] _RAND_3;
+  reg [31:0] exe_wb_alu; // @[datapath.scala 48:29:@789.4]
+  reg [31:0] _RAND_4;
+  reg [31:0] csr_in; // @[datapath.scala 49:29:@790.4]
+  reg [31:0] _RAND_5;
+  reg [1:0] ctrl_st_type; // @[datapath.scala 52:29:@791.4]
+  reg [31:0] _RAND_6;
+  reg [2:0] ctrl_ld_type; // @[datapath.scala 53:29:@792.4]
+  reg [31:0] _RAND_7;
+  reg [1:0] ctrl_wb_mux_sel; // @[datapath.scala 54:29:@793.4]
+  reg [31:0] _RAND_8;
+  reg  ctrl_wb_en; // @[datapath.scala 55:29:@794.4]
+  reg [31:0] _RAND_9;
+  reg [2:0] ctrl_csr_cmd; // @[datapath.scala 56:29:@795.4]
+  reg [31:0] _RAND_10;
+  reg  ctrl_illegal; // @[datapath.scala 57:29:@796.4]
+  reg [31:0] _RAND_11;
+  reg  ctrl_pc_check; // @[datapath.scala 58:29:@797.4]
+  reg [31:0] _RAND_12;
+  reg  notstarted; // @[datapath.scala 61:27:@799.4]
+  reg [31:0] _RAND_13;
+  wire [32:0] _T_146; // @[datapath.scala 64:57:@803.4]
+  wire [32:0] _T_147; // @[datapath.scala 64:57:@804.4]
+  wire [31:0] _T_148; // @[datapath.scala 64:57:@805.4]
+  reg [31:0] pc; // @[datapath.scala 64:27:@806.4]
+  reg [31:0] _RAND_14;
+  wire  _T_153; // @[datapath.scala 66:33:@809.4]
+  wire  _T_198; // @[datapath.scala 113:39:@866.4]
+  wire  _T_199; // @[datapath.scala 113:59:@867.4]
+  wire  _T_200; // @[datapath.scala 113:43:@868.4]
+  wire [4:0] rs1_addr; // @[datapath.scala 91:37:@843.4]
+  wire  _T_184; // @[datapath.scala 103:47:@850.4]
+  wire  _T_185; // @[datapath.scala 103:35:@851.4]
+  wire [4:0] wrbk_rd_addr; // @[datapath.scala 102:35:@849.4]
+  wire  _T_186; // @[datapath.scala 103:64:@852.4]
+  wire  rs1hazard; // @[datapath.scala 103:51:@853.4]
+  wire  _T_201; // @[datapath.scala 113:90:@869.4]
+  wire [4:0] rs2_addr; // @[datapath.scala 92:37:@844.4]
+  wire  _T_188; // @[datapath.scala 104:47:@854.4]
+  wire  _T_189; // @[datapath.scala 104:35:@855.4]
+  wire  _T_190; // @[datapath.scala 104:64:@856.4]
+  wire  rs2hazard; // @[datapath.scala 104:51:@857.4]
+  wire  _T_202; // @[datapath.scala 113:123:@870.4]
+  wire  _T_203; // @[datapath.scala 113:104:@871.4]
+  wire  hazard_stall; // @[datapath.scala 113:70:@872.4]
+  wire  _T_208; // @[datapath.scala 117:57:@875.4]
+  wire  is_load_store; // @[datapath.scala 117:41:@876.4]
+  wire  _T_211; // @[datapath.scala 119:42:@879.4]
+  wire  _T_213; // @[datapath.scala 119:63:@880.4]
+  wire  _T_214; // @[datapath.scala 119:60:@881.4]
+  wire  dmem_stall; // @[datapath.scala 119:25:@882.4]
+  wire  stall; // @[datapath.scala 120:38:@884.4]
+  wire  _T_154; // @[datapath.scala 66:30:@810.4]
+  wire  _T_155; // @[datapath.scala 67:39:@811.4]
+  wire  _T_156; // @[datapath.scala 68:39:@812.4]
+  wire  _T_157; // @[datapath.scala 68:50:@813.4]
+  wire [31:0] _T_159; // @[datapath.scala 68:82:@814.4]
+  wire [32:0] _GEN_28; // @[datapath.scala 68:89:@815.4]
+  wire [32:0] _T_161; // @[datapath.scala 68:89:@815.4]
+  wire  _T_162; // @[datapath.scala 69:39:@816.4]
+  wire [32:0] _T_164; // @[datapath.scala 69:56:@817.4]
+  wire [31:0] _T_165; // @[datapath.scala 69:56:@818.4]
+  wire [31:0] _T_166; // @[datapath.scala 69:23:@819.4]
+  wire [32:0] _T_167; // @[datapath.scala 68:23:@820.4]
+  wire [32:0] _T_168; // @[datapath.scala 67:23:@821.4]
+  wire [32:0] _T_169; // @[datapath.scala 66:57:@822.4]
+  wire [32:0] _T_170; // @[datapath.scala 66:23:@823.4]
+  wire  _T_171; // @[datapath.scala 72:35:@825.4]
+  wire  _T_172; // @[datapath.scala 72:56:@826.4]
+  wire  _T_173; // @[datapath.scala 72:76:@827.4]
+  wire  _T_176; // @[datapath.scala 72:91:@829.4]
+  wire [31:0] inst; // @[datapath.scala 72:23:@830.4]
+  wire  _T_179; // @[datapath.scala 80:9:@833.4]
+  wire  _T_180; // @[datapath.scala 81:45:@835.6]
+  wire  _T_181; // @[datapath.scala 81:65:@836.6]
+  wire [31:0] _T_182; // @[datapath.scala 81:25:@837.6]
+  wire [31:0] _GEN_1; // @[datapath.scala 80:17:@834.4]
+  wire  _T_191; // @[datapath.scala 107:44:@858.4]
+  wire  _T_192; // @[datapath.scala 107:55:@859.4]
+  wire [31:0] rs1; // @[datapath.scala 107:27:@860.4]
+  wire  _T_194; // @[datapath.scala 108:55:@862.4]
+  wire [31:0] rs2; // @[datapath.scala 108:27:@863.4]
+  wire  _T_221; // @[datapath.scala 123:71:@887.4]
+  wire  _T_232; // @[datapath.scala 157:31:@915.4]
+  wire  _T_233; // @[datapath.scala 157:21:@916.4]
+  wire  _T_243; // @[datapath.scala 164:24:@927.6]
+  wire  _T_244; // @[datapath.scala 164:21:@928.6]
+  wire  _T_245; // @[datapath.scala 170:46:@933.8]
+  wire [31:0] _T_246; // @[datapath.scala 170:29:@934.8]
+  wire [1:0] _GEN_2; // @[datapath.scala 178:28:@946.8]
+  wire [2:0] _GEN_3; // @[datapath.scala 178:28:@946.8]
+  wire  _GEN_4; // @[datapath.scala 178:28:@946.8]
+  wire [2:0] _GEN_5; // @[datapath.scala 178:28:@946.8]
+  wire [31:0] _GEN_6; // @[datapath.scala 164:38:@929.6]
+  wire [31:0] _GEN_7; // @[datapath.scala 164:38:@929.6]
+  wire [31:0] _GEN_8; // @[datapath.scala 164:38:@929.6]
+  wire [31:0] _GEN_9; // @[datapath.scala 164:38:@929.6]
+  wire [1:0] _GEN_10; // @[datapath.scala 164:38:@929.6]
+  wire [2:0] _GEN_11; // @[datapath.scala 164:38:@929.6]
+  wire [1:0] _GEN_12; // @[datapath.scala 164:38:@929.6]
+  wire  _GEN_13; // @[datapath.scala 164:38:@929.6]
+  wire [2:0] _GEN_14; // @[datapath.scala 164:38:@929.6]
+  wire  _GEN_15; // @[datapath.scala 164:38:@929.6]
+  wire  _GEN_16; // @[datapath.scala 164:38:@929.6]
+  wire [31:0] _GEN_24; // @[datapath.scala 157:47:@917.4]
+  wire [32:0] _T_249; // @[datapath.scala 208:62:@966.4]
+  wire [32:0] _T_251; // @[datapath.scala 210:54:@967.4]
+  wire [31:0] _T_252; // @[datapath.scala 210:54:@968.4]
+  wire [32:0] _T_253; // @[datapath.scala 210:61:@969.4]
+  wire [32:0] _T_254; // @[datapath.scala 211:54:@970.4]
+  wire  _T_255; // @[Mux.scala 46:19:@971.4]
+  wire [32:0] _T_256; // @[Mux.scala 46:16:@972.4]
+  wire  _T_257; // @[Mux.scala 46:19:@973.4]
+  wire [32:0] _T_258; // @[Mux.scala 46:16:@974.4]
+  wire  _T_259; // @[Mux.scala 46:19:@975.4]
+  wire [32:0] _T_260; // @[Mux.scala 46:16:@976.4]
+  wire [32:0] reg_file_wdata; // @[datapath.scala 211:62:@977.4]
+  wire [31:0] npc; // @[:@807.4 :@808.4 datapath.scala 66:17:@824.4]
+  CSR csr ( // @[datapath.scala 34:26:@770.4]
+    .clock(csr_clock),
+    .reset(csr_reset),
+    .io_stall(csr_io_stall),
+    .io_cmd(csr_io_cmd),
+    .io_in(csr_io_in),
+    .io_out(csr_io_out),
+    .io_pc(csr_io_pc),
+    .io_addr(csr_io_addr),
+    .io_inst(csr_io_inst),
+    .io_illegal(csr_io_illegal),
+    .io_st_type(csr_io_st_type),
+    .io_ld_type(csr_io_ld_type),
+    .io_pc_check(csr_io_pc_check),
+    .io_expt(csr_io_expt),
+    .io_evec(csr_io_evec),
+    .io_epc(csr_io_epc),
+    .io_irq_uart_irq(csr_io_irq_uart_irq),
+    .io_irq_spi_irq(csr_io_irq_spi_irq),
+    .io_irq_motor_irq(csr_io_irq_motor_irq),
+    .io_br_taken(csr_io_br_taken)
+  );
+  RegFile reg_file ( // @[datapath.scala 35:26:@773.4]
+    .clock(reg_file_clock),
+    .io_raddr1(reg_file_io_raddr1),
+    .io_raddr2(reg_file_io_raddr2),
+    .io_rdata1(reg_file_io_rdata1),
+    .io_rdata2(reg_file_io_rdata2),
+    .io_wen(reg_file_io_wen),
+    .io_waddr(reg_file_io_waddr),
+    .io_wdata(reg_file_io_wdata)
+  );
+  ALU alu ( // @[datapath.scala 36:26:@776.4]
+    .io_in_a(alu_io_in_a),
+    .io_in_b(alu_io_in_b),
+    .io_alu_op(alu_io_alu_op),
+    .io_out(alu_io_out),
+    .io_sum(alu_io_sum)
+  );
+  ImmGen gen_imm ( // @[datapath.scala 37:26:@779.4]
+    .io_inst(gen_imm_io_inst),
+    .io_sel(gen_imm_io_sel),
+    .io_out(gen_imm_io_out)
+  );
+  Branch cond_br ( // @[datapath.scala 38:26:@782.4]
+    .io_rs1(cond_br_io_rs1),
+    .io_rs2(cond_br_io_rs2),
+    .io_br_type(cond_br_io_br_type),
+    .io_taken(cond_br_io_taken)
+  );
+  LS_Unit lsu ( // @[datapath.scala 137:19:@901.4]
+    .io_lsu_st_type(lsu_io_lsu_st_type),
+    .io_lsu_wdata_in(lsu_io_lsu_wdata_in),
+    .io_lsu_wdata_out(lsu_io_lsu_wdata_out),
+    .io_lsu_rdata_in(lsu_io_lsu_rdata_in),
+    .io_lsu_rdata_out(lsu_io_lsu_rdata_out),
+    .io_lsu_ld_type(lsu_io_lsu_ld_type)
+  );
+  assign _T_146 = 32'h7000 - 32'h4; // @[datapath.scala 64:57:@803.4]
+  assign _T_147 = $unsigned(_T_146); // @[datapath.scala 64:57:@804.4]
+  assign _T_148 = _T_147[31:0]; // @[datapath.scala 64:57:@805.4]
+  assign _T_153 = io_ibus_valid == 1'h0; // @[datapath.scala 66:33:@809.4]
+  assign _T_198 = ctrl_ld_type != 3'h0; // @[datapath.scala 113:39:@866.4]
+  assign _T_199 = ctrl_csr_cmd != 3'h0; // @[datapath.scala 113:59:@867.4]
+  assign _T_200 = _T_198 | _T_199; // @[datapath.scala 113:43:@868.4]
+  assign rs1_addr = fet_exe_inst[19:15]; // @[datapath.scala 91:37:@843.4]
+  assign _T_184 = rs1_addr != 5'h0; // @[datapath.scala 103:47:@850.4]
+  assign _T_185 = ctrl_wb_en & _T_184; // @[datapath.scala 103:35:@851.4]
+  assign wrbk_rd_addr = exe_wb_inst[11:7]; // @[datapath.scala 102:35:@849.4]
+  assign _T_186 = rs1_addr == wrbk_rd_addr; // @[datapath.scala 103:64:@852.4]
+  assign rs1hazard = _T_185 & _T_186; // @[datapath.scala 103:51:@853.4]
+  assign _T_201 = io_ctrl_en_rs1 & rs1hazard; // @[datapath.scala 113:90:@869.4]
+  assign rs2_addr = fet_exe_inst[24:20]; // @[datapath.scala 92:37:@844.4]
+  assign _T_188 = rs2_addr != 5'h0; // @[datapath.scala 104:47:@854.4]
+  assign _T_189 = ctrl_wb_en & _T_188; // @[datapath.scala 104:35:@855.4]
+  assign _T_190 = rs2_addr == wrbk_rd_addr; // @[datapath.scala 104:64:@856.4]
+  assign rs2hazard = _T_189 & _T_190; // @[datapath.scala 104:51:@857.4]
+  assign _T_202 = io_ctrl_en_rs2 & rs2hazard; // @[datapath.scala 113:123:@870.4]
+  assign _T_203 = _T_201 | _T_202; // @[datapath.scala 113:104:@871.4]
+  assign hazard_stall = _T_200 & _T_203; // @[datapath.scala 113:70:@872.4]
+  assign _T_208 = ctrl_st_type != 2'h0; // @[datapath.scala 117:57:@875.4]
+  assign is_load_store = _T_198 | _T_208; // @[datapath.scala 117:41:@876.4]
+  assign _T_211 = io_dbus_valid & is_load_store; // @[datapath.scala 119:42:@879.4]
+  assign _T_213 = is_load_store == 1'h0; // @[datapath.scala 119:63:@880.4]
+  assign _T_214 = _T_211 | _T_213; // @[datapath.scala 119:60:@881.4]
+  assign dmem_stall = _T_214 == 1'h0; // @[datapath.scala 119:25:@882.4]
+  assign stall = hazard_stall | dmem_stall; // @[datapath.scala 120:38:@884.4]
+  assign _T_154 = stall | _T_153; // @[datapath.scala 66:30:@810.4]
+  assign _T_155 = io_ctrl_pc_sel == 2'h3; // @[datapath.scala 67:39:@811.4]
+  assign _T_156 = io_ctrl_pc_sel == 2'h1; // @[datapath.scala 68:39:@812.4]
+  assign _T_157 = _T_156 | cond_br_io_taken; // @[datapath.scala 68:50:@813.4]
+  assign _T_159 = alu_io_sum >> 1'h1; // @[datapath.scala 68:82:@814.4]
+  assign _GEN_28 = {{1'd0}, _T_159}; // @[datapath.scala 68:89:@815.4]
+  assign _T_161 = _GEN_28 << 1'h1; // @[datapath.scala 68:89:@815.4]
+  assign _T_162 = io_ctrl_pc_sel == 2'h2; // @[datapath.scala 69:39:@816.4]
+  assign _T_164 = pc + 32'h4; // @[datapath.scala 69:56:@817.4]
+  assign _T_165 = pc + 32'h4; // @[datapath.scala 69:56:@818.4]
+  assign _T_166 = _T_162 ? pc : _T_165; // @[datapath.scala 69:23:@819.4]
+  assign _T_167 = _T_157 ? _T_161 : {{1'd0}, _T_166}; // @[datapath.scala 68:23:@820.4]
+  assign _T_168 = _T_155 ? {{1'd0}, csr_io_epc} : _T_167; // @[datapath.scala 67:23:@821.4]
+  assign _T_169 = csr_io_expt ? {{1'd0}, csr_io_evec} : _T_168; // @[datapath.scala 66:57:@822.4]
+  assign _T_170 = _T_154 ? {{1'd0}, pc} : _T_169; // @[datapath.scala 66:23:@823.4]
+  assign _T_171 = notstarted | io_ctrl_inst_kill; // @[datapath.scala 72:35:@825.4]
+  assign _T_172 = _T_171 | cond_br_io_taken; // @[datapath.scala 72:56:@826.4]
+  assign _T_173 = _T_172 | csr_io_expt; // @[datapath.scala 72:76:@827.4]
+  assign _T_176 = _T_173 | _T_153; // @[datapath.scala 72:91:@829.4]
+  assign inst = _T_176 ? 32'h13 : io_ibus_inst; // @[datapath.scala 72:23:@830.4]
+  assign _T_179 = stall == 1'h0; // @[datapath.scala 80:9:@833.4]
+  assign _T_180 = io_ctrl_inst_kill | cond_br_io_taken; // @[datapath.scala 81:45:@835.6]
+  assign _T_181 = _T_180 | csr_io_expt; // @[datapath.scala 81:65:@836.6]
+  assign _T_182 = _T_181 ? fet_exe_pc : pc; // @[datapath.scala 81:25:@837.6]
+  assign _GEN_1 = _T_179 ? inst : fet_exe_inst; // @[datapath.scala 80:17:@834.4]
+  assign _T_191 = ctrl_wb_mux_sel == 2'h0; // @[datapath.scala 107:44:@858.4]
+  assign _T_192 = _T_191 & rs1hazard; // @[datapath.scala 107:55:@859.4]
+  assign rs1 = _T_192 ? exe_wb_alu : reg_file_io_rdata1; // @[datapath.scala 107:27:@860.4]
+  assign _T_194 = _T_191 & rs2hazard; // @[datapath.scala 108:55:@862.4]
+  assign rs2 = _T_194 ? exe_wb_alu : reg_file_io_rdata2; // @[datapath.scala 108:27:@863.4]
+  assign _T_221 = io_ctrl_st_type != 2'h0; // @[datapath.scala 123:71:@887.4]
+  assign _T_232 = _T_179 & csr_io_expt; // @[datapath.scala 157:31:@915.4]
+  assign _T_233 = reset | _T_232; // @[datapath.scala 157:21:@916.4]
+  assign _T_243 = csr_io_expt == 1'h0; // @[datapath.scala 164:24:@927.6]
+  assign _T_244 = _T_179 & _T_243; // @[datapath.scala 164:21:@928.6]
+  assign _T_245 = io_ctrl_imm_sel == 3'h6; // @[datapath.scala 170:46:@933.8]
+  assign _T_246 = _T_245 ? gen_imm_io_out : rs1; // @[datapath.scala 170:29:@934.8]
+  assign _GEN_2 = hazard_stall ? 2'h0 : ctrl_st_type; // @[datapath.scala 178:28:@946.8]
+  assign _GEN_3 = hazard_stall ? 3'h0 : ctrl_ld_type; // @[datapath.scala 178:28:@946.8]
+  assign _GEN_4 = hazard_stall ? 1'h0 : ctrl_wb_en; // @[datapath.scala 178:28:@946.8]
+  assign _GEN_5 = hazard_stall ? 3'h0 : ctrl_csr_cmd; // @[datapath.scala 178:28:@946.8]
+  assign _GEN_6 = _T_244 ? fet_exe_pc : exe_wb_pc; // @[datapath.scala 164:38:@929.6]
+  assign _GEN_7 = _T_244 ? fet_exe_inst : exe_wb_inst; // @[datapath.scala 164:38:@929.6]
+  assign _GEN_8 = _T_244 ? alu_io_out : exe_wb_alu; // @[datapath.scala 164:38:@929.6]
+  assign _GEN_9 = _T_244 ? _T_246 : csr_in; // @[datapath.scala 164:38:@929.6]
+  assign _GEN_10 = _T_244 ? io_ctrl_st_type : _GEN_2; // @[datapath.scala 164:38:@929.6]
+  assign _GEN_11 = _T_244 ? io_ctrl_ld_type : _GEN_3; // @[datapath.scala 164:38:@929.6]
+  assign _GEN_12 = _T_244 ? io_ctrl_wb_mux_sel : ctrl_wb_mux_sel; // @[datapath.scala 164:38:@929.6]
+  assign _GEN_13 = _T_244 ? io_ctrl_wb_en : _GEN_4; // @[datapath.scala 164:38:@929.6]
+  assign _GEN_14 = _T_244 ? io_ctrl_csr_cmd : _GEN_5; // @[datapath.scala 164:38:@929.6]
+  assign _GEN_15 = _T_244 ? io_ctrl_illegal : ctrl_illegal; // @[datapath.scala 164:38:@929.6]
+  assign _GEN_16 = _T_244 ? _T_156 : ctrl_pc_check; // @[datapath.scala 164:38:@929.6]
+  assign _GEN_24 = _T_233 ? exe_wb_inst : _GEN_7; // @[datapath.scala 157:47:@917.4]
+  assign _T_249 = {1'b0,$signed(exe_wb_alu)}; // @[datapath.scala 208:62:@966.4]
+  assign _T_251 = exe_wb_pc + 32'h4; // @[datapath.scala 210:54:@967.4]
+  assign _T_252 = exe_wb_pc + 32'h4; // @[datapath.scala 210:54:@968.4]
+  assign _T_253 = {1'b0,$signed(_T_252)}; // @[datapath.scala 210:61:@969.4]
+  assign _T_254 = {1'b0,$signed(csr_io_out)}; // @[datapath.scala 211:54:@970.4]
+  assign _T_255 = 2'h3 == ctrl_wb_mux_sel; // @[Mux.scala 46:19:@971.4]
+  assign _T_256 = _T_255 ? $signed(_T_254) : $signed(_T_249); // @[Mux.scala 46:16:@972.4]
+  assign _T_257 = 2'h2 == ctrl_wb_mux_sel; // @[Mux.scala 46:19:@973.4]
+  assign _T_258 = _T_257 ? $signed(_T_253) : $signed(_T_256); // @[Mux.scala 46:16:@974.4]
+  assign _T_259 = 2'h1 == ctrl_wb_mux_sel; // @[Mux.scala 46:19:@975.4]
+  assign _T_260 = _T_259 ? $signed({{1{lsu_io_lsu_rdata_out[31]}},lsu_io_lsu_rdata_out}) : $signed(_T_258); // @[Mux.scala 46:16:@976.4]
+  assign reg_file_wdata = $unsigned(_T_260); // @[datapath.scala 211:62:@977.4]
+  assign npc = _T_170[31:0]; // @[:@807.4 :@808.4 datapath.scala 66:17:@824.4]
+  assign io_ibus_addr = _T_170[31:0]; // @[datapath.scala 75:18:@832.4]
+  assign io_dbus_addr = alu_io_sum; // @[datapath.scala 152:23:@912.4]
+  assign io_dbus_wdata = lsu_io_lsu_wdata_out; // @[datapath.scala 142:23:@906.4]
+  assign io_dbus_rd_en = io_ctrl_ld_type != 3'h0; // @[datapath.scala 145:23:@908.4]
+  assign io_dbus_wr_en = hazard_stall ? 1'h0 : _T_221; // @[datapath.scala 123:22:@889.4]
+  assign io_dbus_st_type = io_ctrl_st_type; // @[datapath.scala 124:22:@890.4]
+  assign io_dbus_ld_type = io_ctrl_ld_type; // @[datapath.scala 146:23:@909.4]
+  assign io_ctrl_inst = fet_exe_inst; // @[datapath.scala 87:22:@841.4]
+  assign csr_clock = clock; // @[:@771.4]
+  assign csr_reset = reset; // @[:@772.4]
+  assign csr_io_stall = hazard_stall | dmem_stall; // @[datapath.scala 190:20:@952.4]
+  assign csr_io_cmd = ctrl_csr_cmd; // @[datapath.scala 192:20:@954.4]
+  assign csr_io_in = csr_in; // @[datapath.scala 191:20:@953.4]
+  assign csr_io_pc = exe_wb_pc; // @[datapath.scala 194:20:@956.4]
+  assign csr_io_addr = exe_wb_alu; // @[datapath.scala 195:20:@957.4]
+  assign csr_io_inst = exe_wb_inst; // @[datapath.scala 193:20:@955.4]
+  assign csr_io_illegal = ctrl_illegal; // @[datapath.scala 196:20:@958.4]
+  assign csr_io_st_type = ctrl_st_type; // @[datapath.scala 199:20:@961.4]
+  assign csr_io_ld_type = ctrl_ld_type; // @[datapath.scala 198:20:@960.4]
+  assign csr_io_pc_check = ctrl_pc_check; // @[datapath.scala 197:20:@959.4]
+  assign csr_io_irq_uart_irq = io_irq_uart_irq; // @[datapath.scala 203:20:@965.4]
+  assign csr_io_irq_spi_irq = io_irq_spi_irq; // @[datapath.scala 203:20:@964.4]
+  assign csr_io_irq_motor_irq = io_irq_motor_irq; // @[datapath.scala 203:20:@963.4]
+  assign csr_io_br_taken = cond_br_io_taken; // @[datapath.scala 200:20:@962.4]
+  assign reg_file_clock = clock; // @[:@774.4]
+  assign reg_file_io_raddr1 = fet_exe_inst[19:15]; // @[datapath.scala 93:22:@845.4]
+  assign reg_file_io_raddr2 = fet_exe_inst[24:20]; // @[datapath.scala 94:22:@846.4]
+  assign reg_file_io_wen = ctrl_wb_en & _T_243; // @[datapath.scala 213:22:@980.4]
+  assign reg_file_io_waddr = exe_wb_inst[11:7]; // @[datapath.scala 214:22:@981.4]
+  assign reg_file_io_wdata = reg_file_wdata[31:0]; // @[datapath.scala 215:22:@982.4]
+  assign alu_io_in_a = io_ctrl_a_sel ? rs1 : fet_exe_pc; // @[datapath.scala 127:22:@893.4]
+  assign alu_io_in_b = io_ctrl_b_sel ? rs2 : gen_imm_io_out; // @[datapath.scala 128:22:@896.4]
+  assign alu_io_alu_op = io_ctrl_alu_op[3:0]; // @[datapath.scala 129:22:@897.4]
+  assign gen_imm_io_inst = fet_exe_inst; // @[datapath.scala 97:22:@847.4]
+  assign gen_imm_io_sel = io_ctrl_imm_sel; // @[datapath.scala 98:22:@848.4]
+  assign cond_br_io_rs1 = _T_192 ? exe_wb_alu : reg_file_io_rdata1; // @[datapath.scala 132:22:@898.4]
+  assign cond_br_io_rs2 = _T_194 ? exe_wb_alu : reg_file_io_rdata2; // @[datapath.scala 133:22:@899.4]
+  assign cond_br_io_br_type = io_ctrl_br_type; // @[datapath.scala 134:22:@900.4]
+  assign lsu_io_lsu_st_type = io_ctrl_st_type; // @[datapath.scala 140:23:@904.4]
+  assign lsu_io_lsu_wdata_in = _T_194 ? exe_wb_alu : reg_file_io_rdata2; // @[datapath.scala 141:23:@905.4]
+  assign lsu_io_lsu_rdata_in = io_dbus_rdata; // @[datapath.scala 148:23:@911.4]
+  assign lsu_io_lsu_ld_type = ctrl_ld_type; // @[datapath.scala 147:23:@910.4]
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE
+  integer initvar;
+  initial begin
+    `ifdef INIT_RANDOM
+      `INIT_RANDOM
+    `endif
+    `ifndef VERILATOR
+      #0.002 begin end
+    `endif
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_0 = {1{`RANDOM}};
+  fet_exe_inst = _RAND_0[31:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_1 = {1{`RANDOM}};
+  fet_exe_pc = _RAND_1[31:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_2 = {1{`RANDOM}};
+  exe_wb_inst = _RAND_2[31:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_3 = {1{`RANDOM}};
+  exe_wb_pc = _RAND_3[31:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_4 = {1{`RANDOM}};
+  exe_wb_alu = _RAND_4[31:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_5 = {1{`RANDOM}};
+  csr_in = _RAND_5[31:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_6 = {1{`RANDOM}};
+  ctrl_st_type = _RAND_6[1:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_7 = {1{`RANDOM}};
+  ctrl_ld_type = _RAND_7[2:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_8 = {1{`RANDOM}};
+  ctrl_wb_mux_sel = _RAND_8[1:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_9 = {1{`RANDOM}};
+  ctrl_wb_en = _RAND_9[0:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_10 = {1{`RANDOM}};
+  ctrl_csr_cmd = _RAND_10[2:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_11 = {1{`RANDOM}};
+  ctrl_illegal = _RAND_11[0:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_12 = {1{`RANDOM}};
+  ctrl_pc_check = _RAND_12[0:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_13 = {1{`RANDOM}};
+  notstarted = _RAND_13[0:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_14 = {1{`RANDOM}};
+  pc = _RAND_14[31:0];
+  `endif // RANDOMIZE_REG_INIT
+  end
+`endif // RANDOMIZE
+  always @(posedge clock) begin
+    if (reset) begin
+      fet_exe_inst <= 32'h13;
+    end else begin
+      if (_T_179) begin
+        if (_T_176) begin
+          fet_exe_inst <= 32'h13;
+        end else begin
+          fet_exe_inst <= io_ibus_inst;
+        end
+      end
+    end
+    if (_T_179) begin
+      if (!(_T_181)) begin
+        fet_exe_pc <= pc;
+      end
+    end
+    if (reset) begin
+      exe_wb_inst <= 32'h13;
+    end else begin
+      if (!(_T_233)) begin
+        if (_T_244) begin
+          exe_wb_inst <= fet_exe_inst;
+        end
+      end
+    end
+    if (!(_T_233)) begin
+      if (_T_244) begin
+        exe_wb_pc <= fet_exe_pc;
+      end
+    end
+    if (!(_T_233)) begin
+      if (_T_244) begin
+        exe_wb_alu <= alu_io_out;
+      end
+    end
+    if (!(_T_233)) begin
+      if (_T_244) begin
+        if (_T_245) begin
+          csr_in <= gen_imm_io_out;
+        end else begin
+          if (_T_192) begin
+            csr_in <= exe_wb_alu;
+          end else begin
+            csr_in <= reg_file_io_rdata1;
+          end
+        end
+      end
+    end
+    if (_T_233) begin
+      ctrl_st_type <= 2'h0;
+    end else begin
+      if (_T_244) begin
+        ctrl_st_type <= io_ctrl_st_type;
+      end else begin
+        if (hazard_stall) begin
+          ctrl_st_type <= 2'h0;
+        end
+      end
+    end
+    if (_T_233) begin
+      ctrl_ld_type <= 3'h0;
+    end else begin
+      if (_T_244) begin
+        ctrl_ld_type <= io_ctrl_ld_type;
+      end else begin
+        if (hazard_stall) begin
+          ctrl_ld_type <= 3'h0;
+        end
+      end
+    end
+    if (!(_T_233)) begin
+      if (_T_244) begin
+        ctrl_wb_mux_sel <= io_ctrl_wb_mux_sel;
+      end
+    end
+    if (_T_233) begin
+      ctrl_wb_en <= 1'h0;
+    end else begin
+      if (_T_244) begin
+        ctrl_wb_en <= io_ctrl_wb_en;
+      end else begin
+        if (hazard_stall) begin
+          ctrl_wb_en <= 1'h0;
+        end
+      end
+    end
+    if (_T_233) begin
+      ctrl_csr_cmd <= 3'h0;
+    end else begin
+      if (_T_244) begin
+        ctrl_csr_cmd <= io_ctrl_csr_cmd;
+      end else begin
+        if (hazard_stall) begin
+          ctrl_csr_cmd <= 3'h0;
+        end
+      end
+    end
+    if (_T_233) begin
+      ctrl_illegal <= 1'h0;
+    end else begin
+      if (_T_244) begin
+        ctrl_illegal <= io_ctrl_illegal;
+      end
+    end
+    if (_T_233) begin
+      ctrl_pc_check <= 1'h0;
+    end else begin
+      if (_T_244) begin
+        ctrl_pc_check <= _T_156;
+      end
+    end
+    notstarted <= reset;
+    if (reset) begin
+      pc <= _T_148;
+    end else begin
+      pc <= npc;
+    end
+  end
+endmodule
+module Control( // @[:@984.2]
+  input  [31:0] io_inst, // @[:@987.4]
+  output [1:0]  io_pc_sel, // @[:@987.4]
+  output        io_inst_kill, // @[:@987.4]
+  output        io_a_sel, // @[:@987.4]
+  output        io_b_sel, // @[:@987.4]
+  output [2:0]  io_imm_sel, // @[:@987.4]
+  output [4:0]  io_alu_op, // @[:@987.4]
+  output [2:0]  io_br_type, // @[:@987.4]
+  output [1:0]  io_st_type, // @[:@987.4]
+  output [2:0]  io_ld_type, // @[:@987.4]
+  output [1:0]  io_wb_mux_sel, // @[:@987.4]
+  output        io_wb_en, // @[:@987.4]
+  output [2:0]  io_csr_cmd, // @[:@987.4]
+  output        io_illegal, // @[:@987.4]
+  output        io_en_rs1, // @[:@987.4]
+  output        io_en_rs2 // @[:@987.4]
+);
+  wire [31:0] _T_39; // @[Lookup.scala 9:38:@989.4]
+  wire  _T_40; // @[Lookup.scala 9:38:@990.4]
+  wire  _T_44; // @[Lookup.scala 9:38:@992.4]
+  wire  _T_48; // @[Lookup.scala 9:38:@994.4]
+  wire [31:0] _T_51; // @[Lookup.scala 9:38:@995.4]
+  wire  _T_52; // @[Lookup.scala 9:38:@996.4]
+  wire  _T_56; // @[Lookup.scala 9:38:@998.4]
+  wire  _T_60; // @[Lookup.scala 9:38:@1000.4]
+  wire  _T_64; // @[Lookup.scala 9:38:@1002.4]
+  wire  _T_68; // @[Lookup.scala 9:38:@1004.4]
+  wire  _T_72; // @[Lookup.scala 9:38:@1006.4]
+  wire  _T_76; // @[Lookup.scala 9:38:@1008.4]
+  wire  _T_80; // @[Lookup.scala 9:38:@1010.4]
+  wire  _T_84; // @[Lookup.scala 9:38:@1012.4]
+  wire  _T_88; // @[Lookup.scala 9:38:@1014.4]
+  wire  _T_92; // @[Lookup.scala 9:38:@1016.4]
+  wire  _T_96; // @[Lookup.scala 9:38:@1018.4]
+  wire  _T_100; // @[Lookup.scala 9:38:@1020.4]
+  wire  _T_104; // @[Lookup.scala 9:38:@1022.4]
+  wire  _T_108; // @[Lookup.scala 9:38:@1024.4]
+  wire  _T_112; // @[Lookup.scala 9:38:@1026.4]
+  wire  _T_116; // @[Lookup.scala 9:38:@1028.4]
+  wire  _T_120; // @[Lookup.scala 9:38:@1030.4]
+  wire  _T_124; // @[Lookup.scala 9:38:@1032.4]
+  wire  _T_128; // @[Lookup.scala 9:38:@1034.4]
+  wire  _T_132; // @[Lookup.scala 9:38:@1036.4]
+  wire [31:0] _T_135; // @[Lookup.scala 9:38:@1037.4]
+  wire  _T_136; // @[Lookup.scala 9:38:@1038.4]
+  wire  _T_140; // @[Lookup.scala 9:38:@1040.4]
+  wire  _T_144; // @[Lookup.scala 9:38:@1042.4]
+  wire  _T_148; // @[Lookup.scala 9:38:@1044.4]
+  wire  _T_152; // @[Lookup.scala 9:38:@1046.4]
+  wire  _T_156; // @[Lookup.scala 9:38:@1048.4]
+  wire  _T_160; // @[Lookup.scala 9:38:@1050.4]
+  wire  _T_164; // @[Lookup.scala 9:38:@1052.4]
+  wire  _T_168; // @[Lookup.scala 9:38:@1054.4]
+  wire  _T_172; // @[Lookup.scala 9:38:@1056.4]
+  wire  _T_176; // @[Lookup.scala 9:38:@1058.4]
+  wire  _T_180; // @[Lookup.scala 9:38:@1060.4]
+  wire  _T_184; // @[Lookup.scala 9:38:@1062.4]
+  wire [31:0] _T_187; // @[Lookup.scala 9:38:@1063.4]
+  wire  _T_188; // @[Lookup.scala 9:38:@1064.4]
+  wire  _T_192; // @[Lookup.scala 9:38:@1066.4]
+  wire  _T_196; // @[Lookup.scala 9:38:@1068.4]
+  wire  _T_200; // @[Lookup.scala 9:38:@1070.4]
+  wire  _T_204; // @[Lookup.scala 9:38:@1072.4]
+  wire  _T_208; // @[Lookup.scala 9:38:@1074.4]
+  wire  _T_212; // @[Lookup.scala 9:38:@1076.4]
+  wire  _T_216; // @[Lookup.scala 9:38:@1078.4]
+  wire  _T_220; // @[Lookup.scala 9:38:@1080.4]
+  wire  _T_224; // @[Lookup.scala 9:38:@1082.4]
+  wire  _T_228; // @[Lookup.scala 9:38:@1084.4]
+  wire  _T_232; // @[Lookup.scala 9:38:@1086.4]
+  wire [1:0] _T_234; // @[Lookup.scala 11:37:@1088.4]
+  wire [1:0] _T_235; // @[Lookup.scala 11:37:@1089.4]
+  wire [1:0] _T_236; // @[Lookup.scala 11:37:@1090.4]
+  wire [1:0] _T_237; // @[Lookup.scala 11:37:@1091.4]
+  wire [1:0] _T_238; // @[Lookup.scala 11:37:@1092.4]
+  wire [1:0] _T_239; // @[Lookup.scala 11:37:@1093.4]
+  wire [1:0] _T_240; // @[Lookup.scala 11:37:@1094.4]
+  wire [1:0] _T_241; // @[Lookup.scala 11:37:@1095.4]
+  wire [1:0] _T_242; // @[Lookup.scala 11:37:@1096.4]
+  wire [1:0] _T_243; // @[Lookup.scala 11:37:@1097.4]
+  wire [1:0] _T_244; // @[Lookup.scala 11:37:@1098.4]
+  wire [1:0] _T_245; // @[Lookup.scala 11:37:@1099.4]
+  wire [1:0] _T_246; // @[Lookup.scala 11:37:@1100.4]
+  wire [1:0] _T_247; // @[Lookup.scala 11:37:@1101.4]
+  wire [1:0] _T_248; // @[Lookup.scala 11:37:@1102.4]
+  wire [1:0] _T_249; // @[Lookup.scala 11:37:@1103.4]
+  wire [1:0] _T_250; // @[Lookup.scala 11:37:@1104.4]
+  wire [1:0] _T_251; // @[Lookup.scala 11:37:@1105.4]
+  wire [1:0] _T_252; // @[Lookup.scala 11:37:@1106.4]
+  wire [1:0] _T_253; // @[Lookup.scala 11:37:@1107.4]
+  wire [1:0] _T_254; // @[Lookup.scala 11:37:@1108.4]
+  wire [1:0] _T_255; // @[Lookup.scala 11:37:@1109.4]
+  wire [1:0] _T_256; // @[Lookup.scala 11:37:@1110.4]
+  wire [1:0] _T_257; // @[Lookup.scala 11:37:@1111.4]
+  wire [1:0] _T_258; // @[Lookup.scala 11:37:@1112.4]
+  wire [1:0] _T_259; // @[Lookup.scala 11:37:@1113.4]
+  wire [1:0] _T_260; // @[Lookup.scala 11:37:@1114.4]
+  wire [1:0] _T_261; // @[Lookup.scala 11:37:@1115.4]
+  wire [1:0] _T_262; // @[Lookup.scala 11:37:@1116.4]
+  wire [1:0] _T_263; // @[Lookup.scala 11:37:@1117.4]
+  wire [1:0] _T_264; // @[Lookup.scala 11:37:@1118.4]
+  wire [1:0] _T_265; // @[Lookup.scala 11:37:@1119.4]
+  wire [1:0] _T_266; // @[Lookup.scala 11:37:@1120.4]
+  wire [1:0] _T_267; // @[Lookup.scala 11:37:@1121.4]
+  wire [1:0] _T_268; // @[Lookup.scala 11:37:@1122.4]
+  wire [1:0] _T_269; // @[Lookup.scala 11:37:@1123.4]
+  wire [1:0] _T_270; // @[Lookup.scala 11:37:@1124.4]
+  wire [1:0] _T_271; // @[Lookup.scala 11:37:@1125.4]
+  wire [1:0] _T_272; // @[Lookup.scala 11:37:@1126.4]
+  wire [1:0] _T_273; // @[Lookup.scala 11:37:@1127.4]
+  wire [1:0] _T_274; // @[Lookup.scala 11:37:@1128.4]
+  wire [1:0] _T_275; // @[Lookup.scala 11:37:@1129.4]
+  wire [1:0] _T_276; // @[Lookup.scala 11:37:@1130.4]
+  wire [1:0] _T_277; // @[Lookup.scala 11:37:@1131.4]
+  wire [1:0] _T_278; // @[Lookup.scala 11:37:@1132.4]
+  wire [1:0] _T_279; // @[Lookup.scala 11:37:@1133.4]
+  wire [1:0] _T_280; // @[Lookup.scala 11:37:@1134.4]
+  wire  _T_289; // @[Lookup.scala 11:37:@1144.4]
+  wire  _T_290; // @[Lookup.scala 11:37:@1145.4]
+  wire  _T_291; // @[Lookup.scala 11:37:@1146.4]
+  wire  _T_292; // @[Lookup.scala 11:37:@1147.4]
+  wire  _T_293; // @[Lookup.scala 11:37:@1148.4]
+  wire  _T_294; // @[Lookup.scala 11:37:@1149.4]
+  wire  _T_295; // @[Lookup.scala 11:37:@1150.4]
+  wire  _T_296; // @[Lookup.scala 11:37:@1151.4]
+  wire  _T_297; // @[Lookup.scala 11:37:@1152.4]
+  wire  _T_298; // @[Lookup.scala 11:37:@1153.4]
+  wire  _T_299; // @[Lookup.scala 11:37:@1154.4]
+  wire  _T_300; // @[Lookup.scala 11:37:@1155.4]
+  wire  _T_301; // @[Lookup.scala 11:37:@1156.4]
+  wire  _T_302; // @[Lookup.scala 11:37:@1157.4]
+  wire  _T_303; // @[Lookup.scala 11:37:@1158.4]
+  wire  _T_304; // @[Lookup.scala 11:37:@1159.4]
+  wire  _T_305; // @[Lookup.scala 11:37:@1160.4]
+  wire  _T_306; // @[Lookup.scala 11:37:@1161.4]
+  wire  _T_307; // @[Lookup.scala 11:37:@1162.4]
+  wire  _T_308; // @[Lookup.scala 11:37:@1163.4]
+  wire  _T_309; // @[Lookup.scala 11:37:@1164.4]
+  wire  _T_310; // @[Lookup.scala 11:37:@1165.4]
+  wire  _T_311; // @[Lookup.scala 11:37:@1166.4]
+  wire  _T_312; // @[Lookup.scala 11:37:@1167.4]
+  wire  _T_313; // @[Lookup.scala 11:37:@1168.4]
+  wire  _T_314; // @[Lookup.scala 11:37:@1169.4]
+  wire  _T_315; // @[Lookup.scala 11:37:@1170.4]
+  wire  _T_316; // @[Lookup.scala 11:37:@1171.4]
+  wire  _T_317; // @[Lookup.scala 11:37:@1172.4]
+  wire  _T_318; // @[Lookup.scala 11:37:@1173.4]
+  wire  _T_319; // @[Lookup.scala 11:37:@1174.4]
+  wire  _T_320; // @[Lookup.scala 11:37:@1175.4]
+  wire  _T_321; // @[Lookup.scala 11:37:@1176.4]
+  wire  _T_322; // @[Lookup.scala 11:37:@1177.4]
+  wire  _T_323; // @[Lookup.scala 11:37:@1178.4]
+  wire  _T_324; // @[Lookup.scala 11:37:@1179.4]
+  wire  _T_325; // @[Lookup.scala 11:37:@1180.4]
+  wire  _T_326; // @[Lookup.scala 11:37:@1181.4]
+  wire  _T_327; // @[Lookup.scala 11:37:@1182.4]
+  wire  _T_328; // @[Lookup.scala 11:37:@1183.4]
+  wire  _T_342; // @[Lookup.scala 11:37:@1198.4]
+  wire  _T_343; // @[Lookup.scala 11:37:@1199.4]
+  wire  _T_344; // @[Lookup.scala 11:37:@1200.4]
+  wire  _T_345; // @[Lookup.scala 11:37:@1201.4]
+  wire  _T_346; // @[Lookup.scala 11:37:@1202.4]
+  wire  _T_347; // @[Lookup.scala 11:37:@1203.4]
+  wire  _T_348; // @[Lookup.scala 11:37:@1204.4]
+  wire  _T_349; // @[Lookup.scala 11:37:@1205.4]
+  wire  _T_350; // @[Lookup.scala 11:37:@1206.4]
+  wire  _T_351; // @[Lookup.scala 11:37:@1207.4]
+  wire  _T_352; // @[Lookup.scala 11:37:@1208.4]
+  wire  _T_353; // @[Lookup.scala 11:37:@1209.4]
+  wire  _T_354; // @[Lookup.scala 11:37:@1210.4]
+  wire  _T_355; // @[Lookup.scala 11:37:@1211.4]
+  wire  _T_356; // @[Lookup.scala 11:37:@1212.4]
+  wire  _T_357; // @[Lookup.scala 11:37:@1213.4]
+  wire  _T_358; // @[Lookup.scala 11:37:@1214.4]
+  wire  _T_359; // @[Lookup.scala 11:37:@1215.4]
+  wire  _T_360; // @[Lookup.scala 11:37:@1216.4]
+  wire  _T_361; // @[Lookup.scala 11:37:@1217.4]
+  wire  _T_362; // @[Lookup.scala 11:37:@1218.4]
+  wire  _T_363; // @[Lookup.scala 11:37:@1219.4]
+  wire  _T_364; // @[Lookup.scala 11:37:@1220.4]
+  wire  _T_365; // @[Lookup.scala 11:37:@1221.4]
+  wire  _T_366; // @[Lookup.scala 11:37:@1222.4]
+  wire  _T_367; // @[Lookup.scala 11:37:@1223.4]
+  wire  _T_368; // @[Lookup.scala 11:37:@1224.4]
+  wire  _T_369; // @[Lookup.scala 11:37:@1225.4]
+  wire  _T_370; // @[Lookup.scala 11:37:@1226.4]
+  wire  _T_371; // @[Lookup.scala 11:37:@1227.4]
+  wire  _T_372; // @[Lookup.scala 11:37:@1228.4]
+  wire  _T_373; // @[Lookup.scala 11:37:@1229.4]
+  wire  _T_374; // @[Lookup.scala 11:37:@1230.4]
+  wire  _T_375; // @[Lookup.scala 11:37:@1231.4]
+  wire  _T_376; // @[Lookup.scala 11:37:@1232.4]
+  wire [2:0] _T_381; // @[Lookup.scala 11:37:@1238.4]
+  wire [2:0] _T_382; // @[Lookup.scala 11:37:@1239.4]
+  wire [2:0] _T_383; // @[Lookup.scala 11:37:@1240.4]
+  wire [2:0] _T_384; // @[Lookup.scala 11:37:@1241.4]
+  wire [2:0] _T_385; // @[Lookup.scala 11:37:@1242.4]
+  wire [2:0] _T_386; // @[Lookup.scala 11:37:@1243.4]
+  wire [2:0] _T_387; // @[Lookup.scala 11:37:@1244.4]
+  wire [2:0] _T_388; // @[Lookup.scala 11:37:@1245.4]
+  wire [2:0] _T_389; // @[Lookup.scala 11:37:@1246.4]
+  wire [2:0] _T_390; // @[Lookup.scala 11:37:@1247.4]
+  wire [2:0] _T_391; // @[Lookup.scala 11:37:@1248.4]
+  wire [2:0] _T_392; // @[Lookup.scala 11:37:@1249.4]
+  wire [2:0] _T_393; // @[Lookup.scala 11:37:@1250.4]
+  wire [2:0] _T_394; // @[Lookup.scala 11:37:@1251.4]
+  wire [2:0] _T_395; // @[Lookup.scala 11:37:@1252.4]
+  wire [2:0] _T_396; // @[Lookup.scala 11:37:@1253.4]
+  wire [2:0] _T_397; // @[Lookup.scala 11:37:@1254.4]
+  wire [2:0] _T_398; // @[Lookup.scala 11:37:@1255.4]
+  wire [2:0] _T_399; // @[Lookup.scala 11:37:@1256.4]
+  wire [2:0] _T_400; // @[Lookup.scala 11:37:@1257.4]
+  wire [2:0] _T_401; // @[Lookup.scala 11:37:@1258.4]
+  wire [2:0] _T_402; // @[Lookup.scala 11:37:@1259.4]
+  wire [2:0] _T_403; // @[Lookup.scala 11:37:@1260.4]
+  wire [2:0] _T_404; // @[Lookup.scala 11:37:@1261.4]
+  wire [2:0] _T_405; // @[Lookup.scala 11:37:@1262.4]
+  wire [2:0] _T_406; // @[Lookup.scala 11:37:@1263.4]
+  wire [2:0] _T_407; // @[Lookup.scala 11:37:@1264.4]
+  wire [2:0] _T_408; // @[Lookup.scala 11:37:@1265.4]
+  wire [2:0] _T_409; // @[Lookup.scala 11:37:@1266.4]
+  wire [2:0] _T_410; // @[Lookup.scala 11:37:@1267.4]
+  wire [2:0] _T_411; // @[Lookup.scala 11:37:@1268.4]
+  wire [2:0] _T_412; // @[Lookup.scala 11:37:@1269.4]
+  wire [2:0] _T_413; // @[Lookup.scala 11:37:@1270.4]
+  wire [2:0] _T_414; // @[Lookup.scala 11:37:@1271.4]
+  wire [2:0] _T_415; // @[Lookup.scala 11:37:@1272.4]
+  wire [2:0] _T_416; // @[Lookup.scala 11:37:@1273.4]
+  wire [2:0] _T_417; // @[Lookup.scala 11:37:@1274.4]
+  wire [2:0] _T_418; // @[Lookup.scala 11:37:@1275.4]
+  wire [2:0] _T_419; // @[Lookup.scala 11:37:@1276.4]
+  wire [2:0] _T_420; // @[Lookup.scala 11:37:@1277.4]
+  wire [2:0] _T_421; // @[Lookup.scala 11:37:@1278.4]
+  wire [2:0] _T_422; // @[Lookup.scala 11:37:@1279.4]
+  wire [2:0] _T_423; // @[Lookup.scala 11:37:@1280.4]
+  wire [2:0] _T_424; // @[Lookup.scala 11:37:@1281.4]
+  wire [3:0] _T_432; // @[Lookup.scala 11:37:@1290.4]
+  wire [3:0] _T_433; // @[Lookup.scala 11:37:@1291.4]
+  wire [3:0] _T_434; // @[Lookup.scala 11:37:@1292.4]
+  wire [3:0] _T_435; // @[Lookup.scala 11:37:@1293.4]
+  wire [3:0] _T_436; // @[Lookup.scala 11:37:@1294.4]
+  wire [3:0] _T_437; // @[Lookup.scala 11:37:@1295.4]
+  wire [3:0] _T_438; // @[Lookup.scala 11:37:@1296.4]
+  wire [3:0] _T_439; // @[Lookup.scala 11:37:@1297.4]
+  wire [3:0] _T_440; // @[Lookup.scala 11:37:@1298.4]
+  wire [3:0] _T_441; // @[Lookup.scala 11:37:@1299.4]
+  wire [3:0] _T_442; // @[Lookup.scala 11:37:@1300.4]
+  wire [3:0] _T_443; // @[Lookup.scala 11:37:@1301.4]
+  wire [3:0] _T_444; // @[Lookup.scala 11:37:@1302.4]
+  wire [3:0] _T_445; // @[Lookup.scala 11:37:@1303.4]
+  wire [3:0] _T_446; // @[Lookup.scala 11:37:@1304.4]
+  wire [3:0] _T_447; // @[Lookup.scala 11:37:@1305.4]
+  wire [3:0] _T_448; // @[Lookup.scala 11:37:@1306.4]
+  wire [3:0] _T_449; // @[Lookup.scala 11:37:@1307.4]
+  wire [3:0] _T_450; // @[Lookup.scala 11:37:@1308.4]
+  wire [3:0] _T_451; // @[Lookup.scala 11:37:@1309.4]
+  wire [3:0] _T_452; // @[Lookup.scala 11:37:@1310.4]
+  wire [3:0] _T_453; // @[Lookup.scala 11:37:@1311.4]
+  wire [3:0] _T_454; // @[Lookup.scala 11:37:@1312.4]
+  wire [3:0] _T_455; // @[Lookup.scala 11:37:@1313.4]
+  wire [3:0] _T_456; // @[Lookup.scala 11:37:@1314.4]
+  wire [3:0] _T_457; // @[Lookup.scala 11:37:@1315.4]
+  wire [3:0] _T_458; // @[Lookup.scala 11:37:@1316.4]
+  wire [3:0] _T_459; // @[Lookup.scala 11:37:@1317.4]
+  wire [3:0] _T_460; // @[Lookup.scala 11:37:@1318.4]
+  wire [3:0] _T_461; // @[Lookup.scala 11:37:@1319.4]
+  wire [3:0] _T_462; // @[Lookup.scala 11:37:@1320.4]
+  wire [3:0] _T_463; // @[Lookup.scala 11:37:@1321.4]
+  wire [3:0] _T_464; // @[Lookup.scala 11:37:@1322.4]
+  wire [3:0] _T_465; // @[Lookup.scala 11:37:@1323.4]
+  wire [3:0] _T_466; // @[Lookup.scala 11:37:@1324.4]
+  wire [3:0] _T_467; // @[Lookup.scala 11:37:@1325.4]
+  wire [3:0] _T_468; // @[Lookup.scala 11:37:@1326.4]
+  wire [3:0] _T_469; // @[Lookup.scala 11:37:@1327.4]
+  wire [3:0] _T_470; // @[Lookup.scala 11:37:@1328.4]
+  wire [3:0] _T_471; // @[Lookup.scala 11:37:@1329.4]
+  wire [3:0] _T_472; // @[Lookup.scala 11:37:@1330.4]
+  wire [3:0] ctrlSignals_4; // @[Lookup.scala 11:37:@1331.4]
+  wire [2:0] _T_512; // @[Lookup.scala 11:37:@1371.4]
+  wire [2:0] _T_513; // @[Lookup.scala 11:37:@1372.4]
+  wire [2:0] _T_514; // @[Lookup.scala 11:37:@1373.4]
+  wire [2:0] _T_515; // @[Lookup.scala 11:37:@1374.4]
+  wire [2:0] _T_516; // @[Lookup.scala 11:37:@1375.4]
+  wire [2:0] _T_517; // @[Lookup.scala 11:37:@1376.4]
+  wire [2:0] _T_518; // @[Lookup.scala 11:37:@1377.4]
+  wire [2:0] _T_519; // @[Lookup.scala 11:37:@1378.4]
+  wire [2:0] _T_520; // @[Lookup.scala 11:37:@1379.4]
+  wire  _T_523; // @[Lookup.scala 11:37:@1383.4]
+  wire  _T_524; // @[Lookup.scala 11:37:@1384.4]
+  wire  _T_525; // @[Lookup.scala 11:37:@1385.4]
+  wire  _T_526; // @[Lookup.scala 11:37:@1386.4]
+  wire  _T_527; // @[Lookup.scala 11:37:@1387.4]
+  wire  _T_528; // @[Lookup.scala 11:37:@1388.4]
+  wire  _T_529; // @[Lookup.scala 11:37:@1389.4]
+  wire  _T_530; // @[Lookup.scala 11:37:@1390.4]
+  wire  _T_531; // @[Lookup.scala 11:37:@1391.4]
+  wire  _T_532; // @[Lookup.scala 11:37:@1392.4]
+  wire  _T_533; // @[Lookup.scala 11:37:@1393.4]
+  wire  _T_534; // @[Lookup.scala 11:37:@1394.4]
+  wire  _T_535; // @[Lookup.scala 11:37:@1395.4]
+  wire  _T_536; // @[Lookup.scala 11:37:@1396.4]
+  wire  _T_537; // @[Lookup.scala 11:37:@1397.4]
+  wire  _T_538; // @[Lookup.scala 11:37:@1398.4]
+  wire  _T_539; // @[Lookup.scala 11:37:@1399.4]
+  wire  _T_540; // @[Lookup.scala 11:37:@1400.4]
+  wire  _T_541; // @[Lookup.scala 11:37:@1401.4]
+  wire  _T_542; // @[Lookup.scala 11:37:@1402.4]
+  wire  _T_543; // @[Lookup.scala 11:37:@1403.4]
+  wire  _T_544; // @[Lookup.scala 11:37:@1404.4]
+  wire  _T_545; // @[Lookup.scala 11:37:@1405.4]
+  wire  _T_546; // @[Lookup.scala 11:37:@1406.4]
+  wire  _T_547; // @[Lookup.scala 11:37:@1407.4]
+  wire  _T_548; // @[Lookup.scala 11:37:@1408.4]
+  wire  _T_549; // @[Lookup.scala 11:37:@1409.4]
+  wire  _T_550; // @[Lookup.scala 11:37:@1410.4]
+  wire  _T_551; // @[Lookup.scala 11:37:@1411.4]
+  wire  _T_552; // @[Lookup.scala 11:37:@1412.4]
+  wire  _T_553; // @[Lookup.scala 11:37:@1413.4]
+  wire  _T_554; // @[Lookup.scala 11:37:@1414.4]
+  wire  _T_555; // @[Lookup.scala 11:37:@1415.4]
+  wire  _T_556; // @[Lookup.scala 11:37:@1416.4]
+  wire  _T_557; // @[Lookup.scala 11:37:@1417.4]
+  wire  _T_558; // @[Lookup.scala 11:37:@1418.4]
+  wire  _T_559; // @[Lookup.scala 11:37:@1419.4]
+  wire  _T_560; // @[Lookup.scala 11:37:@1420.4]
+  wire  _T_561; // @[Lookup.scala 11:37:@1421.4]
+  wire  _T_562; // @[Lookup.scala 11:37:@1422.4]
+  wire  _T_563; // @[Lookup.scala 11:37:@1423.4]
+  wire  _T_564; // @[Lookup.scala 11:37:@1424.4]
+  wire  _T_565; // @[Lookup.scala 11:37:@1425.4]
+  wire  _T_566; // @[Lookup.scala 11:37:@1426.4]
+  wire  _T_567; // @[Lookup.scala 11:37:@1427.4]
+  wire  _T_568; // @[Lookup.scala 11:37:@1428.4]
+  wire [1:0] _T_600; // @[Lookup.scala 11:37:@1461.4]
+  wire [1:0] _T_601; // @[Lookup.scala 11:37:@1462.4]
+  wire [1:0] _T_602; // @[Lookup.scala 11:37:@1463.4]
+  wire [1:0] _T_603; // @[Lookup.scala 11:37:@1464.4]
+  wire [1:0] _T_604; // @[Lookup.scala 11:37:@1465.4]
+  wire [1:0] _T_605; // @[Lookup.scala 11:37:@1466.4]
+  wire [1:0] _T_606; // @[Lookup.scala 11:37:@1467.4]
+  wire [1:0] _T_607; // @[Lookup.scala 11:37:@1468.4]
+  wire [1:0] _T_608; // @[Lookup.scala 11:37:@1469.4]
+  wire [1:0] _T_609; // @[Lookup.scala 11:37:@1470.4]
+  wire [1:0] _T_610; // @[Lookup.scala 11:37:@1471.4]
+  wire [1:0] _T_611; // @[Lookup.scala 11:37:@1472.4]
+  wire [1:0] _T_612; // @[Lookup.scala 11:37:@1473.4]
+  wire [1:0] _T_613; // @[Lookup.scala 11:37:@1474.4]
+  wire [1:0] _T_614; // @[Lookup.scala 11:37:@1475.4]
+  wire [1:0] _T_615; // @[Lookup.scala 11:37:@1476.4]
+  wire [1:0] _T_616; // @[Lookup.scala 11:37:@1477.4]
+  wire [2:0] _T_651; // @[Lookup.scala 11:37:@1513.4]
+  wire [2:0] _T_652; // @[Lookup.scala 11:37:@1514.4]
+  wire [2:0] _T_653; // @[Lookup.scala 11:37:@1515.4]
+  wire [2:0] _T_654; // @[Lookup.scala 11:37:@1516.4]
+  wire [2:0] _T_655; // @[Lookup.scala 11:37:@1517.4]
+  wire [2:0] _T_656; // @[Lookup.scala 11:37:@1518.4]
+  wire [2:0] _T_657; // @[Lookup.scala 11:37:@1519.4]
+  wire [2:0] _T_658; // @[Lookup.scala 11:37:@1520.4]
+  wire [2:0] _T_659; // @[Lookup.scala 11:37:@1521.4]
+  wire [2:0] _T_660; // @[Lookup.scala 11:37:@1522.4]
+  wire [2:0] _T_661; // @[Lookup.scala 11:37:@1523.4]
+  wire [2:0] _T_662; // @[Lookup.scala 11:37:@1524.4]
+  wire [2:0] _T_663; // @[Lookup.scala 11:37:@1525.4]
+  wire [2:0] _T_664; // @[Lookup.scala 11:37:@1526.4]
+  wire [1:0] _T_667; // @[Lookup.scala 11:37:@1530.4]
+  wire [1:0] _T_668; // @[Lookup.scala 11:37:@1531.4]
+  wire [1:0] _T_669; // @[Lookup.scala 11:37:@1532.4]
+  wire [1:0] _T_670; // @[Lookup.scala 11:37:@1533.4]
+  wire [1:0] _T_671; // @[Lookup.scala 11:37:@1534.4]
+  wire [1:0] _T_672; // @[Lookup.scala 11:37:@1535.4]
+  wire [1:0] _T_673; // @[Lookup.scala 11:37:@1536.4]
+  wire [1:0] _T_674; // @[Lookup.scala 11:37:@1537.4]
+  wire [1:0] _T_675; // @[Lookup.scala 11:37:@1538.4]
+  wire [1:0] _T_676; // @[Lookup.scala 11:37:@1539.4]
+  wire [1:0] _T_677; // @[Lookup.scala 11:37:@1540.4]
+  wire [1:0] _T_678; // @[Lookup.scala 11:37:@1541.4]
+  wire [1:0] _T_679; // @[Lookup.scala 11:37:@1542.4]
+  wire [1:0] _T_680; // @[Lookup.scala 11:37:@1543.4]
+  wire [1:0] _T_681; // @[Lookup.scala 11:37:@1544.4]
+  wire [1:0] _T_682; // @[Lookup.scala 11:37:@1545.4]
+  wire [1:0] _T_683; // @[Lookup.scala 11:37:@1546.4]
+  wire [1:0] _T_684; // @[Lookup.scala 11:37:@1547.4]
+  wire [1:0] _T_685; // @[Lookup.scala 11:37:@1548.4]
+  wire [1:0] _T_686; // @[Lookup.scala 11:37:@1549.4]
+  wire [1:0] _T_687; // @[Lookup.scala 11:37:@1550.4]
+  wire [1:0] _T_688; // @[Lookup.scala 11:37:@1551.4]
+  wire [1:0] _T_689; // @[Lookup.scala 11:37:@1552.4]
+  wire [1:0] _T_690; // @[Lookup.scala 11:37:@1553.4]
+  wire [1:0] _T_691; // @[Lookup.scala 11:37:@1554.4]
+  wire [1:0] _T_692; // @[Lookup.scala 11:37:@1555.4]
+  wire [1:0] _T_693; // @[Lookup.scala 11:37:@1556.4]
+  wire [1:0] _T_694; // @[Lookup.scala 11:37:@1557.4]
+  wire [1:0] _T_695; // @[Lookup.scala 11:37:@1558.4]
+  wire [1:0] _T_696; // @[Lookup.scala 11:37:@1559.4]
+  wire [1:0] _T_697; // @[Lookup.scala 11:37:@1560.4]
+  wire [1:0] _T_698; // @[Lookup.scala 11:37:@1561.4]
+  wire [1:0] _T_699; // @[Lookup.scala 11:37:@1562.4]
+  wire [1:0] _T_700; // @[Lookup.scala 11:37:@1563.4]
+  wire [1:0] _T_701; // @[Lookup.scala 11:37:@1564.4]
+  wire [1:0] _T_702; // @[Lookup.scala 11:37:@1565.4]
+  wire [1:0] _T_703; // @[Lookup.scala 11:37:@1566.4]
+  wire [1:0] _T_704; // @[Lookup.scala 11:37:@1567.4]
+  wire [1:0] _T_705; // @[Lookup.scala 11:37:@1568.4]
+  wire [1:0] _T_706; // @[Lookup.scala 11:37:@1569.4]
+  wire [1:0] _T_707; // @[Lookup.scala 11:37:@1570.4]
+  wire [1:0] _T_708; // @[Lookup.scala 11:37:@1571.4]
+  wire [1:0] _T_709; // @[Lookup.scala 11:37:@1572.4]
+  wire [1:0] _T_710; // @[Lookup.scala 11:37:@1573.4]
+  wire [1:0] _T_711; // @[Lookup.scala 11:37:@1574.4]
+  wire [1:0] _T_712; // @[Lookup.scala 11:37:@1575.4]
+  wire  _T_718; // @[Lookup.scala 11:37:@1582.4]
+  wire  _T_719; // @[Lookup.scala 11:37:@1583.4]
+  wire  _T_720; // @[Lookup.scala 11:37:@1584.4]
+  wire  _T_721; // @[Lookup.scala 11:37:@1585.4]
+  wire  _T_722; // @[Lookup.scala 11:37:@1586.4]
+  wire  _T_723; // @[Lookup.scala 11:37:@1587.4]
+  wire  _T_724; // @[Lookup.scala 11:37:@1588.4]
+  wire  _T_725; // @[Lookup.scala 11:37:@1589.4]
+  wire  _T_726; // @[Lookup.scala 11:37:@1590.4]
+  wire  _T_727; // @[Lookup.scala 11:37:@1591.4]
+  wire  _T_728; // @[Lookup.scala 11:37:@1592.4]
+  wire  _T_729; // @[Lookup.scala 11:37:@1593.4]
+  wire  _T_730; // @[Lookup.scala 11:37:@1594.4]
+  wire  _T_731; // @[Lookup.scala 11:37:@1595.4]
+  wire  _T_732; // @[Lookup.scala 11:37:@1596.4]
+  wire  _T_733; // @[Lookup.scala 11:37:@1597.4]
+  wire  _T_734; // @[Lookup.scala 11:37:@1598.4]
+  wire  _T_735; // @[Lookup.scala 11:37:@1599.4]
+  wire  _T_736; // @[Lookup.scala 11:37:@1600.4]
+  wire  _T_737; // @[Lookup.scala 11:37:@1601.4]
+  wire  _T_738; // @[Lookup.scala 11:37:@1602.4]
+  wire  _T_739; // @[Lookup.scala 11:37:@1603.4]
+  wire  _T_740; // @[Lookup.scala 11:37:@1604.4]
+  wire  _T_741; // @[Lookup.scala 11:37:@1605.4]
+  wire  _T_742; // @[Lookup.scala 11:37:@1606.4]
+  wire  _T_743; // @[Lookup.scala 11:37:@1607.4]
+  wire  _T_744; // @[Lookup.scala 11:37:@1608.4]
+  wire  _T_745; // @[Lookup.scala 11:37:@1609.4]
+  wire  _T_746; // @[Lookup.scala 11:37:@1610.4]
+  wire  _T_747; // @[Lookup.scala 11:37:@1611.4]
+  wire  _T_748; // @[Lookup.scala 11:37:@1612.4]
+  wire  _T_749; // @[Lookup.scala 11:37:@1613.4]
+  wire  _T_750; // @[Lookup.scala 11:37:@1614.4]
+  wire  _T_751; // @[Lookup.scala 11:37:@1615.4]
+  wire  _T_752; // @[Lookup.scala 11:37:@1616.4]
+  wire  _T_753; // @[Lookup.scala 11:37:@1617.4]
+  wire  _T_754; // @[Lookup.scala 11:37:@1618.4]
+  wire  _T_755; // @[Lookup.scala 11:37:@1619.4]
+  wire  _T_756; // @[Lookup.scala 11:37:@1620.4]
+  wire  _T_757; // @[Lookup.scala 11:37:@1621.4]
+  wire  _T_758; // @[Lookup.scala 11:37:@1622.4]
+  wire  _T_759; // @[Lookup.scala 11:37:@1623.4]
+  wire  _T_760; // @[Lookup.scala 11:37:@1624.4]
+  wire [2:0] _T_762; // @[Lookup.scala 11:37:@1627.4]
+  wire [2:0] _T_763; // @[Lookup.scala 11:37:@1628.4]
+  wire [2:0] _T_764; // @[Lookup.scala 11:37:@1629.4]
+  wire [2:0] _T_765; // @[Lookup.scala 11:37:@1630.4]
+  wire [2:0] _T_766; // @[Lookup.scala 11:37:@1631.4]
+  wire [2:0] _T_767; // @[Lookup.scala 11:37:@1632.4]
+  wire [2:0] _T_768; // @[Lookup.scala 11:37:@1633.4]
+  wire [2:0] _T_769; // @[Lookup.scala 11:37:@1634.4]
+  wire [2:0] _T_770; // @[Lookup.scala 11:37:@1635.4]
+  wire [2:0] _T_771; // @[Lookup.scala 11:37:@1636.4]
+  wire [2:0] _T_772; // @[Lookup.scala 11:37:@1637.4]
+  wire [2:0] _T_773; // @[Lookup.scala 11:37:@1638.4]
+  wire [2:0] _T_774; // @[Lookup.scala 11:37:@1639.4]
+  wire [2:0] _T_775; // @[Lookup.scala 11:37:@1640.4]
+  wire [2:0] _T_776; // @[Lookup.scala 11:37:@1641.4]
+  wire [2:0] _T_777; // @[Lookup.scala 11:37:@1642.4]
+  wire [2:0] _T_778; // @[Lookup.scala 11:37:@1643.4]
+  wire [2:0] _T_779; // @[Lookup.scala 11:37:@1644.4]
+  wire [2:0] _T_780; // @[Lookup.scala 11:37:@1645.4]
+  wire [2:0] _T_781; // @[Lookup.scala 11:37:@1646.4]
+  wire [2:0] _T_782; // @[Lookup.scala 11:37:@1647.4]
+  wire [2:0] _T_783; // @[Lookup.scala 11:37:@1648.4]
+  wire [2:0] _T_784; // @[Lookup.scala 11:37:@1649.4]
+  wire [2:0] _T_785; // @[Lookup.scala 11:37:@1650.4]
+  wire [2:0] _T_786; // @[Lookup.scala 11:37:@1651.4]
+  wire [2:0] _T_787; // @[Lookup.scala 11:37:@1652.4]
+  wire [2:0] _T_788; // @[Lookup.scala 11:37:@1653.4]
+  wire [2:0] _T_789; // @[Lookup.scala 11:37:@1654.4]
+  wire [2:0] _T_790; // @[Lookup.scala 11:37:@1655.4]
+  wire [2:0] _T_791; // @[Lookup.scala 11:37:@1656.4]
+  wire [2:0] _T_792; // @[Lookup.scala 11:37:@1657.4]
+  wire [2:0] _T_793; // @[Lookup.scala 11:37:@1658.4]
+  wire [2:0] _T_794; // @[Lookup.scala 11:37:@1659.4]
+  wire [2:0] _T_795; // @[Lookup.scala 11:37:@1660.4]
+  wire [2:0] _T_796; // @[Lookup.scala 11:37:@1661.4]
+  wire [2:0] _T_797; // @[Lookup.scala 11:37:@1662.4]
+  wire [2:0] _T_798; // @[Lookup.scala 11:37:@1663.4]
+  wire [2:0] _T_799; // @[Lookup.scala 11:37:@1664.4]
+  wire [2:0] _T_800; // @[Lookup.scala 11:37:@1665.4]
+  wire [2:0] _T_801; // @[Lookup.scala 11:37:@1666.4]
+  wire [2:0] _T_802; // @[Lookup.scala 11:37:@1667.4]
+  wire [2:0] _T_803; // @[Lookup.scala 11:37:@1668.4]
+  wire [2:0] _T_804; // @[Lookup.scala 11:37:@1669.4]
+  wire [2:0] _T_805; // @[Lookup.scala 11:37:@1670.4]
+  wire [2:0] _T_806; // @[Lookup.scala 11:37:@1671.4]
+  wire [2:0] _T_807; // @[Lookup.scala 11:37:@1672.4]
+  wire [2:0] _T_808; // @[Lookup.scala 11:37:@1673.4]
+  wire  _T_809; // @[Lookup.scala 11:37:@1675.4]
+  wire  _T_810; // @[Lookup.scala 11:37:@1676.4]
+  wire  _T_811; // @[Lookup.scala 11:37:@1677.4]
+  wire  _T_812; // @[Lookup.scala 11:37:@1678.4]
+  wire  _T_813; // @[Lookup.scala 11:37:@1679.4]
+  wire  _T_814; // @[Lookup.scala 11:37:@1680.4]
+  wire  _T_815; // @[Lookup.scala 11:37:@1681.4]
+  wire  _T_816; // @[Lookup.scala 11:37:@1682.4]
+  wire  _T_817; // @[Lookup.scala 11:37:@1683.4]
+  wire  _T_818; // @[Lookup.scala 11:37:@1684.4]
+  wire  _T_819; // @[Lookup.scala 11:37:@1685.4]
+  wire  _T_820; // @[Lookup.scala 11:37:@1686.4]
+  wire  _T_821; // @[Lookup.scala 11:37:@1687.4]
+  wire  _T_822; // @[Lookup.scala 11:37:@1688.4]
+  wire  _T_823; // @[Lookup.scala 11:37:@1689.4]
+  wire  _T_824; // @[Lookup.scala 11:37:@1690.4]
+  wire  _T_825; // @[Lookup.scala 11:37:@1691.4]
+  wire  _T_826; // @[Lookup.scala 11:37:@1692.4]
+  wire  _T_827; // @[Lookup.scala 11:37:@1693.4]
+  wire  _T_828; // @[Lookup.scala 11:37:@1694.4]
+  wire  _T_829; // @[Lookup.scala 11:37:@1695.4]
+  wire  _T_830; // @[Lookup.scala 11:37:@1696.4]
+  wire  _T_831; // @[Lookup.scala 11:37:@1697.4]
+  wire  _T_832; // @[Lookup.scala 11:37:@1698.4]
+  wire  _T_833; // @[Lookup.scala 11:37:@1699.4]
+  wire  _T_834; // @[Lookup.scala 11:37:@1700.4]
+  wire  _T_835; // @[Lookup.scala 11:37:@1701.4]
+  wire  _T_836; // @[Lookup.scala 11:37:@1702.4]
+  wire  _T_837; // @[Lookup.scala 11:37:@1703.4]
+  wire  _T_838; // @[Lookup.scala 11:37:@1704.4]
+  wire  _T_839; // @[Lookup.scala 11:37:@1705.4]
+  wire  _T_840; // @[Lookup.scala 11:37:@1706.4]
+  wire  _T_841; // @[Lookup.scala 11:37:@1707.4]
+  wire  _T_842; // @[Lookup.scala 11:37:@1708.4]
+  wire  _T_843; // @[Lookup.scala 11:37:@1709.4]
+  wire  _T_844; // @[Lookup.scala 11:37:@1710.4]
+  wire  _T_845; // @[Lookup.scala 11:37:@1711.4]
+  wire  _T_846; // @[Lookup.scala 11:37:@1712.4]
+  wire  _T_847; // @[Lookup.scala 11:37:@1713.4]
+  wire  _T_848; // @[Lookup.scala 11:37:@1714.4]
+  wire  _T_849; // @[Lookup.scala 11:37:@1715.4]
+  wire  _T_850; // @[Lookup.scala 11:37:@1716.4]
+  wire  _T_851; // @[Lookup.scala 11:37:@1717.4]
+  wire  _T_852; // @[Lookup.scala 11:37:@1718.4]
+  wire  _T_853; // @[Lookup.scala 11:37:@1719.4]
+  wire  _T_854; // @[Lookup.scala 11:37:@1720.4]
+  wire  _T_855; // @[Lookup.scala 11:37:@1721.4]
+  wire  _T_856; // @[Lookup.scala 11:37:@1722.4]
+  wire  _T_896; // @[Lookup.scala 11:37:@1763.4]
+  wire  _T_897; // @[Lookup.scala 11:37:@1764.4]
+  wire  _T_898; // @[Lookup.scala 11:37:@1765.4]
+  wire  _T_899; // @[Lookup.scala 11:37:@1766.4]
+  wire  _T_900; // @[Lookup.scala 11:37:@1767.4]
+  wire  _T_901; // @[Lookup.scala 11:37:@1768.4]
+  wire  _T_902; // @[Lookup.scala 11:37:@1769.4]
+  wire  _T_903; // @[Lookup.scala 11:37:@1770.4]
+  wire  _T_904; // @[Lookup.scala 11:37:@1771.4]
+  wire  _T_936; // @[Lookup.scala 11:37:@1804.4]
+  wire  _T_937; // @[Lookup.scala 11:37:@1805.4]
+  wire  _T_938; // @[Lookup.scala 11:37:@1806.4]
+  wire  _T_939; // @[Lookup.scala 11:37:@1807.4]
+  wire  _T_940; // @[Lookup.scala 11:37:@1808.4]
+  wire  _T_941; // @[Lookup.scala 11:37:@1809.4]
+  wire  _T_942; // @[Lookup.scala 11:37:@1810.4]
+  wire  _T_943; // @[Lookup.scala 11:37:@1811.4]
+  wire  _T_944; // @[Lookup.scala 11:37:@1812.4]
+  wire  _T_945; // @[Lookup.scala 11:37:@1813.4]
+  wire  _T_946; // @[Lookup.scala 11:37:@1814.4]
+  wire  _T_947; // @[Lookup.scala 11:37:@1815.4]
+  wire  _T_948; // @[Lookup.scala 11:37:@1816.4]
+  wire  _T_949; // @[Lookup.scala 11:37:@1817.4]
+  wire  _T_950; // @[Lookup.scala 11:37:@1818.4]
+  wire  _T_951; // @[Lookup.scala 11:37:@1819.4]
+  wire  _T_952; // @[Lookup.scala 11:37:@1820.4]
+  assign _T_39 = io_inst & 32'h7f; // @[Lookup.scala 9:38:@989.4]
+  assign _T_40 = 32'h37 == _T_39; // @[Lookup.scala 9:38:@990.4]
+  assign _T_44 = 32'h17 == _T_39; // @[Lookup.scala 9:38:@992.4]
+  assign _T_48 = 32'h6f == _T_39; // @[Lookup.scala 9:38:@994.4]
+  assign _T_51 = io_inst & 32'h707f; // @[Lookup.scala 9:38:@995.4]
+  assign _T_52 = 32'h67 == _T_51; // @[Lookup.scala 9:38:@996.4]
+  assign _T_56 = 32'h63 == _T_51; // @[Lookup.scala 9:38:@998.4]
+  assign _T_60 = 32'h1063 == _T_51; // @[Lookup.scala 9:38:@1000.4]
+  assign _T_64 = 32'h4063 == _T_51; // @[Lookup.scala 9:38:@1002.4]
+  assign _T_68 = 32'h5063 == _T_51; // @[Lookup.scala 9:38:@1004.4]
+  assign _T_72 = 32'h6063 == _T_51; // @[Lookup.scala 9:38:@1006.4]
+  assign _T_76 = 32'h7063 == _T_51; // @[Lookup.scala 9:38:@1008.4]
+  assign _T_80 = 32'h3 == _T_51; // @[Lookup.scala 9:38:@1010.4]
+  assign _T_84 = 32'h1003 == _T_51; // @[Lookup.scala 9:38:@1012.4]
+  assign _T_88 = 32'h2003 == _T_51; // @[Lookup.scala 9:38:@1014.4]
+  assign _T_92 = 32'h4003 == _T_51; // @[Lookup.scala 9:38:@1016.4]
+  assign _T_96 = 32'h5003 == _T_51; // @[Lookup.scala 9:38:@1018.4]
+  assign _T_100 = 32'h23 == _T_51; // @[Lookup.scala 9:38:@1020.4]
+  assign _T_104 = 32'h1023 == _T_51; // @[Lookup.scala 9:38:@1022.4]
+  assign _T_108 = 32'h2023 == _T_51; // @[Lookup.scala 9:38:@1024.4]
+  assign _T_112 = 32'h13 == _T_51; // @[Lookup.scala 9:38:@1026.4]
+  assign _T_116 = 32'h2013 == _T_51; // @[Lookup.scala 9:38:@1028.4]
+  assign _T_120 = 32'h3013 == _T_51; // @[Lookup.scala 9:38:@1030.4]
+  assign _T_124 = 32'h4013 == _T_51; // @[Lookup.scala 9:38:@1032.4]
+  assign _T_128 = 32'h6013 == _T_51; // @[Lookup.scala 9:38:@1034.4]
+  assign _T_132 = 32'h7013 == _T_51; // @[Lookup.scala 9:38:@1036.4]
+  assign _T_135 = io_inst & 32'hfe00707f; // @[Lookup.scala 9:38:@1037.4]
+  assign _T_136 = 32'h1013 == _T_135; // @[Lookup.scala 9:38:@1038.4]
+  assign _T_140 = 32'h5013 == _T_135; // @[Lookup.scala 9:38:@1040.4]
+  assign _T_144 = 32'h40005013 == _T_135; // @[Lookup.scala 9:38:@1042.4]
+  assign _T_148 = 32'h33 == _T_135; // @[Lookup.scala 9:38:@1044.4]
+  assign _T_152 = 32'h40000033 == _T_135; // @[Lookup.scala 9:38:@1046.4]
+  assign _T_156 = 32'h1033 == _T_135; // @[Lookup.scala 9:38:@1048.4]
+  assign _T_160 = 32'h2033 == _T_135; // @[Lookup.scala 9:38:@1050.4]
+  assign _T_164 = 32'h3033 == _T_135; // @[Lookup.scala 9:38:@1052.4]
+  assign _T_168 = 32'h4033 == _T_135; // @[Lookup.scala 9:38:@1054.4]
+  assign _T_172 = 32'h5033 == _T_135; // @[Lookup.scala 9:38:@1056.4]
+  assign _T_176 = 32'h40005033 == _T_135; // @[Lookup.scala 9:38:@1058.4]
+  assign _T_180 = 32'h6033 == _T_135; // @[Lookup.scala 9:38:@1060.4]
+  assign _T_184 = 32'h7033 == _T_135; // @[Lookup.scala 9:38:@1062.4]
+  assign _T_187 = io_inst & 32'hf00fffff; // @[Lookup.scala 9:38:@1063.4]
+  assign _T_188 = 32'hf == _T_187; // @[Lookup.scala 9:38:@1064.4]
+  assign _T_192 = 32'h100f == io_inst; // @[Lookup.scala 9:38:@1066.4]
+  assign _T_196 = 32'h1073 == _T_51; // @[Lookup.scala 9:38:@1068.4]
+  assign _T_200 = 32'h2073 == _T_51; // @[Lookup.scala 9:38:@1070.4]
+  assign _T_204 = 32'h3073 == _T_51; // @[Lookup.scala 9:38:@1072.4]
+  assign _T_208 = 32'h5073 == _T_51; // @[Lookup.scala 9:38:@1074.4]
+  assign _T_212 = 32'h6073 == _T_51; // @[Lookup.scala 9:38:@1076.4]
+  assign _T_216 = 32'h7073 == _T_51; // @[Lookup.scala 9:38:@1078.4]
+  assign _T_220 = 32'h73 == io_inst; // @[Lookup.scala 9:38:@1080.4]
+  assign _T_224 = 32'h100073 == io_inst; // @[Lookup.scala 9:38:@1082.4]
+  assign _T_228 = 32'h30200073 == io_inst; // @[Lookup.scala 9:38:@1084.4]
+  assign _T_232 = 32'h10500073 == io_inst; // @[Lookup.scala 9:38:@1086.4]
+  assign _T_234 = _T_228 ? 2'h3 : 2'h0; // @[Lookup.scala 11:37:@1088.4]
+  assign _T_235 = _T_224 ? 2'h0 : _T_234; // @[Lookup.scala 11:37:@1089.4]
+  assign _T_236 = _T_220 ? 2'h0 : _T_235; // @[Lookup.scala 11:37:@1090.4]
+  assign _T_237 = _T_216 ? 2'h0 : _T_236; // @[Lookup.scala 11:37:@1091.4]
+  assign _T_238 = _T_212 ? 2'h0 : _T_237; // @[Lookup.scala 11:37:@1092.4]
+  assign _T_239 = _T_208 ? 2'h0 : _T_238; // @[Lookup.scala 11:37:@1093.4]
+  assign _T_240 = _T_204 ? 2'h0 : _T_239; // @[Lookup.scala 11:37:@1094.4]
+  assign _T_241 = _T_200 ? 2'h0 : _T_240; // @[Lookup.scala 11:37:@1095.4]
+  assign _T_242 = _T_196 ? 2'h0 : _T_241; // @[Lookup.scala 11:37:@1096.4]
+  assign _T_243 = _T_192 ? 2'h2 : _T_242; // @[Lookup.scala 11:37:@1097.4]
+  assign _T_244 = _T_188 ? 2'h0 : _T_243; // @[Lookup.scala 11:37:@1098.4]
+  assign _T_245 = _T_184 ? 2'h0 : _T_244; // @[Lookup.scala 11:37:@1099.4]
+  assign _T_246 = _T_180 ? 2'h0 : _T_245; // @[Lookup.scala 11:37:@1100.4]
+  assign _T_247 = _T_176 ? 2'h0 : _T_246; // @[Lookup.scala 11:37:@1101.4]
+  assign _T_248 = _T_172 ? 2'h0 : _T_247; // @[Lookup.scala 11:37:@1102.4]
+  assign _T_249 = _T_168 ? 2'h0 : _T_248; // @[Lookup.scala 11:37:@1103.4]
+  assign _T_250 = _T_164 ? 2'h0 : _T_249; // @[Lookup.scala 11:37:@1104.4]
+  assign _T_251 = _T_160 ? 2'h0 : _T_250; // @[Lookup.scala 11:37:@1105.4]
+  assign _T_252 = _T_156 ? 2'h0 : _T_251; // @[Lookup.scala 11:37:@1106.4]
+  assign _T_253 = _T_152 ? 2'h0 : _T_252; // @[Lookup.scala 11:37:@1107.4]
+  assign _T_254 = _T_148 ? 2'h0 : _T_253; // @[Lookup.scala 11:37:@1108.4]
+  assign _T_255 = _T_144 ? 2'h0 : _T_254; // @[Lookup.scala 11:37:@1109.4]
+  assign _T_256 = _T_140 ? 2'h0 : _T_255; // @[Lookup.scala 11:37:@1110.4]
+  assign _T_257 = _T_136 ? 2'h0 : _T_256; // @[Lookup.scala 11:37:@1111.4]
+  assign _T_258 = _T_132 ? 2'h0 : _T_257; // @[Lookup.scala 11:37:@1112.4]
+  assign _T_259 = _T_128 ? 2'h0 : _T_258; // @[Lookup.scala 11:37:@1113.4]
+  assign _T_260 = _T_124 ? 2'h0 : _T_259; // @[Lookup.scala 11:37:@1114.4]
+  assign _T_261 = _T_120 ? 2'h0 : _T_260; // @[Lookup.scala 11:37:@1115.4]
+  assign _T_262 = _T_116 ? 2'h0 : _T_261; // @[Lookup.scala 11:37:@1116.4]
+  assign _T_263 = _T_112 ? 2'h0 : _T_262; // @[Lookup.scala 11:37:@1117.4]
+  assign _T_264 = _T_108 ? 2'h0 : _T_263; // @[Lookup.scala 11:37:@1118.4]
+  assign _T_265 = _T_104 ? 2'h0 : _T_264; // @[Lookup.scala 11:37:@1119.4]
+  assign _T_266 = _T_100 ? 2'h0 : _T_265; // @[Lookup.scala 11:37:@1120.4]
+  assign _T_267 = _T_96 ? 2'h0 : _T_266; // @[Lookup.scala 11:37:@1121.4]
+  assign _T_268 = _T_92 ? 2'h0 : _T_267; // @[Lookup.scala 11:37:@1122.4]
+  assign _T_269 = _T_88 ? 2'h0 : _T_268; // @[Lookup.scala 11:37:@1123.4]
+  assign _T_270 = _T_84 ? 2'h0 : _T_269; // @[Lookup.scala 11:37:@1124.4]
+  assign _T_271 = _T_80 ? 2'h0 : _T_270; // @[Lookup.scala 11:37:@1125.4]
+  assign _T_272 = _T_76 ? 2'h0 : _T_271; // @[Lookup.scala 11:37:@1126.4]
+  assign _T_273 = _T_72 ? 2'h0 : _T_272; // @[Lookup.scala 11:37:@1127.4]
+  assign _T_274 = _T_68 ? 2'h0 : _T_273; // @[Lookup.scala 11:37:@1128.4]
+  assign _T_275 = _T_64 ? 2'h0 : _T_274; // @[Lookup.scala 11:37:@1129.4]
+  assign _T_276 = _T_60 ? 2'h0 : _T_275; // @[Lookup.scala 11:37:@1130.4]
+  assign _T_277 = _T_56 ? 2'h0 : _T_276; // @[Lookup.scala 11:37:@1131.4]
+  assign _T_278 = _T_52 ? 2'h1 : _T_277; // @[Lookup.scala 11:37:@1132.4]
+  assign _T_279 = _T_48 ? 2'h1 : _T_278; // @[Lookup.scala 11:37:@1133.4]
+  assign _T_280 = _T_44 ? 2'h0 : _T_279; // @[Lookup.scala 11:37:@1134.4]
+  assign _T_289 = _T_200 ? 1'h1 : _T_204; // @[Lookup.scala 11:37:@1144.4]
+  assign _T_290 = _T_196 ? 1'h1 : _T_289; // @[Lookup.scala 11:37:@1145.4]
+  assign _T_291 = _T_192 ? 1'h0 : _T_290; // @[Lookup.scala 11:37:@1146.4]
+  assign _T_292 = _T_188 ? 1'h0 : _T_291; // @[Lookup.scala 11:37:@1147.4]
+  assign _T_293 = _T_184 ? 1'h1 : _T_292; // @[Lookup.scala 11:37:@1148.4]
+  assign _T_294 = _T_180 ? 1'h1 : _T_293; // @[Lookup.scala 11:37:@1149.4]
+  assign _T_295 = _T_176 ? 1'h1 : _T_294; // @[Lookup.scala 11:37:@1150.4]
+  assign _T_296 = _T_172 ? 1'h1 : _T_295; // @[Lookup.scala 11:37:@1151.4]
+  assign _T_297 = _T_168 ? 1'h1 : _T_296; // @[Lookup.scala 11:37:@1152.4]
+  assign _T_298 = _T_164 ? 1'h1 : _T_297; // @[Lookup.scala 11:37:@1153.4]
+  assign _T_299 = _T_160 ? 1'h1 : _T_298; // @[Lookup.scala 11:37:@1154.4]
+  assign _T_300 = _T_156 ? 1'h1 : _T_299; // @[Lookup.scala 11:37:@1155.4]
+  assign _T_301 = _T_152 ? 1'h1 : _T_300; // @[Lookup.scala 11:37:@1156.4]
+  assign _T_302 = _T_148 ? 1'h1 : _T_301; // @[Lookup.scala 11:37:@1157.4]
+  assign _T_303 = _T_144 ? 1'h1 : _T_302; // @[Lookup.scala 11:37:@1158.4]
+  assign _T_304 = _T_140 ? 1'h1 : _T_303; // @[Lookup.scala 11:37:@1159.4]
+  assign _T_305 = _T_136 ? 1'h1 : _T_304; // @[Lookup.scala 11:37:@1160.4]
+  assign _T_306 = _T_132 ? 1'h1 : _T_305; // @[Lookup.scala 11:37:@1161.4]
+  assign _T_307 = _T_128 ? 1'h1 : _T_306; // @[Lookup.scala 11:37:@1162.4]
+  assign _T_308 = _T_124 ? 1'h1 : _T_307; // @[Lookup.scala 11:37:@1163.4]
+  assign _T_309 = _T_120 ? 1'h1 : _T_308; // @[Lookup.scala 11:37:@1164.4]
+  assign _T_310 = _T_116 ? 1'h1 : _T_309; // @[Lookup.scala 11:37:@1165.4]
+  assign _T_311 = _T_112 ? 1'h1 : _T_310; // @[Lookup.scala 11:37:@1166.4]
+  assign _T_312 = _T_108 ? 1'h1 : _T_311; // @[Lookup.scala 11:37:@1167.4]
+  assign _T_313 = _T_104 ? 1'h1 : _T_312; // @[Lookup.scala 11:37:@1168.4]
+  assign _T_314 = _T_100 ? 1'h1 : _T_313; // @[Lookup.scala 11:37:@1169.4]
+  assign _T_315 = _T_96 ? 1'h1 : _T_314; // @[Lookup.scala 11:37:@1170.4]
+  assign _T_316 = _T_92 ? 1'h1 : _T_315; // @[Lookup.scala 11:37:@1171.4]
+  assign _T_317 = _T_88 ? 1'h1 : _T_316; // @[Lookup.scala 11:37:@1172.4]
+  assign _T_318 = _T_84 ? 1'h1 : _T_317; // @[Lookup.scala 11:37:@1173.4]
+  assign _T_319 = _T_80 ? 1'h1 : _T_318; // @[Lookup.scala 11:37:@1174.4]
+  assign _T_320 = _T_76 ? 1'h0 : _T_319; // @[Lookup.scala 11:37:@1175.4]
+  assign _T_321 = _T_72 ? 1'h0 : _T_320; // @[Lookup.scala 11:37:@1176.4]
+  assign _T_322 = _T_68 ? 1'h0 : _T_321; // @[Lookup.scala 11:37:@1177.4]
+  assign _T_323 = _T_64 ? 1'h0 : _T_322; // @[Lookup.scala 11:37:@1178.4]
+  assign _T_324 = _T_60 ? 1'h0 : _T_323; // @[Lookup.scala 11:37:@1179.4]
+  assign _T_325 = _T_56 ? 1'h0 : _T_324; // @[Lookup.scala 11:37:@1180.4]
+  assign _T_326 = _T_52 ? 1'h1 : _T_325; // @[Lookup.scala 11:37:@1181.4]
+  assign _T_327 = _T_48 ? 1'h0 : _T_326; // @[Lookup.scala 11:37:@1182.4]
+  assign _T_328 = _T_44 ? 1'h0 : _T_327; // @[Lookup.scala 11:37:@1183.4]
+  assign _T_342 = _T_180 ? 1'h1 : _T_184; // @[Lookup.scala 11:37:@1198.4]
+  assign _T_343 = _T_176 ? 1'h1 : _T_342; // @[Lookup.scala 11:37:@1199.4]
+  assign _T_344 = _T_172 ? 1'h1 : _T_343; // @[Lookup.scala 11:37:@1200.4]
+  assign _T_345 = _T_168 ? 1'h1 : _T_344; // @[Lookup.scala 11:37:@1201.4]
+  assign _T_346 = _T_164 ? 1'h1 : _T_345; // @[Lookup.scala 11:37:@1202.4]
+  assign _T_347 = _T_160 ? 1'h1 : _T_346; // @[Lookup.scala 11:37:@1203.4]
+  assign _T_348 = _T_156 ? 1'h1 : _T_347; // @[Lookup.scala 11:37:@1204.4]
+  assign _T_349 = _T_152 ? 1'h1 : _T_348; // @[Lookup.scala 11:37:@1205.4]
+  assign _T_350 = _T_148 ? 1'h1 : _T_349; // @[Lookup.scala 11:37:@1206.4]
+  assign _T_351 = _T_144 ? 1'h0 : _T_350; // @[Lookup.scala 11:37:@1207.4]
+  assign _T_352 = _T_140 ? 1'h0 : _T_351; // @[Lookup.scala 11:37:@1208.4]
+  assign _T_353 = _T_136 ? 1'h0 : _T_352; // @[Lookup.scala 11:37:@1209.4]
+  assign _T_354 = _T_132 ? 1'h0 : _T_353; // @[Lookup.scala 11:37:@1210.4]
+  assign _T_355 = _T_128 ? 1'h0 : _T_354; // @[Lookup.scala 11:37:@1211.4]
+  assign _T_356 = _T_124 ? 1'h0 : _T_355; // @[Lookup.scala 11:37:@1212.4]
+  assign _T_357 = _T_120 ? 1'h0 : _T_356; // @[Lookup.scala 11:37:@1213.4]
+  assign _T_358 = _T_116 ? 1'h0 : _T_357; // @[Lookup.scala 11:37:@1214.4]
+  assign _T_359 = _T_112 ? 1'h0 : _T_358; // @[Lookup.scala 11:37:@1215.4]
+  assign _T_360 = _T_108 ? 1'h0 : _T_359; // @[Lookup.scala 11:37:@1216.4]
+  assign _T_361 = _T_104 ? 1'h0 : _T_360; // @[Lookup.scala 11:37:@1217.4]
+  assign _T_362 = _T_100 ? 1'h0 : _T_361; // @[Lookup.scala 11:37:@1218.4]
+  assign _T_363 = _T_96 ? 1'h0 : _T_362; // @[Lookup.scala 11:37:@1219.4]
+  assign _T_364 = _T_92 ? 1'h0 : _T_363; // @[Lookup.scala 11:37:@1220.4]
+  assign _T_365 = _T_88 ? 1'h0 : _T_364; // @[Lookup.scala 11:37:@1221.4]
+  assign _T_366 = _T_84 ? 1'h0 : _T_365; // @[Lookup.scala 11:37:@1222.4]
+  assign _T_367 = _T_80 ? 1'h0 : _T_366; // @[Lookup.scala 11:37:@1223.4]
+  assign _T_368 = _T_76 ? 1'h0 : _T_367; // @[Lookup.scala 11:37:@1224.4]
+  assign _T_369 = _T_72 ? 1'h0 : _T_368; // @[Lookup.scala 11:37:@1225.4]
+  assign _T_370 = _T_68 ? 1'h0 : _T_369; // @[Lookup.scala 11:37:@1226.4]
+  assign _T_371 = _T_64 ? 1'h0 : _T_370; // @[Lookup.scala 11:37:@1227.4]
+  assign _T_372 = _T_60 ? 1'h0 : _T_371; // @[Lookup.scala 11:37:@1228.4]
+  assign _T_373 = _T_56 ? 1'h0 : _T_372; // @[Lookup.scala 11:37:@1229.4]
+  assign _T_374 = _T_52 ? 1'h0 : _T_373; // @[Lookup.scala 11:37:@1230.4]
+  assign _T_375 = _T_48 ? 1'h0 : _T_374; // @[Lookup.scala 11:37:@1231.4]
+  assign _T_376 = _T_44 ? 1'h0 : _T_375; // @[Lookup.scala 11:37:@1232.4]
+  assign _T_381 = _T_216 ? 3'h6 : 3'h0; // @[Lookup.scala 11:37:@1238.4]
+  assign _T_382 = _T_212 ? 3'h6 : _T_381; // @[Lookup.scala 11:37:@1239.4]
+  assign _T_383 = _T_208 ? 3'h6 : _T_382; // @[Lookup.scala 11:37:@1240.4]
+  assign _T_384 = _T_204 ? 3'h0 : _T_383; // @[Lookup.scala 11:37:@1241.4]
+  assign _T_385 = _T_200 ? 3'h0 : _T_384; // @[Lookup.scala 11:37:@1242.4]
+  assign _T_386 = _T_196 ? 3'h0 : _T_385; // @[Lookup.scala 11:37:@1243.4]
+  assign _T_387 = _T_192 ? 3'h0 : _T_386; // @[Lookup.scala 11:37:@1244.4]
+  assign _T_388 = _T_188 ? 3'h0 : _T_387; // @[Lookup.scala 11:37:@1245.4]
+  assign _T_389 = _T_184 ? 3'h0 : _T_388; // @[Lookup.scala 11:37:@1246.4]
+  assign _T_390 = _T_180 ? 3'h0 : _T_389; // @[Lookup.scala 11:37:@1247.4]
+  assign _T_391 = _T_176 ? 3'h0 : _T_390; // @[Lookup.scala 11:37:@1248.4]
+  assign _T_392 = _T_172 ? 3'h0 : _T_391; // @[Lookup.scala 11:37:@1249.4]
+  assign _T_393 = _T_168 ? 3'h0 : _T_392; // @[Lookup.scala 11:37:@1250.4]
+  assign _T_394 = _T_164 ? 3'h0 : _T_393; // @[Lookup.scala 11:37:@1251.4]
+  assign _T_395 = _T_160 ? 3'h0 : _T_394; // @[Lookup.scala 11:37:@1252.4]
+  assign _T_396 = _T_156 ? 3'h0 : _T_395; // @[Lookup.scala 11:37:@1253.4]
+  assign _T_397 = _T_152 ? 3'h0 : _T_396; // @[Lookup.scala 11:37:@1254.4]
+  assign _T_398 = _T_148 ? 3'h0 : _T_397; // @[Lookup.scala 11:37:@1255.4]
+  assign _T_399 = _T_144 ? 3'h1 : _T_398; // @[Lookup.scala 11:37:@1256.4]
+  assign _T_400 = _T_140 ? 3'h1 : _T_399; // @[Lookup.scala 11:37:@1257.4]
+  assign _T_401 = _T_136 ? 3'h1 : _T_400; // @[Lookup.scala 11:37:@1258.4]
+  assign _T_402 = _T_132 ? 3'h1 : _T_401; // @[Lookup.scala 11:37:@1259.4]
+  assign _T_403 = _T_128 ? 3'h1 : _T_402; // @[Lookup.scala 11:37:@1260.4]
+  assign _T_404 = _T_124 ? 3'h1 : _T_403; // @[Lookup.scala 11:37:@1261.4]
+  assign _T_405 = _T_120 ? 3'h1 : _T_404; // @[Lookup.scala 11:37:@1262.4]
+  assign _T_406 = _T_116 ? 3'h1 : _T_405; // @[Lookup.scala 11:37:@1263.4]
+  assign _T_407 = _T_112 ? 3'h1 : _T_406; // @[Lookup.scala 11:37:@1264.4]
+  assign _T_408 = _T_108 ? 3'h2 : _T_407; // @[Lookup.scala 11:37:@1265.4]
+  assign _T_409 = _T_104 ? 3'h2 : _T_408; // @[Lookup.scala 11:37:@1266.4]
+  assign _T_410 = _T_100 ? 3'h2 : _T_409; // @[Lookup.scala 11:37:@1267.4]
+  assign _T_411 = _T_96 ? 3'h1 : _T_410; // @[Lookup.scala 11:37:@1268.4]
+  assign _T_412 = _T_92 ? 3'h1 : _T_411; // @[Lookup.scala 11:37:@1269.4]
+  assign _T_413 = _T_88 ? 3'h1 : _T_412; // @[Lookup.scala 11:37:@1270.4]
+  assign _T_414 = _T_84 ? 3'h1 : _T_413; // @[Lookup.scala 11:37:@1271.4]
+  assign _T_415 = _T_80 ? 3'h1 : _T_414; // @[Lookup.scala 11:37:@1272.4]
+  assign _T_416 = _T_76 ? 3'h5 : _T_415; // @[Lookup.scala 11:37:@1273.4]
+  assign _T_417 = _T_72 ? 3'h5 : _T_416; // @[Lookup.scala 11:37:@1274.4]
+  assign _T_418 = _T_68 ? 3'h5 : _T_417; // @[Lookup.scala 11:37:@1275.4]
+  assign _T_419 = _T_64 ? 3'h5 : _T_418; // @[Lookup.scala 11:37:@1276.4]
+  assign _T_420 = _T_60 ? 3'h5 : _T_419; // @[Lookup.scala 11:37:@1277.4]
+  assign _T_421 = _T_56 ? 3'h5 : _T_420; // @[Lookup.scala 11:37:@1278.4]
+  assign _T_422 = _T_52 ? 3'h1 : _T_421; // @[Lookup.scala 11:37:@1279.4]
+  assign _T_423 = _T_48 ? 3'h4 : _T_422; // @[Lookup.scala 11:37:@1280.4]
+  assign _T_424 = _T_44 ? 3'h3 : _T_423; // @[Lookup.scala 11:37:@1281.4]
+  assign _T_432 = _T_204 ? 4'ha : 4'hf; // @[Lookup.scala 11:37:@1290.4]
+  assign _T_433 = _T_200 ? 4'ha : _T_432; // @[Lookup.scala 11:37:@1291.4]
+  assign _T_434 = _T_196 ? 4'ha : _T_433; // @[Lookup.scala 11:37:@1292.4]
+  assign _T_435 = _T_192 ? 4'hf : _T_434; // @[Lookup.scala 11:37:@1293.4]
+  assign _T_436 = _T_188 ? 4'hf : _T_435; // @[Lookup.scala 11:37:@1294.4]
+  assign _T_437 = _T_184 ? 4'h2 : _T_436; // @[Lookup.scala 11:37:@1295.4]
+  assign _T_438 = _T_180 ? 4'h3 : _T_437; // @[Lookup.scala 11:37:@1296.4]
+  assign _T_439 = _T_176 ? 4'h9 : _T_438; // @[Lookup.scala 11:37:@1297.4]
+  assign _T_440 = _T_172 ? 4'h8 : _T_439; // @[Lookup.scala 11:37:@1298.4]
+  assign _T_441 = _T_168 ? 4'h4 : _T_440; // @[Lookup.scala 11:37:@1299.4]
+  assign _T_442 = _T_164 ? 4'h7 : _T_441; // @[Lookup.scala 11:37:@1300.4]
+  assign _T_443 = _T_160 ? 4'h5 : _T_442; // @[Lookup.scala 11:37:@1301.4]
+  assign _T_444 = _T_156 ? 4'h6 : _T_443; // @[Lookup.scala 11:37:@1302.4]
+  assign _T_445 = _T_152 ? 4'h1 : _T_444; // @[Lookup.scala 11:37:@1303.4]
+  assign _T_446 = _T_148 ? 4'h0 : _T_445; // @[Lookup.scala 11:37:@1304.4]
+  assign _T_447 = _T_144 ? 4'h9 : _T_446; // @[Lookup.scala 11:37:@1305.4]
+  assign _T_448 = _T_140 ? 4'h8 : _T_447; // @[Lookup.scala 11:37:@1306.4]
+  assign _T_449 = _T_136 ? 4'h6 : _T_448; // @[Lookup.scala 11:37:@1307.4]
+  assign _T_450 = _T_132 ? 4'h2 : _T_449; // @[Lookup.scala 11:37:@1308.4]
+  assign _T_451 = _T_128 ? 4'h3 : _T_450; // @[Lookup.scala 11:37:@1309.4]
+  assign _T_452 = _T_124 ? 4'h4 : _T_451; // @[Lookup.scala 11:37:@1310.4]
+  assign _T_453 = _T_120 ? 4'h7 : _T_452; // @[Lookup.scala 11:37:@1311.4]
+  assign _T_454 = _T_116 ? 4'h5 : _T_453; // @[Lookup.scala 11:37:@1312.4]
+  assign _T_455 = _T_112 ? 4'h0 : _T_454; // @[Lookup.scala 11:37:@1313.4]
+  assign _T_456 = _T_108 ? 4'h0 : _T_455; // @[Lookup.scala 11:37:@1314.4]
+  assign _T_457 = _T_104 ? 4'h0 : _T_456; // @[Lookup.scala 11:37:@1315.4]
+  assign _T_458 = _T_100 ? 4'h0 : _T_457; // @[Lookup.scala 11:37:@1316.4]
+  assign _T_459 = _T_96 ? 4'h0 : _T_458; // @[Lookup.scala 11:37:@1317.4]
+  assign _T_460 = _T_92 ? 4'h0 : _T_459; // @[Lookup.scala 11:37:@1318.4]
+  assign _T_461 = _T_88 ? 4'h0 : _T_460; // @[Lookup.scala 11:37:@1319.4]
+  assign _T_462 = _T_84 ? 4'h0 : _T_461; // @[Lookup.scala 11:37:@1320.4]
+  assign _T_463 = _T_80 ? 4'h0 : _T_462; // @[Lookup.scala 11:37:@1321.4]
+  assign _T_464 = _T_76 ? 4'h0 : _T_463; // @[Lookup.scala 11:37:@1322.4]
+  assign _T_465 = _T_72 ? 4'h0 : _T_464; // @[Lookup.scala 11:37:@1323.4]
+  assign _T_466 = _T_68 ? 4'h0 : _T_465; // @[Lookup.scala 11:37:@1324.4]
+  assign _T_467 = _T_64 ? 4'h0 : _T_466; // @[Lookup.scala 11:37:@1325.4]
+  assign _T_468 = _T_60 ? 4'h0 : _T_467; // @[Lookup.scala 11:37:@1326.4]
+  assign _T_469 = _T_56 ? 4'h0 : _T_468; // @[Lookup.scala 11:37:@1327.4]
+  assign _T_470 = _T_52 ? 4'h0 : _T_469; // @[Lookup.scala 11:37:@1328.4]
+  assign _T_471 = _T_48 ? 4'h0 : _T_470; // @[Lookup.scala 11:37:@1329.4]
+  assign _T_472 = _T_44 ? 4'h0 : _T_471; // @[Lookup.scala 11:37:@1330.4]
+  assign ctrlSignals_4 = _T_40 ? 4'hb : _T_472; // @[Lookup.scala 11:37:@1331.4]
+  assign _T_512 = _T_76 ? 3'h4 : 3'h0; // @[Lookup.scala 11:37:@1371.4]
+  assign _T_513 = _T_72 ? 3'h1 : _T_512; // @[Lookup.scala 11:37:@1372.4]
+  assign _T_514 = _T_68 ? 3'h5 : _T_513; // @[Lookup.scala 11:37:@1373.4]
+  assign _T_515 = _T_64 ? 3'h2 : _T_514; // @[Lookup.scala 11:37:@1374.4]
+  assign _T_516 = _T_60 ? 3'h6 : _T_515; // @[Lookup.scala 11:37:@1375.4]
+  assign _T_517 = _T_56 ? 3'h3 : _T_516; // @[Lookup.scala 11:37:@1376.4]
+  assign _T_518 = _T_52 ? 3'h0 : _T_517; // @[Lookup.scala 11:37:@1377.4]
+  assign _T_519 = _T_48 ? 3'h0 : _T_518; // @[Lookup.scala 11:37:@1378.4]
+  assign _T_520 = _T_44 ? 3'h0 : _T_519; // @[Lookup.scala 11:37:@1379.4]
+  assign _T_523 = _T_224 ? 1'h0 : _T_228; // @[Lookup.scala 11:37:@1383.4]
+  assign _T_524 = _T_220 ? 1'h0 : _T_523; // @[Lookup.scala 11:37:@1384.4]
+  assign _T_525 = _T_216 ? 1'h0 : _T_524; // @[Lookup.scala 11:37:@1385.4]
+  assign _T_526 = _T_212 ? 1'h0 : _T_525; // @[Lookup.scala 11:37:@1386.4]
+  assign _T_527 = _T_208 ? 1'h0 : _T_526; // @[Lookup.scala 11:37:@1387.4]
+  assign _T_528 = _T_204 ? 1'h0 : _T_527; // @[Lookup.scala 11:37:@1388.4]
+  assign _T_529 = _T_200 ? 1'h0 : _T_528; // @[Lookup.scala 11:37:@1389.4]
+  assign _T_530 = _T_196 ? 1'h0 : _T_529; // @[Lookup.scala 11:37:@1390.4]
+  assign _T_531 = _T_192 ? 1'h1 : _T_530; // @[Lookup.scala 11:37:@1391.4]
+  assign _T_532 = _T_188 ? 1'h0 : _T_531; // @[Lookup.scala 11:37:@1392.4]
+  assign _T_533 = _T_184 ? 1'h0 : _T_532; // @[Lookup.scala 11:37:@1393.4]
+  assign _T_534 = _T_180 ? 1'h0 : _T_533; // @[Lookup.scala 11:37:@1394.4]
+  assign _T_535 = _T_176 ? 1'h0 : _T_534; // @[Lookup.scala 11:37:@1395.4]
+  assign _T_536 = _T_172 ? 1'h0 : _T_535; // @[Lookup.scala 11:37:@1396.4]
+  assign _T_537 = _T_168 ? 1'h0 : _T_536; // @[Lookup.scala 11:37:@1397.4]
+  assign _T_538 = _T_164 ? 1'h0 : _T_537; // @[Lookup.scala 11:37:@1398.4]
+  assign _T_539 = _T_160 ? 1'h0 : _T_538; // @[Lookup.scala 11:37:@1399.4]
+  assign _T_540 = _T_156 ? 1'h0 : _T_539; // @[Lookup.scala 11:37:@1400.4]
+  assign _T_541 = _T_152 ? 1'h0 : _T_540; // @[Lookup.scala 11:37:@1401.4]
+  assign _T_542 = _T_148 ? 1'h0 : _T_541; // @[Lookup.scala 11:37:@1402.4]
+  assign _T_543 = _T_144 ? 1'h0 : _T_542; // @[Lookup.scala 11:37:@1403.4]
+  assign _T_544 = _T_140 ? 1'h0 : _T_543; // @[Lookup.scala 11:37:@1404.4]
+  assign _T_545 = _T_136 ? 1'h0 : _T_544; // @[Lookup.scala 11:37:@1405.4]
+  assign _T_546 = _T_132 ? 1'h0 : _T_545; // @[Lookup.scala 11:37:@1406.4]
+  assign _T_547 = _T_128 ? 1'h0 : _T_546; // @[Lookup.scala 11:37:@1407.4]
+  assign _T_548 = _T_124 ? 1'h0 : _T_547; // @[Lookup.scala 11:37:@1408.4]
+  assign _T_549 = _T_120 ? 1'h0 : _T_548; // @[Lookup.scala 11:37:@1409.4]
+  assign _T_550 = _T_116 ? 1'h0 : _T_549; // @[Lookup.scala 11:37:@1410.4]
+  assign _T_551 = _T_112 ? 1'h0 : _T_550; // @[Lookup.scala 11:37:@1411.4]
+  assign _T_552 = _T_108 ? 1'h0 : _T_551; // @[Lookup.scala 11:37:@1412.4]
+  assign _T_553 = _T_104 ? 1'h0 : _T_552; // @[Lookup.scala 11:37:@1413.4]
+  assign _T_554 = _T_100 ? 1'h0 : _T_553; // @[Lookup.scala 11:37:@1414.4]
+  assign _T_555 = _T_96 ? 1'h0 : _T_554; // @[Lookup.scala 11:37:@1415.4]
+  assign _T_556 = _T_92 ? 1'h0 : _T_555; // @[Lookup.scala 11:37:@1416.4]
+  assign _T_557 = _T_88 ? 1'h0 : _T_556; // @[Lookup.scala 11:37:@1417.4]
+  assign _T_558 = _T_84 ? 1'h0 : _T_557; // @[Lookup.scala 11:37:@1418.4]
+  assign _T_559 = _T_80 ? 1'h0 : _T_558; // @[Lookup.scala 11:37:@1419.4]
+  assign _T_560 = _T_76 ? 1'h0 : _T_559; // @[Lookup.scala 11:37:@1420.4]
+  assign _T_561 = _T_72 ? 1'h0 : _T_560; // @[Lookup.scala 11:37:@1421.4]
+  assign _T_562 = _T_68 ? 1'h0 : _T_561; // @[Lookup.scala 11:37:@1422.4]
+  assign _T_563 = _T_64 ? 1'h0 : _T_562; // @[Lookup.scala 11:37:@1423.4]
+  assign _T_564 = _T_60 ? 1'h0 : _T_563; // @[Lookup.scala 11:37:@1424.4]
+  assign _T_565 = _T_56 ? 1'h0 : _T_564; // @[Lookup.scala 11:37:@1425.4]
+  assign _T_566 = _T_52 ? 1'h1 : _T_565; // @[Lookup.scala 11:37:@1426.4]
+  assign _T_567 = _T_48 ? 1'h1 : _T_566; // @[Lookup.scala 11:37:@1427.4]
+  assign _T_568 = _T_44 ? 1'h0 : _T_567; // @[Lookup.scala 11:37:@1428.4]
+  assign _T_600 = _T_108 ? 2'h1 : 2'h0; // @[Lookup.scala 11:37:@1461.4]
+  assign _T_601 = _T_104 ? 2'h2 : _T_600; // @[Lookup.scala 11:37:@1462.4]
+  assign _T_602 = _T_100 ? 2'h3 : _T_601; // @[Lookup.scala 11:37:@1463.4]
+  assign _T_603 = _T_96 ? 2'h0 : _T_602; // @[Lookup.scala 11:37:@1464.4]
+  assign _T_604 = _T_92 ? 2'h0 : _T_603; // @[Lookup.scala 11:37:@1465.4]
+  assign _T_605 = _T_88 ? 2'h0 : _T_604; // @[Lookup.scala 11:37:@1466.4]
+  assign _T_606 = _T_84 ? 2'h0 : _T_605; // @[Lookup.scala 11:37:@1467.4]
+  assign _T_607 = _T_80 ? 2'h0 : _T_606; // @[Lookup.scala 11:37:@1468.4]
+  assign _T_608 = _T_76 ? 2'h0 : _T_607; // @[Lookup.scala 11:37:@1469.4]
+  assign _T_609 = _T_72 ? 2'h0 : _T_608; // @[Lookup.scala 11:37:@1470.4]
+  assign _T_610 = _T_68 ? 2'h0 : _T_609; // @[Lookup.scala 11:37:@1471.4]
+  assign _T_611 = _T_64 ? 2'h0 : _T_610; // @[Lookup.scala 11:37:@1472.4]
+  assign _T_612 = _T_60 ? 2'h0 : _T_611; // @[Lookup.scala 11:37:@1473.4]
+  assign _T_613 = _T_56 ? 2'h0 : _T_612; // @[Lookup.scala 11:37:@1474.4]
+  assign _T_614 = _T_52 ? 2'h0 : _T_613; // @[Lookup.scala 11:37:@1475.4]
+  assign _T_615 = _T_48 ? 2'h0 : _T_614; // @[Lookup.scala 11:37:@1476.4]
+  assign _T_616 = _T_44 ? 2'h0 : _T_615; // @[Lookup.scala 11:37:@1477.4]
+  assign _T_651 = _T_96 ? 3'h4 : 3'h0; // @[Lookup.scala 11:37:@1513.4]
+  assign _T_652 = _T_92 ? 3'h5 : _T_651; // @[Lookup.scala 11:37:@1514.4]
+  assign _T_653 = _T_88 ? 3'h1 : _T_652; // @[Lookup.scala 11:37:@1515.4]
+  assign _T_654 = _T_84 ? 3'h2 : _T_653; // @[Lookup.scala 11:37:@1516.4]
+  assign _T_655 = _T_80 ? 3'h3 : _T_654; // @[Lookup.scala 11:37:@1517.4]
+  assign _T_656 = _T_76 ? 3'h0 : _T_655; // @[Lookup.scala 11:37:@1518.4]
+  assign _T_657 = _T_72 ? 3'h0 : _T_656; // @[Lookup.scala 11:37:@1519.4]
+  assign _T_658 = _T_68 ? 3'h0 : _T_657; // @[Lookup.scala 11:37:@1520.4]
+  assign _T_659 = _T_64 ? 3'h0 : _T_658; // @[Lookup.scala 11:37:@1521.4]
+  assign _T_660 = _T_60 ? 3'h0 : _T_659; // @[Lookup.scala 11:37:@1522.4]
+  assign _T_661 = _T_56 ? 3'h0 : _T_660; // @[Lookup.scala 11:37:@1523.4]
+  assign _T_662 = _T_52 ? 3'h0 : _T_661; // @[Lookup.scala 11:37:@1524.4]
+  assign _T_663 = _T_48 ? 3'h0 : _T_662; // @[Lookup.scala 11:37:@1525.4]
+  assign _T_664 = _T_44 ? 3'h0 : _T_663; // @[Lookup.scala 11:37:@1526.4]
+  assign _T_667 = _T_224 ? 2'h3 : _T_234; // @[Lookup.scala 11:37:@1530.4]
+  assign _T_668 = _T_220 ? 2'h3 : _T_667; // @[Lookup.scala 11:37:@1531.4]
+  assign _T_669 = _T_216 ? 2'h3 : _T_668; // @[Lookup.scala 11:37:@1532.4]
+  assign _T_670 = _T_212 ? 2'h3 : _T_669; // @[Lookup.scala 11:37:@1533.4]
+  assign _T_671 = _T_208 ? 2'h3 : _T_670; // @[Lookup.scala 11:37:@1534.4]
+  assign _T_672 = _T_204 ? 2'h3 : _T_671; // @[Lookup.scala 11:37:@1535.4]
+  assign _T_673 = _T_200 ? 2'h3 : _T_672; // @[Lookup.scala 11:37:@1536.4]
+  assign _T_674 = _T_196 ? 2'h3 : _T_673; // @[Lookup.scala 11:37:@1537.4]
+  assign _T_675 = _T_192 ? 2'h0 : _T_674; // @[Lookup.scala 11:37:@1538.4]
+  assign _T_676 = _T_188 ? 2'h0 : _T_675; // @[Lookup.scala 11:37:@1539.4]
+  assign _T_677 = _T_184 ? 2'h0 : _T_676; // @[Lookup.scala 11:37:@1540.4]
+  assign _T_678 = _T_180 ? 2'h0 : _T_677; // @[Lookup.scala 11:37:@1541.4]
+  assign _T_679 = _T_176 ? 2'h0 : _T_678; // @[Lookup.scala 11:37:@1542.4]
+  assign _T_680 = _T_172 ? 2'h0 : _T_679; // @[Lookup.scala 11:37:@1543.4]
+  assign _T_681 = _T_168 ? 2'h0 : _T_680; // @[Lookup.scala 11:37:@1544.4]
+  assign _T_682 = _T_164 ? 2'h0 : _T_681; // @[Lookup.scala 11:37:@1545.4]
+  assign _T_683 = _T_160 ? 2'h0 : _T_682; // @[Lookup.scala 11:37:@1546.4]
+  assign _T_684 = _T_156 ? 2'h0 : _T_683; // @[Lookup.scala 11:37:@1547.4]
+  assign _T_685 = _T_152 ? 2'h0 : _T_684; // @[Lookup.scala 11:37:@1548.4]
+  assign _T_686 = _T_148 ? 2'h0 : _T_685; // @[Lookup.scala 11:37:@1549.4]
+  assign _T_687 = _T_144 ? 2'h0 : _T_686; // @[Lookup.scala 11:37:@1550.4]
+  assign _T_688 = _T_140 ? 2'h0 : _T_687; // @[Lookup.scala 11:37:@1551.4]
+  assign _T_689 = _T_136 ? 2'h0 : _T_688; // @[Lookup.scala 11:37:@1552.4]
+  assign _T_690 = _T_132 ? 2'h0 : _T_689; // @[Lookup.scala 11:37:@1553.4]
+  assign _T_691 = _T_128 ? 2'h0 : _T_690; // @[Lookup.scala 11:37:@1554.4]
+  assign _T_692 = _T_124 ? 2'h0 : _T_691; // @[Lookup.scala 11:37:@1555.4]
+  assign _T_693 = _T_120 ? 2'h0 : _T_692; // @[Lookup.scala 11:37:@1556.4]
+  assign _T_694 = _T_116 ? 2'h0 : _T_693; // @[Lookup.scala 11:37:@1557.4]
+  assign _T_695 = _T_112 ? 2'h0 : _T_694; // @[Lookup.scala 11:37:@1558.4]
+  assign _T_696 = _T_108 ? 2'h0 : _T_695; // @[Lookup.scala 11:37:@1559.4]
+  assign _T_697 = _T_104 ? 2'h0 : _T_696; // @[Lookup.scala 11:37:@1560.4]
+  assign _T_698 = _T_100 ? 2'h0 : _T_697; // @[Lookup.scala 11:37:@1561.4]
+  assign _T_699 = _T_96 ? 2'h1 : _T_698; // @[Lookup.scala 11:37:@1562.4]
+  assign _T_700 = _T_92 ? 2'h1 : _T_699; // @[Lookup.scala 11:37:@1563.4]
+  assign _T_701 = _T_88 ? 2'h1 : _T_700; // @[Lookup.scala 11:37:@1564.4]
+  assign _T_702 = _T_84 ? 2'h1 : _T_701; // @[Lookup.scala 11:37:@1565.4]
+  assign _T_703 = _T_80 ? 2'h1 : _T_702; // @[Lookup.scala 11:37:@1566.4]
+  assign _T_704 = _T_76 ? 2'h0 : _T_703; // @[Lookup.scala 11:37:@1567.4]
+  assign _T_705 = _T_72 ? 2'h0 : _T_704; // @[Lookup.scala 11:37:@1568.4]
+  assign _T_706 = _T_68 ? 2'h0 : _T_705; // @[Lookup.scala 11:37:@1569.4]
+  assign _T_707 = _T_64 ? 2'h0 : _T_706; // @[Lookup.scala 11:37:@1570.4]
+  assign _T_708 = _T_60 ? 2'h0 : _T_707; // @[Lookup.scala 11:37:@1571.4]
+  assign _T_709 = _T_56 ? 2'h0 : _T_708; // @[Lookup.scala 11:37:@1572.4]
+  assign _T_710 = _T_52 ? 2'h2 : _T_709; // @[Lookup.scala 11:37:@1573.4]
+  assign _T_711 = _T_48 ? 2'h2 : _T_710; // @[Lookup.scala 11:37:@1574.4]
+  assign _T_712 = _T_44 ? 2'h0 : _T_711; // @[Lookup.scala 11:37:@1575.4]
+  assign _T_718 = _T_212 ? 1'h1 : _T_216; // @[Lookup.scala 11:37:@1582.4]
+  assign _T_719 = _T_208 ? 1'h1 : _T_718; // @[Lookup.scala 11:37:@1583.4]
+  assign _T_720 = _T_204 ? 1'h1 : _T_719; // @[Lookup.scala 11:37:@1584.4]
+  assign _T_721 = _T_200 ? 1'h1 : _T_720; // @[Lookup.scala 11:37:@1585.4]
+  assign _T_722 = _T_196 ? 1'h1 : _T_721; // @[Lookup.scala 11:37:@1586.4]
+  assign _T_723 = _T_192 ? 1'h0 : _T_722; // @[Lookup.scala 11:37:@1587.4]
+  assign _T_724 = _T_188 ? 1'h0 : _T_723; // @[Lookup.scala 11:37:@1588.4]
+  assign _T_725 = _T_184 ? 1'h1 : _T_724; // @[Lookup.scala 11:37:@1589.4]
+  assign _T_726 = _T_180 ? 1'h1 : _T_725; // @[Lookup.scala 11:37:@1590.4]
+  assign _T_727 = _T_176 ? 1'h1 : _T_726; // @[Lookup.scala 11:37:@1591.4]
+  assign _T_728 = _T_172 ? 1'h1 : _T_727; // @[Lookup.scala 11:37:@1592.4]
+  assign _T_729 = _T_168 ? 1'h1 : _T_728; // @[Lookup.scala 11:37:@1593.4]
+  assign _T_730 = _T_164 ? 1'h1 : _T_729; // @[Lookup.scala 11:37:@1594.4]
+  assign _T_731 = _T_160 ? 1'h1 : _T_730; // @[Lookup.scala 11:37:@1595.4]
+  assign _T_732 = _T_156 ? 1'h1 : _T_731; // @[Lookup.scala 11:37:@1596.4]
+  assign _T_733 = _T_152 ? 1'h1 : _T_732; // @[Lookup.scala 11:37:@1597.4]
+  assign _T_734 = _T_148 ? 1'h1 : _T_733; // @[Lookup.scala 11:37:@1598.4]
+  assign _T_735 = _T_144 ? 1'h1 : _T_734; // @[Lookup.scala 11:37:@1599.4]
+  assign _T_736 = _T_140 ? 1'h1 : _T_735; // @[Lookup.scala 11:37:@1600.4]
+  assign _T_737 = _T_136 ? 1'h1 : _T_736; // @[Lookup.scala 11:37:@1601.4]
+  assign _T_738 = _T_132 ? 1'h1 : _T_737; // @[Lookup.scala 11:37:@1602.4]
+  assign _T_739 = _T_128 ? 1'h1 : _T_738; // @[Lookup.scala 11:37:@1603.4]
+  assign _T_740 = _T_124 ? 1'h1 : _T_739; // @[Lookup.scala 11:37:@1604.4]
+  assign _T_741 = _T_120 ? 1'h1 : _T_740; // @[Lookup.scala 11:37:@1605.4]
+  assign _T_742 = _T_116 ? 1'h1 : _T_741; // @[Lookup.scala 11:37:@1606.4]
+  assign _T_743 = _T_112 ? 1'h1 : _T_742; // @[Lookup.scala 11:37:@1607.4]
+  assign _T_744 = _T_108 ? 1'h0 : _T_743; // @[Lookup.scala 11:37:@1608.4]
+  assign _T_745 = _T_104 ? 1'h0 : _T_744; // @[Lookup.scala 11:37:@1609.4]
+  assign _T_746 = _T_100 ? 1'h0 : _T_745; // @[Lookup.scala 11:37:@1610.4]
+  assign _T_747 = _T_96 ? 1'h1 : _T_746; // @[Lookup.scala 11:37:@1611.4]
+  assign _T_748 = _T_92 ? 1'h1 : _T_747; // @[Lookup.scala 11:37:@1612.4]
+  assign _T_749 = _T_88 ? 1'h1 : _T_748; // @[Lookup.scala 11:37:@1613.4]
+  assign _T_750 = _T_84 ? 1'h1 : _T_749; // @[Lookup.scala 11:37:@1614.4]
+  assign _T_751 = _T_80 ? 1'h1 : _T_750; // @[Lookup.scala 11:37:@1615.4]
+  assign _T_752 = _T_76 ? 1'h0 : _T_751; // @[Lookup.scala 11:37:@1616.4]
+  assign _T_753 = _T_72 ? 1'h0 : _T_752; // @[Lookup.scala 11:37:@1617.4]
+  assign _T_754 = _T_68 ? 1'h0 : _T_753; // @[Lookup.scala 11:37:@1618.4]
+  assign _T_755 = _T_64 ? 1'h0 : _T_754; // @[Lookup.scala 11:37:@1619.4]
+  assign _T_756 = _T_60 ? 1'h0 : _T_755; // @[Lookup.scala 11:37:@1620.4]
+  assign _T_757 = _T_56 ? 1'h0 : _T_756; // @[Lookup.scala 11:37:@1621.4]
+  assign _T_758 = _T_52 ? 1'h1 : _T_757; // @[Lookup.scala 11:37:@1622.4]
+  assign _T_759 = _T_48 ? 1'h1 : _T_758; // @[Lookup.scala 11:37:@1623.4]
+  assign _T_760 = _T_44 ? 1'h1 : _T_759; // @[Lookup.scala 11:37:@1624.4]
+  assign _T_762 = _T_228 ? 3'h4 : 3'h0; // @[Lookup.scala 11:37:@1627.4]
+  assign _T_763 = _T_224 ? 3'h4 : _T_762; // @[Lookup.scala 11:37:@1628.4]
+  assign _T_764 = _T_220 ? 3'h4 : _T_763; // @[Lookup.scala 11:37:@1629.4]
+  assign _T_765 = _T_216 ? 3'h3 : _T_764; // @[Lookup.scala 11:37:@1630.4]
+  assign _T_766 = _T_212 ? 3'h2 : _T_765; // @[Lookup.scala 11:37:@1631.4]
+  assign _T_767 = _T_208 ? 3'h1 : _T_766; // @[Lookup.scala 11:37:@1632.4]
+  assign _T_768 = _T_204 ? 3'h3 : _T_767; // @[Lookup.scala 11:37:@1633.4]
+  assign _T_769 = _T_200 ? 3'h2 : _T_768; // @[Lookup.scala 11:37:@1634.4]
+  assign _T_770 = _T_196 ? 3'h1 : _T_769; // @[Lookup.scala 11:37:@1635.4]
+  assign _T_771 = _T_192 ? 3'h0 : _T_770; // @[Lookup.scala 11:37:@1636.4]
+  assign _T_772 = _T_188 ? 3'h0 : _T_771; // @[Lookup.scala 11:37:@1637.4]
+  assign _T_773 = _T_184 ? 3'h0 : _T_772; // @[Lookup.scala 11:37:@1638.4]
+  assign _T_774 = _T_180 ? 3'h0 : _T_773; // @[Lookup.scala 11:37:@1639.4]
+  assign _T_775 = _T_176 ? 3'h0 : _T_774; // @[Lookup.scala 11:37:@1640.4]
+  assign _T_776 = _T_172 ? 3'h0 : _T_775; // @[Lookup.scala 11:37:@1641.4]
+  assign _T_777 = _T_168 ? 3'h0 : _T_776; // @[Lookup.scala 11:37:@1642.4]
+  assign _T_778 = _T_164 ? 3'h0 : _T_777; // @[Lookup.scala 11:37:@1643.4]
+  assign _T_779 = _T_160 ? 3'h0 : _T_778; // @[Lookup.scala 11:37:@1644.4]
+  assign _T_780 = _T_156 ? 3'h0 : _T_779; // @[Lookup.scala 11:37:@1645.4]
+  assign _T_781 = _T_152 ? 3'h0 : _T_780; // @[Lookup.scala 11:37:@1646.4]
+  assign _T_782 = _T_148 ? 3'h0 : _T_781; // @[Lookup.scala 11:37:@1647.4]
+  assign _T_783 = _T_144 ? 3'h0 : _T_782; // @[Lookup.scala 11:37:@1648.4]
+  assign _T_784 = _T_140 ? 3'h0 : _T_783; // @[Lookup.scala 11:37:@1649.4]
+  assign _T_785 = _T_136 ? 3'h0 : _T_784; // @[Lookup.scala 11:37:@1650.4]
+  assign _T_786 = _T_132 ? 3'h0 : _T_785; // @[Lookup.scala 11:37:@1651.4]
+  assign _T_787 = _T_128 ? 3'h0 : _T_786; // @[Lookup.scala 11:37:@1652.4]
+  assign _T_788 = _T_124 ? 3'h0 : _T_787; // @[Lookup.scala 11:37:@1653.4]
+  assign _T_789 = _T_120 ? 3'h0 : _T_788; // @[Lookup.scala 11:37:@1654.4]
+  assign _T_790 = _T_116 ? 3'h0 : _T_789; // @[Lookup.scala 11:37:@1655.4]
+  assign _T_791 = _T_112 ? 3'h0 : _T_790; // @[Lookup.scala 11:37:@1656.4]
+  assign _T_792 = _T_108 ? 3'h0 : _T_791; // @[Lookup.scala 11:37:@1657.4]
+  assign _T_793 = _T_104 ? 3'h0 : _T_792; // @[Lookup.scala 11:37:@1658.4]
+  assign _T_794 = _T_100 ? 3'h0 : _T_793; // @[Lookup.scala 11:37:@1659.4]
+  assign _T_795 = _T_96 ? 3'h0 : _T_794; // @[Lookup.scala 11:37:@1660.4]
+  assign _T_796 = _T_92 ? 3'h0 : _T_795; // @[Lookup.scala 11:37:@1661.4]
+  assign _T_797 = _T_88 ? 3'h0 : _T_796; // @[Lookup.scala 11:37:@1662.4]
+  assign _T_798 = _T_84 ? 3'h0 : _T_797; // @[Lookup.scala 11:37:@1663.4]
+  assign _T_799 = _T_80 ? 3'h0 : _T_798; // @[Lookup.scala 11:37:@1664.4]
+  assign _T_800 = _T_76 ? 3'h0 : _T_799; // @[Lookup.scala 11:37:@1665.4]
+  assign _T_801 = _T_72 ? 3'h0 : _T_800; // @[Lookup.scala 11:37:@1666.4]
+  assign _T_802 = _T_68 ? 3'h0 : _T_801; // @[Lookup.scala 11:37:@1667.4]
+  assign _T_803 = _T_64 ? 3'h0 : _T_802; // @[Lookup.scala 11:37:@1668.4]
+  assign _T_804 = _T_60 ? 3'h0 : _T_803; // @[Lookup.scala 11:37:@1669.4]
+  assign _T_805 = _T_56 ? 3'h0 : _T_804; // @[Lookup.scala 11:37:@1670.4]
+  assign _T_806 = _T_52 ? 3'h0 : _T_805; // @[Lookup.scala 11:37:@1671.4]
+  assign _T_807 = _T_48 ? 3'h0 : _T_806; // @[Lookup.scala 11:37:@1672.4]
+  assign _T_808 = _T_44 ? 3'h0 : _T_807; // @[Lookup.scala 11:37:@1673.4]
+  assign _T_809 = _T_232 ? 1'h0 : 1'h1; // @[Lookup.scala 11:37:@1675.4]
+  assign _T_810 = _T_228 ? 1'h0 : _T_809; // @[Lookup.scala 11:37:@1676.4]
+  assign _T_811 = _T_224 ? 1'h0 : _T_810; // @[Lookup.scala 11:37:@1677.4]
+  assign _T_812 = _T_220 ? 1'h0 : _T_811; // @[Lookup.scala 11:37:@1678.4]
+  assign _T_813 = _T_216 ? 1'h0 : _T_812; // @[Lookup.scala 11:37:@1679.4]
+  assign _T_814 = _T_212 ? 1'h0 : _T_813; // @[Lookup.scala 11:37:@1680.4]
+  assign _T_815 = _T_208 ? 1'h0 : _T_814; // @[Lookup.scala 11:37:@1681.4]
+  assign _T_816 = _T_204 ? 1'h0 : _T_815; // @[Lookup.scala 11:37:@1682.4]
+  assign _T_817 = _T_200 ? 1'h0 : _T_816; // @[Lookup.scala 11:37:@1683.4]
+  assign _T_818 = _T_196 ? 1'h0 : _T_817; // @[Lookup.scala 11:37:@1684.4]
+  assign _T_819 = _T_192 ? 1'h0 : _T_818; // @[Lookup.scala 11:37:@1685.4]
+  assign _T_820 = _T_188 ? 1'h0 : _T_819; // @[Lookup.scala 11:37:@1686.4]
+  assign _T_821 = _T_184 ? 1'h0 : _T_820; // @[Lookup.scala 11:37:@1687.4]
+  assign _T_822 = _T_180 ? 1'h0 : _T_821; // @[Lookup.scala 11:37:@1688.4]
+  assign _T_823 = _T_176 ? 1'h0 : _T_822; // @[Lookup.scala 11:37:@1689.4]
+  assign _T_824 = _T_172 ? 1'h0 : _T_823; // @[Lookup.scala 11:37:@1690.4]
+  assign _T_825 = _T_168 ? 1'h0 : _T_824; // @[Lookup.scala 11:37:@1691.4]
+  assign _T_826 = _T_164 ? 1'h0 : _T_825; // @[Lookup.scala 11:37:@1692.4]
+  assign _T_827 = _T_160 ? 1'h0 : _T_826; // @[Lookup.scala 11:37:@1693.4]
+  assign _T_828 = _T_156 ? 1'h0 : _T_827; // @[Lookup.scala 11:37:@1694.4]
+  assign _T_829 = _T_152 ? 1'h0 : _T_828; // @[Lookup.scala 11:37:@1695.4]
+  assign _T_830 = _T_148 ? 1'h0 : _T_829; // @[Lookup.scala 11:37:@1696.4]
+  assign _T_831 = _T_144 ? 1'h0 : _T_830; // @[Lookup.scala 11:37:@1697.4]
+  assign _T_832 = _T_140 ? 1'h0 : _T_831; // @[Lookup.scala 11:37:@1698.4]
+  assign _T_833 = _T_136 ? 1'h0 : _T_832; // @[Lookup.scala 11:37:@1699.4]
+  assign _T_834 = _T_132 ? 1'h0 : _T_833; // @[Lookup.scala 11:37:@1700.4]
+  assign _T_835 = _T_128 ? 1'h0 : _T_834; // @[Lookup.scala 11:37:@1701.4]
+  assign _T_836 = _T_124 ? 1'h0 : _T_835; // @[Lookup.scala 11:37:@1702.4]
+  assign _T_837 = _T_120 ? 1'h0 : _T_836; // @[Lookup.scala 11:37:@1703.4]
+  assign _T_838 = _T_116 ? 1'h0 : _T_837; // @[Lookup.scala 11:37:@1704.4]
+  assign _T_839 = _T_112 ? 1'h0 : _T_838; // @[Lookup.scala 11:37:@1705.4]
+  assign _T_840 = _T_108 ? 1'h0 : _T_839; // @[Lookup.scala 11:37:@1706.4]
+  assign _T_841 = _T_104 ? 1'h0 : _T_840; // @[Lookup.scala 11:37:@1707.4]
+  assign _T_842 = _T_100 ? 1'h0 : _T_841; // @[Lookup.scala 11:37:@1708.4]
+  assign _T_843 = _T_96 ? 1'h0 : _T_842; // @[Lookup.scala 11:37:@1709.4]
+  assign _T_844 = _T_92 ? 1'h0 : _T_843; // @[Lookup.scala 11:37:@1710.4]
+  assign _T_845 = _T_88 ? 1'h0 : _T_844; // @[Lookup.scala 11:37:@1711.4]
+  assign _T_846 = _T_84 ? 1'h0 : _T_845; // @[Lookup.scala 11:37:@1712.4]
+  assign _T_847 = _T_80 ? 1'h0 : _T_846; // @[Lookup.scala 11:37:@1713.4]
+  assign _T_848 = _T_76 ? 1'h0 : _T_847; // @[Lookup.scala 11:37:@1714.4]
+  assign _T_849 = _T_72 ? 1'h0 : _T_848; // @[Lookup.scala 11:37:@1715.4]
+  assign _T_850 = _T_68 ? 1'h0 : _T_849; // @[Lookup.scala 11:37:@1716.4]
+  assign _T_851 = _T_64 ? 1'h0 : _T_850; // @[Lookup.scala 11:37:@1717.4]
+  assign _T_852 = _T_60 ? 1'h0 : _T_851; // @[Lookup.scala 11:37:@1718.4]
+  assign _T_853 = _T_56 ? 1'h0 : _T_852; // @[Lookup.scala 11:37:@1719.4]
+  assign _T_854 = _T_52 ? 1'h0 : _T_853; // @[Lookup.scala 11:37:@1720.4]
+  assign _T_855 = _T_48 ? 1'h0 : _T_854; // @[Lookup.scala 11:37:@1721.4]
+  assign _T_856 = _T_44 ? 1'h0 : _T_855; // @[Lookup.scala 11:37:@1722.4]
+  assign _T_896 = _T_76 ? 1'h1 : _T_319; // @[Lookup.scala 11:37:@1763.4]
+  assign _T_897 = _T_72 ? 1'h1 : _T_896; // @[Lookup.scala 11:37:@1764.4]
+  assign _T_898 = _T_68 ? 1'h1 : _T_897; // @[Lookup.scala 11:37:@1765.4]
+  assign _T_899 = _T_64 ? 1'h1 : _T_898; // @[Lookup.scala 11:37:@1766.4]
+  assign _T_900 = _T_60 ? 1'h1 : _T_899; // @[Lookup.scala 11:37:@1767.4]
+  assign _T_901 = _T_56 ? 1'h1 : _T_900; // @[Lookup.scala 11:37:@1768.4]
+  assign _T_902 = _T_52 ? 1'h1 : _T_901; // @[Lookup.scala 11:37:@1769.4]
+  assign _T_903 = _T_48 ? 1'h0 : _T_902; // @[Lookup.scala 11:37:@1770.4]
+  assign _T_904 = _T_44 ? 1'h0 : _T_903; // @[Lookup.scala 11:37:@1771.4]
+  assign _T_936 = _T_108 ? 1'h1 : _T_359; // @[Lookup.scala 11:37:@1804.4]
+  assign _T_937 = _T_104 ? 1'h1 : _T_936; // @[Lookup.scala 11:37:@1805.4]
+  assign _T_938 = _T_100 ? 1'h1 : _T_937; // @[Lookup.scala 11:37:@1806.4]
+  assign _T_939 = _T_96 ? 1'h0 : _T_938; // @[Lookup.scala 11:37:@1807.4]
+  assign _T_940 = _T_92 ? 1'h0 : _T_939; // @[Lookup.scala 11:37:@1808.4]
+  assign _T_941 = _T_88 ? 1'h0 : _T_940; // @[Lookup.scala 11:37:@1809.4]
+  assign _T_942 = _T_84 ? 1'h0 : _T_941; // @[Lookup.scala 11:37:@1810.4]
+  assign _T_943 = _T_80 ? 1'h0 : _T_942; // @[Lookup.scala 11:37:@1811.4]
+  assign _T_944 = _T_76 ? 1'h1 : _T_943; // @[Lookup.scala 11:37:@1812.4]
+  assign _T_945 = _T_72 ? 1'h1 : _T_944; // @[Lookup.scala 11:37:@1813.4]
+  assign _T_946 = _T_68 ? 1'h1 : _T_945; // @[Lookup.scala 11:37:@1814.4]
+  assign _T_947 = _T_64 ? 1'h1 : _T_946; // @[Lookup.scala 11:37:@1815.4]
+  assign _T_948 = _T_60 ? 1'h1 : _T_947; // @[Lookup.scala 11:37:@1816.4]
+  assign _T_949 = _T_56 ? 1'h1 : _T_948; // @[Lookup.scala 11:37:@1817.4]
+  assign _T_950 = _T_52 ? 1'h0 : _T_949; // @[Lookup.scala 11:37:@1818.4]
+  assign _T_951 = _T_48 ? 1'h0 : _T_950; // @[Lookup.scala 11:37:@1819.4]
+  assign _T_952 = _T_44 ? 1'h0 : _T_951; // @[Lookup.scala 11:37:@1820.4]
+  assign io_pc_sel = _T_40 ? 2'h0 : _T_280; // @[pipeline_control.scala 112:16:@1822.4]
+  assign io_inst_kill = _T_40 ? 1'h0 : _T_568; // @[pipeline_control.scala 113:16:@1824.4]
+  assign io_a_sel = _T_40 ? 1'h0 : _T_328; // @[pipeline_control.scala 116:17:@1825.4]
+  assign io_b_sel = _T_40 ? 1'h0 : _T_376; // @[pipeline_control.scala 117:17:@1826.4]
+  assign io_imm_sel = _T_40 ? 3'h3 : _T_424; // @[pipeline_control.scala 118:17:@1827.4]
+  assign io_alu_op = {{1'd0}, ctrlSignals_4}; // @[pipeline_control.scala 119:17:@1828.4]
+  assign io_br_type = _T_40 ? 3'h0 : _T_520; // @[pipeline_control.scala 120:17:@1829.4]
+  assign io_st_type = _T_40 ? 2'h0 : _T_616; // @[pipeline_control.scala 121:17:@1830.4]
+  assign io_ld_type = _T_40 ? 3'h0 : _T_664; // @[pipeline_control.scala 124:17:@1831.4]
+  assign io_wb_mux_sel = _T_40 ? 2'h0 : _T_712; // @[pipeline_control.scala 125:17:@1832.4]
+  assign io_wb_en = _T_40 ? 1'h1 : _T_760; // @[pipeline_control.scala 126:17:@1834.4]
+  assign io_csr_cmd = _T_40 ? 3'h0 : _T_808; // @[pipeline_control.scala 127:17:@1835.4]
+  assign io_illegal = _T_40 ? 1'h0 : _T_856; // @[pipeline_control.scala 128:17:@1836.4]
+  assign io_en_rs1 = _T_40 ? 1'h0 : _T_904; // @[pipeline_control.scala 129:17:@1837.4]
+  assign io_en_rs2 = _T_40 ? 1'h0 : _T_952; // @[pipeline_control.scala 130:17:@1838.4]
+endmodule
+module Core( // @[:@1840.2]
+  input         clock, // @[:@1841.4]
+  input         reset, // @[:@1842.4]
+  input         io_irq_uart_irq, // @[:@1843.4]
+  input         io_irq_spi_irq, // @[:@1843.4]
+  input         io_irq_motor_irq, // @[:@1843.4]
+  output [31:0] io_ibus_addr, // @[:@1843.4]
+  input  [31:0] io_ibus_inst, // @[:@1843.4]
+  input         io_ibus_valid, // @[:@1843.4]
+  output [31:0] io_dbus_addr, // @[:@1843.4]
+  output [31:0] io_dbus_wdata, // @[:@1843.4]
+  input  [31:0] io_dbus_rdata, // @[:@1843.4]
+  output        io_dbus_rd_en, // @[:@1843.4]
+  output        io_dbus_wr_en, // @[:@1843.4]
+  output [1:0]  io_dbus_st_type, // @[:@1843.4]
+  output [2:0]  io_dbus_ld_type, // @[:@1843.4]
+  input         io_dbus_valid // @[:@1843.4]
+);
+  wire  dpath_clock; // @[core.scala 55:25:@1845.4]
+  wire  dpath_reset; // @[core.scala 55:25:@1845.4]
+  wire  dpath_io_irq_uart_irq; // @[core.scala 55:25:@1845.4]
+  wire  dpath_io_irq_spi_irq; // @[core.scala 55:25:@1845.4]
+  wire  dpath_io_irq_motor_irq; // @[core.scala 55:25:@1845.4]
+  wire [31:0] dpath_io_ibus_addr; // @[core.scala 55:25:@1845.4]
+  wire [31:0] dpath_io_ibus_inst; // @[core.scala 55:25:@1845.4]
+  wire  dpath_io_ibus_valid; // @[core.scala 55:25:@1845.4]
+  wire [31:0] dpath_io_dbus_addr; // @[core.scala 55:25:@1845.4]
+  wire [31:0] dpath_io_dbus_wdata; // @[core.scala 55:25:@1845.4]
+  wire [31:0] dpath_io_dbus_rdata; // @[core.scala 55:25:@1845.4]
+  wire  dpath_io_dbus_rd_en; // @[core.scala 55:25:@1845.4]
+  wire  dpath_io_dbus_wr_en; // @[core.scala 55:25:@1845.4]
+  wire [1:0] dpath_io_dbus_st_type; // @[core.scala 55:25:@1845.4]
+  wire [2:0] dpath_io_dbus_ld_type; // @[core.scala 55:25:@1845.4]
+  wire  dpath_io_dbus_valid; // @[core.scala 55:25:@1845.4]
+  wire [31:0] dpath_io_ctrl_inst; // @[core.scala 55:25:@1845.4]
+  wire [1:0] dpath_io_ctrl_pc_sel; // @[core.scala 55:25:@1845.4]
+  wire  dpath_io_ctrl_inst_kill; // @[core.scala 55:25:@1845.4]
+  wire  dpath_io_ctrl_a_sel; // @[core.scala 55:25:@1845.4]
+  wire  dpath_io_ctrl_b_sel; // @[core.scala 55:25:@1845.4]
+  wire [2:0] dpath_io_ctrl_imm_sel; // @[core.scala 55:25:@1845.4]
+  wire [4:0] dpath_io_ctrl_alu_op; // @[core.scala 55:25:@1845.4]
+  wire [2:0] dpath_io_ctrl_br_type; // @[core.scala 55:25:@1845.4]
+  wire [1:0] dpath_io_ctrl_st_type; // @[core.scala 55:25:@1845.4]
+  wire [2:0] dpath_io_ctrl_ld_type; // @[core.scala 55:25:@1845.4]
+  wire [1:0] dpath_io_ctrl_wb_mux_sel; // @[core.scala 55:25:@1845.4]
+  wire  dpath_io_ctrl_wb_en; // @[core.scala 55:25:@1845.4]
+  wire [2:0] dpath_io_ctrl_csr_cmd; // @[core.scala 55:25:@1845.4]
+  wire  dpath_io_ctrl_illegal; // @[core.scala 55:25:@1845.4]
+  wire  dpath_io_ctrl_en_rs1; // @[core.scala 55:25:@1845.4]
+  wire  dpath_io_ctrl_en_rs2; // @[core.scala 55:25:@1845.4]
+  wire [31:0] ctrl_io_inst; // @[core.scala 56:25:@1848.4]
+  wire [1:0] ctrl_io_pc_sel; // @[core.scala 56:25:@1848.4]
+  wire  ctrl_io_inst_kill; // @[core.scala 56:25:@1848.4]
+  wire  ctrl_io_a_sel; // @[core.scala 56:25:@1848.4]
+  wire  ctrl_io_b_sel; // @[core.scala 56:25:@1848.4]
+  wire [2:0] ctrl_io_imm_sel; // @[core.scala 56:25:@1848.4]
+  wire [4:0] ctrl_io_alu_op; // @[core.scala 56:25:@1848.4]
+  wire [2:0] ctrl_io_br_type; // @[core.scala 56:25:@1848.4]
+  wire [1:0] ctrl_io_st_type; // @[core.scala 56:25:@1848.4]
+  wire [2:0] ctrl_io_ld_type; // @[core.scala 56:25:@1848.4]
+  wire [1:0] ctrl_io_wb_mux_sel; // @[core.scala 56:25:@1848.4]
+  wire  ctrl_io_wb_en; // @[core.scala 56:25:@1848.4]
+  wire [2:0] ctrl_io_csr_cmd; // @[core.scala 56:25:@1848.4]
+  wire  ctrl_io_illegal; // @[core.scala 56:25:@1848.4]
+  wire  ctrl_io_en_rs1; // @[core.scala 56:25:@1848.4]
+  wire  ctrl_io_en_rs2; // @[core.scala 56:25:@1848.4]
+  Datapath dpath ( // @[core.scala 55:25:@1845.4]
+    .clock(dpath_clock),
+    .reset(dpath_reset),
+    .io_irq_uart_irq(dpath_io_irq_uart_irq),
+    .io_irq_spi_irq(dpath_io_irq_spi_irq),
+    .io_irq_motor_irq(dpath_io_irq_motor_irq),
+    .io_ibus_addr(dpath_io_ibus_addr),
+    .io_ibus_inst(dpath_io_ibus_inst),
+    .io_ibus_valid(dpath_io_ibus_valid),
+    .io_dbus_addr(dpath_io_dbus_addr),
+    .io_dbus_wdata(dpath_io_dbus_wdata),
+    .io_dbus_rdata(dpath_io_dbus_rdata),
+    .io_dbus_rd_en(dpath_io_dbus_rd_en),
+    .io_dbus_wr_en(dpath_io_dbus_wr_en),
+    .io_dbus_st_type(dpath_io_dbus_st_type),
+    .io_dbus_ld_type(dpath_io_dbus_ld_type),
+    .io_dbus_valid(dpath_io_dbus_valid),
+    .io_ctrl_inst(dpath_io_ctrl_inst),
+    .io_ctrl_pc_sel(dpath_io_ctrl_pc_sel),
+    .io_ctrl_inst_kill(dpath_io_ctrl_inst_kill),
+    .io_ctrl_a_sel(dpath_io_ctrl_a_sel),
+    .io_ctrl_b_sel(dpath_io_ctrl_b_sel),
+    .io_ctrl_imm_sel(dpath_io_ctrl_imm_sel),
+    .io_ctrl_alu_op(dpath_io_ctrl_alu_op),
+    .io_ctrl_br_type(dpath_io_ctrl_br_type),
+    .io_ctrl_st_type(dpath_io_ctrl_st_type),
+    .io_ctrl_ld_type(dpath_io_ctrl_ld_type),
+    .io_ctrl_wb_mux_sel(dpath_io_ctrl_wb_mux_sel),
+    .io_ctrl_wb_en(dpath_io_ctrl_wb_en),
+    .io_ctrl_csr_cmd(dpath_io_ctrl_csr_cmd),
+    .io_ctrl_illegal(dpath_io_ctrl_illegal),
+    .io_ctrl_en_rs1(dpath_io_ctrl_en_rs1),
+    .io_ctrl_en_rs2(dpath_io_ctrl_en_rs2)
+  );
+  Control ctrl ( // @[core.scala 56:25:@1848.4]
+    .io_inst(ctrl_io_inst),
+    .io_pc_sel(ctrl_io_pc_sel),
+    .io_inst_kill(ctrl_io_inst_kill),
+    .io_a_sel(ctrl_io_a_sel),
+    .io_b_sel(ctrl_io_b_sel),
+    .io_imm_sel(ctrl_io_imm_sel),
+    .io_alu_op(ctrl_io_alu_op),
+    .io_br_type(ctrl_io_br_type),
+    .io_st_type(ctrl_io_st_type),
+    .io_ld_type(ctrl_io_ld_type),
+    .io_wb_mux_sel(ctrl_io_wb_mux_sel),
+    .io_wb_en(ctrl_io_wb_en),
+    .io_csr_cmd(ctrl_io_csr_cmd),
+    .io_illegal(ctrl_io_illegal),
+    .io_en_rs1(ctrl_io_en_rs1),
+    .io_en_rs2(ctrl_io_en_rs2)
+  );
+  assign io_ibus_addr = dpath_io_ibus_addr; // @[core.scala 61:17:@1856.4]
+  assign io_dbus_addr = dpath_io_dbus_addr; // @[core.scala 62:17:@1864.4]
+  assign io_dbus_wdata = dpath_io_dbus_wdata; // @[core.scala 62:17:@1863.4]
+  assign io_dbus_rd_en = dpath_io_dbus_rd_en; // @[core.scala 62:17:@1861.4]
+  assign io_dbus_wr_en = dpath_io_dbus_wr_en; // @[core.scala 62:17:@1860.4]
+  assign io_dbus_st_type = dpath_io_dbus_st_type; // @[core.scala 62:17:@1859.4]
+  assign io_dbus_ld_type = dpath_io_dbus_ld_type; // @[core.scala 62:17:@1858.4]
+  assign dpath_clock = clock; // @[:@1846.4]
+  assign dpath_reset = reset; // @[:@1847.4]
+  assign dpath_io_irq_uart_irq = io_irq_uart_irq; // @[core.scala 60:17:@1853.4]
+  assign dpath_io_irq_spi_irq = io_irq_spi_irq; // @[core.scala 60:17:@1852.4]
+  assign dpath_io_irq_motor_irq = io_irq_motor_irq; // @[core.scala 60:17:@1851.4]
+  assign dpath_io_ibus_inst = io_ibus_inst; // @[core.scala 61:17:@1855.4]
+  assign dpath_io_ibus_valid = io_ibus_valid; // @[core.scala 61:17:@1854.4]
+  assign dpath_io_dbus_rdata = io_dbus_rdata; // @[core.scala 62:17:@1862.4]
+  assign dpath_io_dbus_valid = io_dbus_valid; // @[core.scala 62:17:@1857.4]
+  assign dpath_io_ctrl_pc_sel = ctrl_io_pc_sel; // @[core.scala 63:17:@1879.4]
+  assign dpath_io_ctrl_inst_kill = ctrl_io_inst_kill; // @[core.scala 63:17:@1878.4]
+  assign dpath_io_ctrl_a_sel = ctrl_io_a_sel; // @[core.scala 63:17:@1877.4]
+  assign dpath_io_ctrl_b_sel = ctrl_io_b_sel; // @[core.scala 63:17:@1876.4]
+  assign dpath_io_ctrl_imm_sel = ctrl_io_imm_sel; // @[core.scala 63:17:@1875.4]
+  assign dpath_io_ctrl_alu_op = ctrl_io_alu_op; // @[core.scala 63:17:@1874.4]
+  assign dpath_io_ctrl_br_type = ctrl_io_br_type; // @[core.scala 63:17:@1873.4]
+  assign dpath_io_ctrl_st_type = ctrl_io_st_type; // @[core.scala 63:17:@1872.4]
+  assign dpath_io_ctrl_ld_type = ctrl_io_ld_type; // @[core.scala 63:17:@1871.4]
+  assign dpath_io_ctrl_wb_mux_sel = ctrl_io_wb_mux_sel; // @[core.scala 63:17:@1870.4]
+  assign dpath_io_ctrl_wb_en = ctrl_io_wb_en; // @[core.scala 63:17:@1869.4]
+  assign dpath_io_ctrl_csr_cmd = ctrl_io_csr_cmd; // @[core.scala 63:17:@1868.4]
+  assign dpath_io_ctrl_illegal = ctrl_io_illegal; // @[core.scala 63:17:@1867.4]
+  assign dpath_io_ctrl_en_rs1 = ctrl_io_en_rs1; // @[core.scala 63:17:@1866.4]
+  assign dpath_io_ctrl_en_rs2 = ctrl_io_en_rs2; // @[core.scala 63:17:@1865.4]
+  assign ctrl_io_inst = dpath_io_ctrl_inst; // @[core.scala 63:17:@1880.4]
+endmodule
diff --git a/verilog/rtl/DMem.v b/verilog/rtl/DMem.v
new file mode 100644
index 0000000..7108a81
--- /dev/null
+++ b/verilog/rtl/DMem.v
@@ -0,0 +1,178 @@
+module DMem( // @[:@12681.2]
+  input         clock, // @[:@12682.4]
+  input  [7:0]  io_addr, // @[:@12684.4]
+  input  [31:0] io_wdata, // @[:@12684.4]
+  output [31:0] io_rdata, // @[:@12684.4]
+  input         io_cs, // @[:@12684.4]
+  input         io_wr_en, // @[:@12684.4]
+  input  [3:0]  io_st_type // @[:@12684.4]
+);
+  reg [7:0] dmem [0:1023]; // @[dmemory.scala 26:26:@12686.4]
+  reg [31:0] _RAND_0;
+  wire [7:0] dmem__T_65_data; // @[dmemory.scala 26:26:@12686.4]
+  wire [9:0] dmem__T_65_addr; // @[dmemory.scala 26:26:@12686.4]
+  wire [7:0] dmem__T_69_data; // @[dmemory.scala 26:26:@12686.4]
+  wire [9:0] dmem__T_69_addr; // @[dmemory.scala 26:26:@12686.4]
+  wire [7:0] dmem__T_73_data; // @[dmemory.scala 26:26:@12686.4]
+  wire [9:0] dmem__T_73_addr; // @[dmemory.scala 26:26:@12686.4]
+  wire [7:0] dmem__T_74_data; // @[dmemory.scala 26:26:@12686.4]
+  wire [9:0] dmem__T_74_addr; // @[dmemory.scala 26:26:@12686.4]
+  wire [7:0] dmem__T_38_data; // @[dmemory.scala 26:26:@12686.4]
+  wire [9:0] dmem__T_38_addr; // @[dmemory.scala 26:26:@12686.4]
+  wire  dmem__T_38_mask; // @[dmemory.scala 26:26:@12686.4]
+  wire  dmem__T_38_en; // @[dmemory.scala 26:26:@12686.4]
+  wire [7:0] dmem__T_45_data; // @[dmemory.scala 26:26:@12686.4]
+  wire [9:0] dmem__T_45_addr; // @[dmemory.scala 26:26:@12686.4]
+  wire  dmem__T_45_mask; // @[dmemory.scala 26:26:@12686.4]
+  wire  dmem__T_45_en; // @[dmemory.scala 26:26:@12686.4]
+  wire [7:0] dmem__T_52_data; // @[dmemory.scala 26:26:@12686.4]
+  wire [9:0] dmem__T_52_addr; // @[dmemory.scala 26:26:@12686.4]
+  wire  dmem__T_52_mask; // @[dmemory.scala 26:26:@12686.4]
+  wire  dmem__T_52_en; // @[dmemory.scala 26:26:@12686.4]
+  wire [7:0] dmem__T_59_data; // @[dmemory.scala 26:26:@12686.4]
+  wire [9:0] dmem__T_59_addr; // @[dmemory.scala 26:26:@12686.4]
+  wire  dmem__T_59_mask; // @[dmemory.scala 26:26:@12686.4]
+  wire  dmem__T_59_en; // @[dmemory.scala 26:26:@12686.4]
+  wire  mem_wr; // @[dmemory.scala 31:27:@12687.4]
+  wire  _T_36; // @[dmemory.scala 40:18:@12690.6]
+  wire  _GEN_3; // @[dmemory.scala 40:30:@12692.6]
+  wire  _T_40; // @[dmemory.scala 43:18:@12697.6]
+  wire [8:0] _T_43; // @[dmemory.scala 44:17:@12700.8]
+  wire [7:0] _T_44; // @[dmemory.scala 44:17:@12701.8]
+  wire  _T_47; // @[dmemory.scala 46:18:@12706.6]
+  wire [8:0] _T_50; // @[dmemory.scala 47:17:@12709.8]
+  wire [7:0] _T_51; // @[dmemory.scala 47:17:@12710.8]
+  wire  _T_54; // @[dmemory.scala 49:18:@12715.6]
+  wire [8:0] _T_57; // @[dmemory.scala 50:17:@12718.8]
+  wire [7:0] _T_58; // @[dmemory.scala 50:17:@12719.8]
+  wire [15:0] _T_75; // @[Cat.scala 30:58:@12736.4]
+  wire [15:0] _T_76; // @[Cat.scala 30:58:@12737.4]
+  wire [9:0] _GEN_41;
+  reg [9:0] dmem__T_65_addr_pipe_0;
+  reg [31:0] _RAND_1;
+  wire [9:0] _GEN_43;
+  reg [9:0] dmem__T_69_addr_pipe_0;
+  reg [31:0] _RAND_2;
+  wire [9:0] _GEN_45;
+  reg [9:0] dmem__T_73_addr_pipe_0;
+  reg [31:0] _RAND_3;
+  wire [9:0] _GEN_47;
+  reg [9:0] dmem__T_74_addr_pipe_0;
+  reg [31:0] _RAND_4;
+  assign dmem__T_65_addr = dmem__T_65_addr_pipe_0;
+  assign dmem__T_65_data = dmem[dmem__T_65_addr]; // @[dmemory.scala 26:26:@12686.4]
+  assign dmem__T_69_addr = dmem__T_69_addr_pipe_0;
+  assign dmem__T_69_data = dmem[dmem__T_69_addr]; // @[dmemory.scala 26:26:@12686.4]
+  assign dmem__T_73_addr = dmem__T_73_addr_pipe_0;
+  assign dmem__T_73_data = dmem[dmem__T_73_addr]; // @[dmemory.scala 26:26:@12686.4]
+  assign dmem__T_74_addr = dmem__T_74_addr_pipe_0;
+  assign dmem__T_74_data = dmem[dmem__T_74_addr]; // @[dmemory.scala 26:26:@12686.4]
+  assign dmem__T_38_data = io_wdata[7:0];
+  assign dmem__T_38_addr = {{2'd0}, io_addr};
+  assign dmem__T_38_mask = 1'h1;
+  assign dmem__T_38_en = mem_wr ? _T_36 : 1'h0;
+  assign dmem__T_45_data = io_wdata[15:8];
+  assign dmem__T_45_addr = {{2'd0}, _T_44};
+  assign dmem__T_45_mask = 1'h1;
+  assign dmem__T_45_en = mem_wr ? _T_40 : 1'h0;
+  assign dmem__T_52_data = io_wdata[23:16];
+  assign dmem__T_52_addr = {{2'd0}, _T_51};
+  assign dmem__T_52_mask = 1'h1;
+  assign dmem__T_52_en = mem_wr ? _T_47 : 1'h0;
+  assign dmem__T_59_data = io_wdata[31:24];
+  assign dmem__T_59_addr = {{2'd0}, _T_58};
+  assign dmem__T_59_mask = 1'h1;
+  assign dmem__T_59_en = mem_wr ? _T_54 : 1'h0;
+  assign mem_wr = io_wr_en & io_cs; // @[dmemory.scala 31:27:@12687.4]
+  assign _T_36 = io_st_type[0]; // @[dmemory.scala 40:18:@12690.6]
+  assign _GEN_3 = 1'h1; // @[dmemory.scala 40:30:@12692.6]
+  assign _T_40 = io_st_type[1]; // @[dmemory.scala 43:18:@12697.6]
+  assign _T_43 = io_addr + 8'h1; // @[dmemory.scala 44:17:@12700.8]
+  assign _T_44 = io_addr + 8'h1; // @[dmemory.scala 44:17:@12701.8]
+  assign _T_47 = io_st_type[2]; // @[dmemory.scala 46:18:@12706.6]
+  assign _T_50 = io_addr + 8'h2; // @[dmemory.scala 47:17:@12709.8]
+  assign _T_51 = io_addr + 8'h2; // @[dmemory.scala 47:17:@12710.8]
+  assign _T_54 = io_st_type[3]; // @[dmemory.scala 49:18:@12715.6]
+  assign _T_57 = io_addr + 8'h3; // @[dmemory.scala 50:17:@12718.8]
+  assign _T_58 = io_addr + 8'h3; // @[dmemory.scala 50:17:@12719.8]
+  assign _T_75 = {dmem__T_73_data,dmem__T_74_data}; // @[Cat.scala 30:58:@12736.4]
+  assign _T_76 = {dmem__T_65_data,dmem__T_69_data}; // @[Cat.scala 30:58:@12737.4]
+  assign io_rdata = {_T_76,_T_75}; // @[dmemory.scala 57:12:@12740.4]
+  assign _GEN_41 = {{2'd0}, _T_58};
+  assign _GEN_43 = {{2'd0}, _T_51};
+  assign _GEN_45 = {{2'd0}, _T_44};
+  assign _GEN_47 = {{2'd0}, io_addr};
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE
+  integer initvar;
+  initial begin
+    `ifdef INIT_RANDOM
+      `INIT_RANDOM
+    `endif
+    `ifndef VERILATOR
+      #0.002 begin end
+    `endif
+  _RAND_0 = {1{`RANDOM}};
+  `ifdef RANDOMIZE_MEM_INIT
+  for (initvar = 0; initvar < 1024; initvar = initvar+1)
+    dmem[initvar] = _RAND_0[7:0];
+  `endif // RANDOMIZE_MEM_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_1 = {1{`RANDOM}};
+  dmem__T_65_addr_pipe_0 = _RAND_1[9:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_2 = {1{`RANDOM}};
+  dmem__T_69_addr_pipe_0 = _RAND_2[9:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_3 = {1{`RANDOM}};
+  dmem__T_73_addr_pipe_0 = _RAND_3[9:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_4 = {1{`RANDOM}};
+  dmem__T_74_addr_pipe_0 = _RAND_4[9:0];
+  `endif // RANDOMIZE_REG_INIT
+  end
+`endif // RANDOMIZE
+  always @(posedge clock) begin
+    if(dmem__T_38_en & dmem__T_38_mask) begin
+      dmem[dmem__T_38_addr] <= dmem__T_38_data; // @[dmemory.scala 26:26:@12686.4]
+    end
+    if(dmem__T_45_en & dmem__T_45_mask) begin
+      dmem[dmem__T_45_addr] <= dmem__T_45_data; // @[dmemory.scala 26:26:@12686.4]
+    end
+    if(dmem__T_52_en & dmem__T_52_mask) begin
+      dmem[dmem__T_52_addr] <= dmem__T_52_data; // @[dmemory.scala 26:26:@12686.4]
+    end
+    if(dmem__T_59_en & dmem__T_59_mask) begin
+      dmem[dmem__T_59_addr] <= dmem__T_59_data; // @[dmemory.scala 26:26:@12686.4]
+    end
+    if (_GEN_3) begin
+      dmem__T_65_addr_pipe_0 <= _GEN_41;
+    end
+    if (_GEN_3) begin
+      dmem__T_69_addr_pipe_0 <= _GEN_43;
+    end
+    if (_GEN_3) begin
+      dmem__T_73_addr_pipe_0 <= _GEN_45;
+    end
+    if (_GEN_3) begin
+      dmem__T_74_addr_pipe_0 <= _GEN_47;
+    end
+  end
+endmodule
diff --git a/verilog/rtl/IMem.v b/verilog/rtl/IMem.v
new file mode 100644
index 0000000..1df1163
--- /dev/null
+++ b/verilog/rtl/IMem.v
@@ -0,0 +1,73 @@
+module IMem( // @[:@12666.2]
+  input         clock, // @[:@12667.4]
+  input  [8:0]  io_addr, // @[:@12669.4]
+  output [31:0] io_rdata, // @[:@12669.4]
+  input  [31:0] io_wdata, // @[:@12669.4]
+  input         io_wr_en, // @[:@12669.4]
+  input         io_cs // @[:@12669.4]
+);
+  reg [31:0] imem [0:2047]; // @[imemory.scala 26:25:@12671.4]
+  reg [31:0] _RAND_0;
+  wire [31:0] imem__T_37_data; // @[imemory.scala 26:25:@12671.4]
+  wire [10:0] imem__T_37_addr; // @[imemory.scala 26:25:@12671.4]
+  wire [31:0] imem__T_36_data; // @[imemory.scala 26:25:@12671.4]
+  wire [10:0] imem__T_36_addr; // @[imemory.scala 26:25:@12671.4]
+  wire  imem__T_36_mask; // @[imemory.scala 26:25:@12671.4]
+  wire  imem__T_36_en; // @[imemory.scala 26:25:@12671.4]
+  wire  _GEN_3; // @[imemory.scala 41:17:@12674.4]
+  wire [10:0] _GEN_6;
+  reg [10:0] imem__T_37_addr_pipe_0;
+  reg [31:0] _RAND_1;
+  assign imem__T_37_addr = imem__T_37_addr_pipe_0;
+  assign imem__T_37_data = imem[imem__T_37_addr]; // @[imemory.scala 26:25:@12671.4]
+  assign imem__T_36_data = io_wdata;
+  assign imem__T_36_addr = {{2'd0}, io_addr};
+  assign imem__T_36_mask = 1'h1;
+  assign imem__T_36_en = io_wr_en & io_cs;
+  assign _GEN_3 = 1'h1; // @[imemory.scala 41:17:@12674.4]
+  assign io_rdata = imem__T_37_data; // @[imemory.scala 45:12:@12679.4]
+  assign _GEN_6 = {{2'd0}, io_addr};
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE
+  integer initvar;
+  initial begin
+    `ifdef INIT_RANDOM
+      `INIT_RANDOM
+    `endif
+    `ifndef VERILATOR
+      #0.002 begin end
+    `endif
+  _RAND_0 = {1{`RANDOM}};
+  `ifdef RANDOMIZE_MEM_INIT
+  for (initvar = 0; initvar < 2048; initvar = initvar+1)
+    imem[initvar] = _RAND_0[31:0];
+  `endif // RANDOMIZE_MEM_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_1 = {1{`RANDOM}};
+  imem__T_37_addr_pipe_0 = _RAND_1[10:0];
+  `endif // RANDOMIZE_REG_INIT
+  end
+`endif // RANDOMIZE
+  always @(posedge clock) begin
+    if(imem__T_36_en & imem__T_36_mask) begin
+      imem[imem__T_36_addr] <= imem__T_36_data; // @[imemory.scala 26:25:@12671.4]
+    end
+    if (_GEN_3) begin
+      imem__T_37_addr_pipe_0 <= _GEN_6;
+    end
+  end
+endmodule
\ No newline at end of file
diff --git a/verilog/rtl/Motor_Top.v b/verilog/rtl/Motor_Top.v
new file mode 100644
index 0000000..af06661
--- /dev/null
+++ b/verilog/rtl/Motor_Top.v
@@ -0,0 +1,1905 @@
+module Interlink_Module( // @[:@4032.2]
+  input         clock, // @[:@4033.4]
+  input         reset, // @[:@4034.4]
+  input  [31:0] io_bus_adr_i, // @[:@4035.4]
+  input  [3:0]  io_bus_sel_i, // @[:@4035.4]
+  input         io_bus_we_i, // @[:@4035.4]
+  input         io_bus_stb_i, // @[:@4035.4]
+  output        io_bus_ack_o, // @[:@4035.4]
+  output [31:0] io_bus_dat_o, // @[:@4035.4]
+  output        io_tmr_val_we, // @[:@4035.4]
+  input  [31:0] io_tmr_val_do, // @[:@4035.4]
+  output        io_tmr_dat_we, // @[:@4035.4]
+  input  [31:0] io_tmr_dat_do, // @[:@4035.4]
+  output        io_tmr_duty_we, // @[:@4035.4]
+  input  [31:0] io_tmr_duty_do, // @[:@4035.4]
+  output        io_tmr_cfg_we, // @[:@4035.4]
+  input  [31:0] io_tmr_cfg_do, // @[:@4035.4]
+  output        io_qei_count_we, // @[:@4035.4]
+  input  [31:0] io_qei_count_do, // @[:@4035.4]
+  output        io_qei_cfg_we, // @[:@4035.4]
+  input  [31:0] io_qei_cfg_do, // @[:@4035.4]
+  input  [15:0] io_qei_speed_do, // @[:@4035.4]
+  output        io_pid_kp_we, // @[:@4035.4]
+  input  [15:0] io_pid_kp_do, // @[:@4035.4]
+  output        io_pid_ki_we, // @[:@4035.4]
+  input  [15:0] io_pid_ki_do, // @[:@4035.4]
+  output        io_pid_kd_we, // @[:@4035.4]
+  input  [15:0] io_pid_kd_do, // @[:@4035.4]
+  output        io_pid_ref_we, // @[:@4035.4]
+  input  [15:0] io_pid_ref_do, // @[:@4035.4]
+  output        io_pid_fb_we, // @[:@4035.4]
+  input  [15:0] io_pid_fb_do, // @[:@4035.4]
+  output        io_pid_cfg_we, // @[:@4035.4]
+  input  [15:0] io_pid_cfg_do, // @[:@4035.4]
+  input         io_ba_match // @[:@4035.4]
+);
+  wire [11:0] reg_offset; // @[interlink.scala 98:35:@4044.4]
+  wire  _T_78; // @[interlink.scala 100:50:@4045.4]
+  wire  _T_79; // @[interlink.scala 100:81:@4046.4]
+  wire  tmr_cfg_sel; // @[interlink.scala 100:66:@4047.4]
+  wire  _T_83; // @[interlink.scala 101:81:@4051.4]
+  wire  tmr_val_sel; // @[interlink.scala 101:66:@4052.4]
+  wire  _T_87; // @[interlink.scala 102:81:@4056.4]
+  wire  tmr_dat_sel; // @[interlink.scala 102:66:@4057.4]
+  wire  _T_91; // @[interlink.scala 103:81:@4061.4]
+  wire  tmr_duty_sel; // @[interlink.scala 103:66:@4062.4]
+  wire  _T_94; // @[interlink.scala 105:72:@4065.4]
+  wire  _T_95; // @[interlink.scala 105:76:@4066.4]
+  wire  _T_121; // @[interlink.scala 112:35:@4092.4]
+  wire  _T_122; // @[interlink.scala 112:50:@4093.4]
+  wire  tmr_sel; // @[interlink.scala 112:65:@4094.4]
+  wire [31:0] _T_123; // @[interlink.scala 114:26:@4095.4]
+  wire [31:0] _T_124; // @[interlink.scala 113:57:@4096.4]
+  wire [31:0] tmr_do; // @[interlink.scala 113:26:@4097.4]
+  wire  _T_128; // @[interlink.scala 118:81:@4100.4]
+  wire  qei_count_sel; // @[interlink.scala 118:66:@4101.4]
+  wire  _T_138; // @[interlink.scala 122:81:@4111.4]
+  wire  qei_cfg_sel; // @[interlink.scala 122:66:@4112.4]
+  wire  _T_148; // @[interlink.scala 126:81:@4122.4]
+  wire  qei_speed_sel; // @[interlink.scala 126:66:@4123.4]
+  wire  _T_155; // @[interlink.scala 130:37:@4131.4]
+  wire  qei_sel; // @[interlink.scala 130:52:@4132.4]
+  wire [31:0] _T_156; // @[interlink.scala 131:59:@4133.4]
+  wire [15:0] _T_236; // @[interlink.scala 187:46:@4235.4]
+  wire [31:0] qei_speed_do; // @[interlink.scala 125:27:@4120.4 interlink.scala 187:21:@4236.4]
+  wire [31:0] qei_do; // @[interlink.scala 131:26:@4134.4]
+  wire  _T_160; // @[interlink.scala 135:81:@4137.4]
+  wire  pid_kp_sel; // @[interlink.scala 135:66:@4138.4]
+  wire  _T_170; // @[interlink.scala 139:81:@4148.4]
+  wire  pid_ki_sel; // @[interlink.scala 139:66:@4149.4]
+  wire  _T_180; // @[interlink.scala 143:81:@4159.4]
+  wire  pid_kd_sel; // @[interlink.scala 143:66:@4160.4]
+  wire  _T_190; // @[interlink.scala 147:81:@4170.4]
+  wire  pid_ref_sel; // @[interlink.scala 147:66:@4171.4]
+  wire  _T_200; // @[interlink.scala 151:81:@4181.4]
+  wire  pid_fb_sel; // @[interlink.scala 151:66:@4182.4]
+  wire  _T_210; // @[interlink.scala 155:81:@4192.4]
+  wire  pid_cfg_sel; // @[interlink.scala 155:66:@4193.4]
+  wire  _T_217; // @[interlink.scala 158:34:@4201.4]
+  wire  _T_218; // @[interlink.scala 158:48:@4202.4]
+  wire  _T_219; // @[interlink.scala 158:62:@4203.4]
+  wire  _T_220; // @[interlink.scala 158:77:@4204.4]
+  wire  pid_sel; // @[interlink.scala 158:91:@4205.4]
+  wire [15:0] _T_221; // @[interlink.scala 162:46:@4206.4]
+  wire [15:0] _T_222; // @[interlink.scala 161:46:@4207.4]
+  wire [15:0] _T_223; // @[interlink.scala 160:46:@4208.4]
+  wire [15:0] _T_224; // @[interlink.scala 159:53:@4209.4]
+  wire [15:0] pid_do; // @[interlink.scala 159:26:@4210.4]
+  reg  wb_ack_o; // @[interlink.scala 165:30:@4211.4]
+  reg [31:0] _RAND_0;
+  reg [31:0] wb_data_o; // @[interlink.scala 166:30:@4212.4]
+  reg [31:0] _RAND_1;
+  wire [15:0] _T_229; // @[interlink.scala 167:92:@4213.4]
+  wire [15:0] _T_231; // @[interlink.scala 167:69:@4214.4]
+  wire [31:0] _T_232; // @[interlink.scala 167:48:@4215.4]
+  wire [31:0] _T_233; // @[interlink.scala 167:27:@4216.4]
+  wire  _T_234; // @[interlink.scala 168:32:@4218.4]
+  wire  _T_235; // @[interlink.scala 168:43:@4219.4]
+  assign reg_offset = io_bus_adr_i[11:0]; // @[interlink.scala 98:35:@4044.4]
+  assign _T_78 = io_bus_stb_i & io_ba_match; // @[interlink.scala 100:50:@4045.4]
+  assign _T_79 = reg_offset == 12'h0; // @[interlink.scala 100:81:@4046.4]
+  assign tmr_cfg_sel = _T_78 & _T_79; // @[interlink.scala 100:66:@4047.4]
+  assign _T_83 = reg_offset == 12'h4; // @[interlink.scala 101:81:@4051.4]
+  assign tmr_val_sel = _T_78 & _T_83; // @[interlink.scala 101:66:@4052.4]
+  assign _T_87 = reg_offset == 12'h8; // @[interlink.scala 102:81:@4056.4]
+  assign tmr_dat_sel = _T_78 & _T_87; // @[interlink.scala 102:66:@4057.4]
+  assign _T_91 = reg_offset == 12'hc; // @[interlink.scala 103:81:@4061.4]
+  assign tmr_duty_sel = _T_78 & _T_91; // @[interlink.scala 103:66:@4062.4]
+  assign _T_94 = io_bus_sel_i[0]; // @[interlink.scala 105:72:@4065.4]
+  assign _T_95 = _T_94 & io_bus_we_i; // @[interlink.scala 105:76:@4066.4]
+  assign _T_121 = tmr_cfg_sel | tmr_val_sel; // @[interlink.scala 112:35:@4092.4]
+  assign _T_122 = _T_121 | tmr_dat_sel; // @[interlink.scala 112:50:@4093.4]
+  assign tmr_sel = _T_122 | tmr_duty_sel; // @[interlink.scala 112:65:@4094.4]
+  assign _T_123 = tmr_duty_sel ? io_tmr_duty_do : io_tmr_dat_do; // @[interlink.scala 114:26:@4095.4]
+  assign _T_124 = tmr_val_sel ? io_tmr_val_do : _T_123; // @[interlink.scala 113:57:@4096.4]
+  assign tmr_do = tmr_cfg_sel ? io_tmr_cfg_do : _T_124; // @[interlink.scala 113:26:@4097.4]
+  assign _T_128 = reg_offset == 12'h100; // @[interlink.scala 118:81:@4100.4]
+  assign qei_count_sel = _T_78 & _T_128; // @[interlink.scala 118:66:@4101.4]
+  assign _T_138 = reg_offset == 12'h108; // @[interlink.scala 122:81:@4111.4]
+  assign qei_cfg_sel = _T_78 & _T_138; // @[interlink.scala 122:66:@4112.4]
+  assign _T_148 = reg_offset == 12'h104; // @[interlink.scala 126:81:@4122.4]
+  assign qei_speed_sel = _T_78 & _T_148; // @[interlink.scala 126:66:@4123.4]
+  assign _T_155 = qei_count_sel | qei_cfg_sel; // @[interlink.scala 130:37:@4131.4]
+  assign qei_sel = _T_155 | qei_speed_sel; // @[interlink.scala 130:52:@4132.4]
+  assign _T_156 = qei_cfg_sel ? io_qei_cfg_do : io_qei_count_do; // @[interlink.scala 131:59:@4133.4]
+  assign _T_236 = $unsigned(io_qei_speed_do); // @[interlink.scala 187:46:@4235.4]
+  assign qei_speed_do = {{16'd0}, _T_236}; // @[interlink.scala 125:27:@4120.4 interlink.scala 187:21:@4236.4]
+  assign qei_do = qei_speed_sel ? qei_speed_do : _T_156; // @[interlink.scala 131:26:@4134.4]
+  assign _T_160 = reg_offset == 12'h200; // @[interlink.scala 135:81:@4137.4]
+  assign pid_kp_sel = _T_78 & _T_160; // @[interlink.scala 135:66:@4138.4]
+  assign _T_170 = reg_offset == 12'h204; // @[interlink.scala 139:81:@4148.4]
+  assign pid_ki_sel = _T_78 & _T_170; // @[interlink.scala 139:66:@4149.4]
+  assign _T_180 = reg_offset == 12'h208; // @[interlink.scala 143:81:@4159.4]
+  assign pid_kd_sel = _T_78 & _T_180; // @[interlink.scala 143:66:@4160.4]
+  assign _T_190 = reg_offset == 12'h20c; // @[interlink.scala 147:81:@4170.4]
+  assign pid_ref_sel = _T_78 & _T_190; // @[interlink.scala 147:66:@4171.4]
+  assign _T_200 = reg_offset == 12'h210; // @[interlink.scala 151:81:@4181.4]
+  assign pid_fb_sel = _T_78 & _T_200; // @[interlink.scala 151:66:@4182.4]
+  assign _T_210 = reg_offset == 12'h214; // @[interlink.scala 155:81:@4192.4]
+  assign pid_cfg_sel = _T_78 & _T_210; // @[interlink.scala 155:66:@4193.4]
+  assign _T_217 = pid_kp_sel | pid_ki_sel; // @[interlink.scala 158:34:@4201.4]
+  assign _T_218 = _T_217 | pid_kd_sel; // @[interlink.scala 158:48:@4202.4]
+  assign _T_219 = _T_218 | pid_ref_sel; // @[interlink.scala 158:62:@4203.4]
+  assign _T_220 = _T_219 | pid_fb_sel; // @[interlink.scala 158:77:@4204.4]
+  assign pid_sel = _T_220 | pid_cfg_sel; // @[interlink.scala 158:91:@4205.4]
+  assign _T_221 = pid_fb_sel ? $signed(io_pid_fb_do) : $signed(io_pid_cfg_do); // @[interlink.scala 162:46:@4206.4]
+  assign _T_222 = pid_ref_sel ? $signed(io_pid_ref_do) : $signed(_T_221); // @[interlink.scala 161:46:@4207.4]
+  assign _T_223 = pid_kd_sel ? $signed(io_pid_kd_do) : $signed(_T_222); // @[interlink.scala 160:46:@4208.4]
+  assign _T_224 = pid_ki_sel ? $signed(io_pid_ki_do) : $signed(_T_223); // @[interlink.scala 159:53:@4209.4]
+  assign pid_do = pid_kp_sel ? $signed(io_pid_kp_do) : $signed(_T_224); // @[interlink.scala 159:26:@4210.4]
+  assign _T_229 = $unsigned(pid_do); // @[interlink.scala 167:92:@4213.4]
+  assign _T_231 = pid_sel ? _T_229 : 16'h0; // @[interlink.scala 167:69:@4214.4]
+  assign _T_232 = qei_sel ? qei_do : {{16'd0}, _T_231}; // @[interlink.scala 167:48:@4215.4]
+  assign _T_233 = tmr_sel ? tmr_do : _T_232; // @[interlink.scala 167:27:@4216.4]
+  assign _T_234 = tmr_sel | qei_sel; // @[interlink.scala 168:32:@4218.4]
+  assign _T_235 = _T_234 | pid_sel; // @[interlink.scala 168:43:@4219.4]
+  assign io_bus_ack_o = wb_ack_o; // @[interlink.scala 171:21:@4222.4]
+  assign io_bus_dat_o = wb_data_o; // @[interlink.scala 170:21:@4221.4]
+  assign io_tmr_val_we = tmr_val_sel ? _T_95 : 1'h0; // @[interlink.scala 174:21:@4223.4]
+  assign io_tmr_dat_we = tmr_dat_sel ? _T_95 : 1'h0; // @[interlink.scala 176:21:@4225.4]
+  assign io_tmr_duty_we = tmr_duty_sel ? _T_95 : 1'h0; // @[interlink.scala 178:21:@4227.4]
+  assign io_tmr_cfg_we = tmr_cfg_sel ? _T_95 : 1'h0; // @[interlink.scala 180:21:@4229.4]
+  assign io_qei_count_we = qei_count_sel ? _T_95 : 1'h0; // @[interlink.scala 183:21:@4231.4]
+  assign io_qei_cfg_we = qei_cfg_sel ? _T_95 : 1'h0; // @[interlink.scala 185:21:@4233.4]
+  assign io_pid_kp_we = pid_kp_sel ? _T_95 : 1'h0; // @[interlink.scala 189:21:@4237.4]
+  assign io_pid_ki_we = pid_ki_sel ? _T_95 : 1'h0; // @[interlink.scala 191:21:@4239.4]
+  assign io_pid_kd_we = pid_kd_sel ? _T_95 : 1'h0; // @[interlink.scala 193:21:@4241.4]
+  assign io_pid_ref_we = pid_ref_sel ? _T_95 : 1'h0; // @[interlink.scala 195:21:@4243.4]
+  assign io_pid_fb_we = pid_fb_sel ? _T_95 : 1'h0; // @[interlink.scala 197:21:@4245.4]
+  assign io_pid_cfg_we = pid_cfg_sel ? _T_95 : 1'h0; // @[interlink.scala 199:21:@4247.4]
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE
+  integer initvar;
+  initial begin
+    `ifdef INIT_RANDOM
+      `INIT_RANDOM
+    `endif
+    `ifndef VERILATOR
+      #0.002 begin end
+    `endif
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_0 = {1{`RANDOM}};
+  wb_ack_o = _RAND_0[0:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_1 = {1{`RANDOM}};
+  wb_data_o = _RAND_1[31:0];
+  `endif // RANDOMIZE_REG_INIT
+  end
+`endif // RANDOMIZE
+  always @(posedge clock) begin
+    if (reset) begin
+      wb_ack_o <= 1'h0;
+    end else begin
+      wb_ack_o <= _T_235;
+    end
+    if (reset) begin
+      wb_data_o <= 32'h0;
+    end else begin
+      if (tmr_sel) begin
+        if (tmr_cfg_sel) begin
+          wb_data_o <= io_tmr_cfg_do;
+        end else begin
+          if (tmr_val_sel) begin
+            wb_data_o <= io_tmr_val_do;
+          end else begin
+            if (tmr_duty_sel) begin
+              wb_data_o <= io_tmr_duty_do;
+            end else begin
+              wb_data_o <= io_tmr_dat_do;
+            end
+          end
+        end
+      end else begin
+        if (qei_sel) begin
+          if (qei_speed_sel) begin
+            wb_data_o <= qei_speed_do;
+          end else begin
+            if (qei_cfg_sel) begin
+              wb_data_o <= io_qei_cfg_do;
+            end else begin
+              wb_data_o <= io_qei_count_do;
+            end
+          end
+        end else begin
+          wb_data_o <= {{16'd0}, _T_231};
+        end
+      end
+    end
+  end
+endmodule
+module PWM( // @[:@4250.2]
+  input         clock, // @[:@4251.4]
+  input         reset, // @[:@4252.4]
+  input         io_reg_val_we, // @[:@4253.4]
+  input  [31:0] io_reg_val_di, // @[:@4253.4]
+  output [31:0] io_reg_val_do, // @[:@4253.4]
+  input         io_reg_cfg_we, // @[:@4253.4]
+  input  [31:0] io_reg_cfg_di, // @[:@4253.4]
+  output [31:0] io_reg_cfg_do, // @[:@4253.4]
+  input         io_reg_dat_we, // @[:@4253.4]
+  input  [31:0] io_reg_dat_di, // @[:@4253.4]
+  output [31:0] io_reg_dat_do, // @[:@4253.4]
+  input         io_reg_duty_we, // @[:@4253.4]
+  input  [31:0] io_reg_duty_di, // @[:@4253.4]
+  output [31:0] io_reg_duty_do, // @[:@4253.4]
+  input  [15:0] io_reg_pid_out, // @[:@4253.4]
+  output        io_pwm_h, // @[:@4253.4]
+  output        io_pwm_l, // @[:@4253.4]
+  output        io_irq_out, // @[:@4253.4]
+  output        io_rawirq_out // @[:@4253.4]
+);
+  reg [31:0] value_cur; // @[pwm.scala 44:32:@4255.4]
+  reg [31:0] _RAND_0;
+  reg [31:0] value_reload; // @[pwm.scala 45:32:@4256.4]
+  reg [31:0] _RAND_1;
+  reg [31:0] pwm_duty; // @[pwm.scala 46:32:@4257.4]
+  reg [31:0] _RAND_2;
+  reg [31:0] reg_duty; // @[pwm.scala 47:32:@4258.4]
+  reg [31:0] _RAND_3;
+  reg  enable; // @[pwm.scala 54:32:@4262.4]
+  reg [31:0] _RAND_4;
+  reg  stop_out; // @[pwm.scala 56:32:@4263.4]
+  reg [31:0] _RAND_5;
+  reg  irq_out; // @[pwm.scala 57:32:@4264.4]
+  reg [31:0] _RAND_6;
+  reg  lastenable; // @[pwm.scala 60:28:@4265.4]
+  reg [31:0] _RAND_7;
+  reg  updown; // @[pwm.scala 63:32:@4266.4]
+  reg [31:0] _RAND_8;
+  reg  irq_ena; // @[pwm.scala 66:32:@4267.4]
+  reg [31:0] _RAND_9;
+  reg  pid_out_sel; // @[pwm.scala 69:32:@4268.4]
+  reg [31:0] _RAND_10;
+  reg [3:0] pwm_db; // @[pwm.scala 72:32:@4269.4]
+  reg [31:0] _RAND_11;
+  wire [31:0] _GEN_0; // @[pwm.scala 76:24:@4271.4]
+  wire [15:0] _T_65; // @[pwm.scala 82:40:@4276.8]
+  wire [31:0] _GEN_1; // @[pwm.scala 81:22:@4275.6]
+  wire [31:0] _GEN_2; // @[pwm.scala 80:18:@4274.4]
+  reg [31:0] proc_offset; // @[pwm.scala 88:24:@4283.4]
+  reg [31:0] _RAND_12;
+  reg  pwm_ld; // @[pwm.scala 89:24:@4284.4]
+  reg [31:0] _RAND_13;
+  reg  pwm_hd; // @[pwm.scala 90:24:@4285.4]
+  reg [31:0] _RAND_14;
+  wire [4:0] _GEN_25; // @[pwm.scala 93:30:@4286.4]
+  wire [4:0] pwm_db_twice; // @[pwm.scala 93:30:@4286.4]
+  wire [31:0] _GEN_26; // @[pwm.scala 95:37:@4287.4]
+  wire  _T_70; // @[pwm.scala 95:37:@4287.4]
+  wire [32:0] _T_71; // @[pwm.scala 95:84:@4288.4]
+  wire [32:0] _T_72; // @[pwm.scala 95:84:@4289.4]
+  wire [31:0] _T_73; // @[pwm.scala 95:84:@4290.4]
+  wire  _T_74; // @[pwm.scala 95:67:@4291.4]
+  wire  _T_75; // @[pwm.scala 95:54:@4292.4]
+  wire  _T_76; // @[pwm.scala 96:36:@4293.4]
+  wire [31:0] _T_80; // @[pwm.scala 96:26:@4297.4]
+  wire [31:0] _GEN_30; // @[pwm.scala 97:48:@4300.4]
+  wire [32:0] _T_82; // @[pwm.scala 97:48:@4300.4]
+  wire [32:0] _T_83; // @[pwm.scala 97:48:@4301.4]
+  wire [31:0] _T_84; // @[pwm.scala 97:48:@4302.4]
+  wire  _T_86; // @[pwm.scala 98:34:@4305.4]
+  wire [32:0] _T_87; // @[pwm.scala 98:79:@4306.4]
+  wire [32:0] _T_88; // @[pwm.scala 98:79:@4307.4]
+  wire [31:0] _T_89; // @[pwm.scala 98:79:@4308.4]
+  wire  _T_90; // @[pwm.scala 98:63:@4309.4]
+  wire  _T_94; // @[pwm.scala 104:34:@4317.4]
+  wire  _T_95; // @[pwm.scala 104:32:@4318.4]
+  wire [2:0] _T_99; // @[Cat.scala 30:58:@4322.4]
+  wire [28:0] _T_101; // @[Cat.scala 30:58:@4324.4]
+  wire  _T_103; // @[pwm.scala 109:35:@4328.6]
+  wire  _T_104; // @[pwm.scala 110:35:@4330.6]
+  wire  _T_105; // @[pwm.scala 111:35:@4332.6]
+  wire  _T_106; // @[pwm.scala 112:35:@4334.6]
+  wire [3:0] _T_107; // @[pwm.scala 113:36:@4336.6]
+  wire [4:0] _T_109; // @[pwm.scala 113:42:@4337.6]
+  wire [3:0] _T_110; // @[pwm.scala 113:42:@4338.6]
+  wire  _GEN_3; // @[pwm.scala 108:23:@4327.4]
+  wire  _GEN_4; // @[pwm.scala 108:23:@4327.4]
+  wire  _GEN_5; // @[pwm.scala 108:23:@4327.4]
+  wire  _GEN_6; // @[pwm.scala 108:23:@4327.4]
+  wire [3:0] _GEN_7; // @[pwm.scala 108:23:@4327.4]
+  wire [31:0] _GEN_8; // @[pwm.scala 118:29:@4343.4]
+  wire [32:0] _T_114; // @[pwm.scala 124:39:@4347.4]
+  wire [31:0] value_cur_plus; // @[pwm.scala 124:39:@4348.4]
+  wire [32:0] _T_117; // @[pwm.scala 125:39:@4350.4]
+  wire [32:0] _T_118; // @[pwm.scala 125:39:@4351.4]
+  wire [31:0] value_cur_minus; // @[pwm.scala 125:39:@4352.4]
+  wire  _T_127; // @[pwm.scala 135:23:@4365.8]
+  wire  _T_131; // @[pwm.scala 138:25:@4369.10]
+  wire  _T_134; // @[pwm.scala 143:33:@4375.12]
+  wire [31:0] _GEN_9; // @[pwm.scala 143:58:@4376.12]
+  wire [31:0] _GEN_11; // @[pwm.scala 138:38:@4370.10]
+  wire  _GEN_12; // @[pwm.scala 138:38:@4370.10]
+  wire  _T_142; // @[pwm.scala 158:35:@4393.12]
+  wire [31:0] _GEN_13; // @[pwm.scala 158:50:@4394.12]
+  wire [31:0] _GEN_15; // @[pwm.scala 153:38:@4388.10]
+  wire  _GEN_16; // @[pwm.scala 153:38:@4388.10]
+  wire [31:0] _GEN_17; // @[pwm.scala 137:31:@4368.8]
+  wire  _GEN_18; // @[pwm.scala 137:31:@4368.8]
+  wire  _GEN_19; // @[pwm.scala 132:39:@4362.6]
+  wire [31:0] _GEN_20; // @[pwm.scala 132:39:@4362.6]
+  wire  _GEN_21; // @[pwm.scala 132:39:@4362.6]
+  wire [31:0] _GEN_22; // @[pwm.scala 130:29:@4357.4]
+  wire  _GEN_23; // @[pwm.scala 130:29:@4357.4]
+  wire  _GEN_24; // @[pwm.scala 130:29:@4357.4]
+  assign _GEN_0 = io_reg_duty_we ? io_reg_duty_di : reg_duty; // @[pwm.scala 76:24:@4271.4]
+  assign _T_65 = $unsigned(io_reg_pid_out); // @[pwm.scala 82:40:@4276.8]
+  assign _GEN_1 = pid_out_sel ? {{16'd0}, _T_65} : reg_duty; // @[pwm.scala 81:22:@4275.6]
+  assign _GEN_2 = stop_out ? _GEN_1 : pwm_duty; // @[pwm.scala 80:18:@4274.4]
+  assign _GEN_25 = {{1'd0}, pwm_db}; // @[pwm.scala 93:30:@4286.4]
+  assign pwm_db_twice = _GEN_25 << 1'h1; // @[pwm.scala 93:30:@4286.4]
+  assign _GEN_26 = {{27'd0}, pwm_db_twice}; // @[pwm.scala 95:37:@4287.4]
+  assign _T_70 = pwm_duty >= _GEN_26; // @[pwm.scala 95:37:@4287.4]
+  assign _T_71 = value_reload - _GEN_26; // @[pwm.scala 95:84:@4288.4]
+  assign _T_72 = $unsigned(_T_71); // @[pwm.scala 95:84:@4289.4]
+  assign _T_73 = _T_72[31:0]; // @[pwm.scala 95:84:@4290.4]
+  assign _T_74 = pwm_duty <= _T_73; // @[pwm.scala 95:67:@4291.4]
+  assign _T_75 = _T_70 & _T_74; // @[pwm.scala 95:54:@4292.4]
+  assign _T_76 = pwm_duty < _GEN_26; // @[pwm.scala 96:36:@4293.4]
+  assign _T_80 = _T_76 ? {{27'd0}, pwm_db_twice} : _T_73; // @[pwm.scala 96:26:@4297.4]
+  assign _GEN_30 = {{28'd0}, pwm_db}; // @[pwm.scala 97:48:@4300.4]
+  assign _T_82 = proc_offset - _GEN_30; // @[pwm.scala 97:48:@4300.4]
+  assign _T_83 = $unsigned(_T_82); // @[pwm.scala 97:48:@4301.4]
+  assign _T_84 = _T_83[31:0]; // @[pwm.scala 97:48:@4302.4]
+  assign _T_86 = value_cur > proc_offset; // @[pwm.scala 98:34:@4305.4]
+  assign _T_87 = value_reload - _GEN_30; // @[pwm.scala 98:79:@4306.4]
+  assign _T_88 = $unsigned(_T_87); // @[pwm.scala 98:79:@4307.4]
+  assign _T_89 = _T_88[31:0]; // @[pwm.scala 98:79:@4308.4]
+  assign _T_90 = value_cur < _T_89; // @[pwm.scala 98:63:@4309.4]
+  assign _T_94 = ~ irq_out; // @[pwm.scala 104:34:@4317.4]
+  assign _T_95 = stop_out & _T_94; // @[pwm.scala 104:32:@4318.4]
+  assign _T_99 = {irq_ena,updown,enable}; // @[Cat.scala 30:58:@4322.4]
+  assign _T_101 = {24'h0,pwm_db,pid_out_sel}; // @[Cat.scala 30:58:@4324.4]
+  assign _T_103 = io_reg_cfg_di[0]; // @[pwm.scala 109:35:@4328.6]
+  assign _T_104 = io_reg_cfg_di[1]; // @[pwm.scala 110:35:@4330.6]
+  assign _T_105 = io_reg_cfg_di[2]; // @[pwm.scala 111:35:@4332.6]
+  assign _T_106 = io_reg_cfg_di[3]; // @[pwm.scala 112:35:@4334.6]
+  assign _T_107 = io_reg_cfg_di[7:4]; // @[pwm.scala 113:36:@4336.6]
+  assign _T_109 = _T_107 + 4'h2; // @[pwm.scala 113:42:@4337.6]
+  assign _T_110 = _T_107 + 4'h2; // @[pwm.scala 113:42:@4338.6]
+  assign _GEN_3 = io_reg_cfg_we ? _T_103 : enable; // @[pwm.scala 108:23:@4327.4]
+  assign _GEN_4 = io_reg_cfg_we ? _T_104 : updown; // @[pwm.scala 108:23:@4327.4]
+  assign _GEN_5 = io_reg_cfg_we ? _T_105 : irq_ena; // @[pwm.scala 108:23:@4327.4]
+  assign _GEN_6 = io_reg_cfg_we ? _T_106 : pid_out_sel; // @[pwm.scala 108:23:@4327.4]
+  assign _GEN_7 = io_reg_cfg_we ? _T_110 : pwm_db; // @[pwm.scala 108:23:@4327.4]
+  assign _GEN_8 = io_reg_val_we ? io_reg_val_di : value_reload; // @[pwm.scala 118:29:@4343.4]
+  assign _T_114 = value_cur + 32'h1; // @[pwm.scala 124:39:@4347.4]
+  assign value_cur_plus = value_cur + 32'h1; // @[pwm.scala 124:39:@4348.4]
+  assign _T_117 = value_cur - 32'h1; // @[pwm.scala 125:39:@4350.4]
+  assign _T_118 = $unsigned(_T_117); // @[pwm.scala 125:39:@4351.4]
+  assign value_cur_minus = _T_118[31:0]; // @[pwm.scala 125:39:@4352.4]
+  assign _T_127 = irq_ena ? _T_95 : 1'h0; // @[pwm.scala 135:23:@4365.8]
+  assign _T_131 = lastenable == 1'h0; // @[pwm.scala 138:25:@4369.10]
+  assign _T_134 = value_cur == value_reload; // @[pwm.scala 143:33:@4375.12]
+  assign _GEN_9 = _T_134 ? 32'h0 : value_cur_plus; // @[pwm.scala 143:58:@4376.12]
+  assign _GEN_11 = _T_131 ? 32'h0 : _GEN_9; // @[pwm.scala 138:38:@4370.10]
+  assign _GEN_12 = _T_131 ? 1'h0 : _T_134; // @[pwm.scala 138:38:@4370.10]
+  assign _T_142 = value_cur == 32'h0; // @[pwm.scala 158:35:@4393.12]
+  assign _GEN_13 = _T_142 ? value_reload : value_cur_minus; // @[pwm.scala 158:50:@4394.12]
+  assign _GEN_15 = _T_131 ? value_reload : _GEN_13; // @[pwm.scala 153:38:@4388.10]
+  assign _GEN_16 = _T_131 ? 1'h0 : _T_142; // @[pwm.scala 153:38:@4388.10]
+  assign _GEN_17 = updown ? _GEN_11 : _GEN_15; // @[pwm.scala 137:31:@4368.8]
+  assign _GEN_18 = updown ? _GEN_12 : _GEN_16; // @[pwm.scala 137:31:@4368.8]
+  assign _GEN_19 = enable ? _T_127 : irq_out; // @[pwm.scala 132:39:@4362.6]
+  assign _GEN_20 = enable ? _GEN_17 : value_cur; // @[pwm.scala 132:39:@4362.6]
+  assign _GEN_21 = enable ? _GEN_18 : stop_out; // @[pwm.scala 132:39:@4362.6]
+  assign _GEN_22 = io_reg_dat_we ? io_reg_dat_di : _GEN_20; // @[pwm.scala 130:29:@4357.4]
+  assign _GEN_23 = io_reg_dat_we ? irq_out : _GEN_19; // @[pwm.scala 130:29:@4357.4]
+  assign _GEN_24 = io_reg_dat_we ? stop_out : _GEN_21; // @[pwm.scala 130:29:@4357.4]
+  assign io_reg_val_do = value_reload; // @[pwm.scala 117:19:@4341.4]
+  assign io_reg_cfg_do = {_T_101,_T_99}; // @[pwm.scala 107:20:@4326.4]
+  assign io_reg_dat_do = value_cur; // @[pwm.scala 123:19:@4346.4]
+  assign io_reg_duty_do = pwm_duty; // @[pwm.scala 75:23:@4270.4]
+  assign io_pwm_h = pwm_hd & enable; // @[pwm.scala 99:20:@4313.4]
+  assign io_pwm_l = pwm_ld & enable; // @[pwm.scala 100:20:@4315.4]
+  assign io_irq_out = irq_out; // @[pwm.scala 103:20:@4316.4]
+  assign io_rawirq_out = stop_out & _T_94; // @[pwm.scala 104:20:@4319.4]
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE
+  integer initvar;
+  initial begin
+    `ifdef INIT_RANDOM
+      `INIT_RANDOM
+    `endif
+    `ifndef VERILATOR
+      #0.002 begin end
+    `endif
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_0 = {1{`RANDOM}};
+  value_cur = _RAND_0[31:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_1 = {1{`RANDOM}};
+  value_reload = _RAND_1[31:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_2 = {1{`RANDOM}};
+  pwm_duty = _RAND_2[31:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_3 = {1{`RANDOM}};
+  reg_duty = _RAND_3[31:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_4 = {1{`RANDOM}};
+  enable = _RAND_4[0:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_5 = {1{`RANDOM}};
+  stop_out = _RAND_5[0:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_6 = {1{`RANDOM}};
+  irq_out = _RAND_6[0:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_7 = {1{`RANDOM}};
+  lastenable = _RAND_7[0:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_8 = {1{`RANDOM}};
+  updown = _RAND_8[0:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_9 = {1{`RANDOM}};
+  irq_ena = _RAND_9[0:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_10 = {1{`RANDOM}};
+  pid_out_sel = _RAND_10[0:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_11 = {1{`RANDOM}};
+  pwm_db = _RAND_11[3:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_12 = {1{`RANDOM}};
+  proc_offset = _RAND_12[31:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_13 = {1{`RANDOM}};
+  pwm_ld = _RAND_13[0:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_14 = {1{`RANDOM}};
+  pwm_hd = _RAND_14[0:0];
+  `endif // RANDOMIZE_REG_INIT
+  end
+`endif // RANDOMIZE
+  always @(posedge clock) begin
+    if (reset) begin
+      value_cur <= 32'h0;
+    end else begin
+      if (io_reg_dat_we) begin
+        value_cur <= io_reg_dat_di;
+      end else begin
+        if (enable) begin
+          if (updown) begin
+            if (_T_131) begin
+              value_cur <= 32'h0;
+            end else begin
+              if (_T_134) begin
+                value_cur <= 32'h0;
+              end else begin
+                value_cur <= value_cur_plus;
+              end
+            end
+          end else begin
+            if (_T_131) begin
+              value_cur <= value_reload;
+            end else begin
+              if (_T_142) begin
+                value_cur <= value_reload;
+              end else begin
+                value_cur <= value_cur_minus;
+              end
+            end
+          end
+        end
+      end
+    end
+    if (reset) begin
+      value_reload <= 32'hff;
+    end else begin
+      if (io_reg_val_we) begin
+        value_reload <= io_reg_val_di;
+      end
+    end
+    if (reset) begin
+      pwm_duty <= 32'h0;
+    end else begin
+      if (stop_out) begin
+        if (pid_out_sel) begin
+          pwm_duty <= {{16'd0}, _T_65};
+        end else begin
+          pwm_duty <= reg_duty;
+        end
+      end
+    end
+    if (reset) begin
+      reg_duty <= 32'h0;
+    end else begin
+      if (io_reg_duty_we) begin
+        reg_duty <= io_reg_duty_di;
+      end
+    end
+    if (reset) begin
+      enable <= 1'h0;
+    end else begin
+      if (io_reg_cfg_we) begin
+        enable <= _T_103;
+      end
+    end
+    if (reset) begin
+      stop_out <= 1'h0;
+    end else begin
+      if (!(io_reg_dat_we)) begin
+        if (enable) begin
+          if (updown) begin
+            if (_T_131) begin
+              stop_out <= 1'h0;
+            end else begin
+              stop_out <= _T_134;
+            end
+          end else begin
+            if (_T_131) begin
+              stop_out <= 1'h0;
+            end else begin
+              stop_out <= _T_142;
+            end
+          end
+        end
+      end
+    end
+    if (reset) begin
+      irq_out <= 1'h0;
+    end else begin
+      if (!(io_reg_dat_we)) begin
+        if (enable) begin
+          if (irq_ena) begin
+            irq_out <= _T_95;
+          end else begin
+            irq_out <= 1'h0;
+          end
+        end
+      end
+    end
+    lastenable <= enable;
+    if (reset) begin
+      updown <= 1'h0;
+    end else begin
+      if (io_reg_cfg_we) begin
+        updown <= _T_104;
+      end
+    end
+    if (reset) begin
+      irq_ena <= 1'h0;
+    end else begin
+      if (io_reg_cfg_we) begin
+        irq_ena <= _T_105;
+      end
+    end
+    if (reset) begin
+      pid_out_sel <= 1'h0;
+    end else begin
+      if (io_reg_cfg_we) begin
+        pid_out_sel <= _T_106;
+      end
+    end
+    if (reset) begin
+      pwm_db <= 4'h2;
+    end else begin
+      if (io_reg_cfg_we) begin
+        pwm_db <= _T_110;
+      end
+    end
+    if (_T_75) begin
+      proc_offset <= pwm_duty;
+    end else begin
+      if (_T_76) begin
+        proc_offset <= {{27'd0}, pwm_db_twice};
+      end else begin
+        proc_offset <= _T_73;
+      end
+    end
+    pwm_ld <= _T_86 & _T_90;
+    pwm_hd <= value_cur < _T_84;
+  end
+endmodule
+module Quad_Encoder( // @[:@4406.2]
+  input         clock, // @[:@4407.4]
+  input         reset, // @[:@4408.4]
+  input         io_quad_a, // @[:@4409.4]
+  input         io_quad_b, // @[:@4409.4]
+  input         io_raw_irq, // @[:@4409.4]
+  input         io_reg_count_we, // @[:@4409.4]
+  input  [31:0] io_reg_count_di, // @[:@4409.4]
+  output [31:0] io_reg_count_do, // @[:@4409.4]
+  input         io_reg_cfg_we, // @[:@4409.4]
+  input  [31:0] io_reg_cfg_di, // @[:@4409.4]
+  output [31:0] io_reg_cfg_do, // @[:@4409.4]
+  output [15:0] io_reg_speed_do, // @[:@4409.4]
+  output        io_fb_period // @[:@4409.4]
+);
+  reg [2:0] quad_a_delayed; // @[qei.scala 35:33:@4411.4]
+  reg [31:0] _RAND_0;
+  reg [2:0] quad_b_delayed; // @[qei.scala 36:33:@4412.4]
+  reg [31:0] _RAND_1;
+  reg [31:0] count_reg; // @[qei.scala 37:33:@4413.4]
+  reg [31:0] _RAND_2;
+  reg [15:0] count_reg_2; // @[qei.scala 38:33:@4414.4]
+  reg [31:0] _RAND_3;
+  reg [15:0] period_count; // @[qei.scala 39:33:@4415.4]
+  reg [31:0] _RAND_4;
+  reg  speed_enable; // @[qei.scala 41:33:@4416.4]
+  reg [31:0] _RAND_5;
+  reg  count_sel_2x; // @[qei.scala 42:33:@4417.4]
+  reg [31:0] _RAND_6;
+  reg [15:0] qei_output; // @[qei.scala 44:33:@4419.4]
+  reg [31:0] _RAND_7;
+  reg [15:0] qei_speed_count; // @[qei.scala 45:33:@4420.4]
+  reg [31:0] _RAND_8;
+  reg [15:0] qei_period_count; // @[qei.scala 46:33:@4421.4]
+  reg [31:0] _RAND_9;
+  reg  period_sel; // @[qei.scala 47:33:@4422.4]
+  reg [31:0] _RAND_10;
+  wire  _T_51; // @[qei.scala 51:44:@4424.4]
+  wire  _T_52; // @[qei.scala 51:63:@4425.4]
+  wire [2:0] _T_54; // @[Cat.scala 30:58:@4427.4]
+  wire  _T_55; // @[qei.scala 52:44:@4429.4]
+  wire  _T_56; // @[qei.scala 52:63:@4430.4]
+  wire [2:0] _T_58; // @[Cat.scala 30:58:@4432.4]
+  wire  _T_61; // @[qei.scala 54:75:@4435.4]
+  wire  count_2x; // @[qei.scala 54:60:@4436.4]
+  wire  _T_68; // @[qei.scala 55:78:@4443.4]
+  wire  _T_69; // @[qei.scala 55:111:@4444.4]
+  wire  count_4x; // @[qei.scala 55:96:@4445.4]
+  wire  count_direction; // @[qei.scala 56:60:@4450.4]
+  wire  count_pulses; // @[qei.scala 57:29:@4453.4]
+  wire [32:0] _T_76; // @[qei.scala 64:36:@4456.8]
+  wire [31:0] _T_77; // @[qei.scala 64:36:@4457.8]
+  wire [32:0] _T_79; // @[qei.scala 66:36:@4461.8]
+  wire [32:0] _T_80; // @[qei.scala 66:36:@4462.8]
+  wire [31:0] _T_81; // @[qei.scala 66:36:@4463.8]
+  wire [31:0] _GEN_0; // @[qei.scala 63:27:@4455.6]
+  wire [31:0] _GEN_1; // @[qei.scala 62:22:@4454.4]
+  wire  _T_82; // @[qei.scala 71:20:@4467.4]
+  wire [16:0] _T_85; // @[qei.scala 76:38:@4474.8]
+  wire [15:0] _T_86; // @[qei.scala 76:38:@4475.8]
+  wire [15:0] _GEN_2; // @[qei.scala 72:23:@4469.6]
+  wire [15:0] _GEN_3; // @[qei.scala 72:23:@4469.6]
+  wire [15:0] _GEN_4; // @[qei.scala 71:37:@4468.4]
+  wire [15:0] _GEN_5; // @[qei.scala 71:37:@4468.4]
+  wire  _T_89; // @[qei.scala 85:29:@4485.8]
+  wire [16:0] _T_92; // @[qei.scala 89:40:@4491.10]
+  wire [15:0] _T_93; // @[qei.scala 89:40:@4492.10]
+  wire [15:0] _GEN_6; // @[qei.scala 85:40:@4486.8]
+  wire [15:0] _GEN_7; // @[qei.scala 85:40:@4486.8]
+  wire [15:0] _GEN_8; // @[qei.scala 82:24:@4480.6]
+  wire [15:0] _GEN_9; // @[qei.scala 82:24:@4480.6]
+  wire [15:0] _GEN_10; // @[qei.scala 81:20:@4479.4]
+  wire [15:0] _GEN_11; // @[qei.scala 81:20:@4479.4]
+  wire [15:0] _T_94; // @[qei.scala 94:30:@4496.4]
+  wire [1:0] _T_96; // @[Cat.scala 30:58:@4498.4]
+  wire [29:0] _T_97; // @[Cat.scala 30:58:@4499.4]
+  wire  _T_101; // @[qei.scala 106:40:@4511.8]
+  wire  _T_102; // @[qei.scala 107:40:@4513.8]
+  wire  _T_103; // @[qei.scala 108:40:@4515.8]
+  wire  _GEN_12; // @[qei.scala 105:28:@4510.6]
+  wire  _GEN_13; // @[qei.scala 105:28:@4510.6]
+  wire  _GEN_14; // @[qei.scala 105:28:@4510.6]
+  wire [31:0] _GEN_15; // @[qei.scala 103:25:@4506.4]
+  wire  _GEN_16; // @[qei.scala 103:25:@4506.4]
+  wire  _GEN_17; // @[qei.scala 103:25:@4506.4]
+  wire  _GEN_18; // @[qei.scala 103:25:@4506.4]
+  assign _T_51 = quad_a_delayed[1]; // @[qei.scala 51:44:@4424.4]
+  assign _T_52 = quad_a_delayed[0]; // @[qei.scala 51:63:@4425.4]
+  assign _T_54 = {_T_51,_T_52,io_quad_a}; // @[Cat.scala 30:58:@4427.4]
+  assign _T_55 = quad_b_delayed[1]; // @[qei.scala 52:44:@4429.4]
+  assign _T_56 = quad_b_delayed[0]; // @[qei.scala 52:63:@4430.4]
+  assign _T_58 = {_T_55,_T_56,io_quad_b}; // @[Cat.scala 30:58:@4432.4]
+  assign _T_61 = quad_a_delayed[2]; // @[qei.scala 54:75:@4435.4]
+  assign count_2x = _T_51 ^ _T_61; // @[qei.scala 54:60:@4436.4]
+  assign _T_68 = count_2x ^ _T_55; // @[qei.scala 55:78:@4443.4]
+  assign _T_69 = quad_b_delayed[2]; // @[qei.scala 55:111:@4444.4]
+  assign count_4x = _T_68 ^ _T_69; // @[qei.scala 55:96:@4445.4]
+  assign count_direction = _T_51 ^ _T_69; // @[qei.scala 56:60:@4450.4]
+  assign count_pulses = count_sel_2x ? count_2x : count_4x; // @[qei.scala 57:29:@4453.4]
+  assign _T_76 = count_reg + 32'h1; // @[qei.scala 64:36:@4456.8]
+  assign _T_77 = count_reg + 32'h1; // @[qei.scala 64:36:@4457.8]
+  assign _T_79 = count_reg - 32'h1; // @[qei.scala 66:36:@4461.8]
+  assign _T_80 = $unsigned(_T_79); // @[qei.scala 66:36:@4462.8]
+  assign _T_81 = _T_80[31:0]; // @[qei.scala 66:36:@4463.8]
+  assign _GEN_0 = count_direction ? _T_77 : _T_81; // @[qei.scala 63:27:@4455.6]
+  assign _GEN_1 = count_pulses ? _GEN_0 : count_reg; // @[qei.scala 62:22:@4454.4]
+  assign _T_82 = io_raw_irq | count_pulses; // @[qei.scala 71:20:@4467.4]
+  assign _T_85 = count_reg_2 + 16'h1; // @[qei.scala 76:38:@4474.8]
+  assign _T_86 = count_reg_2 + 16'h1; // @[qei.scala 76:38:@4475.8]
+  assign _GEN_2 = io_raw_irq ? count_reg_2 : qei_speed_count; // @[qei.scala 72:23:@4469.6]
+  assign _GEN_3 = io_raw_irq ? 16'h0 : _T_86; // @[qei.scala 72:23:@4469.6]
+  assign _GEN_4 = _T_82 ? _GEN_2 : qei_speed_count; // @[qei.scala 71:37:@4468.4]
+  assign _GEN_5 = _T_82 ? _GEN_3 : count_reg_2; // @[qei.scala 71:37:@4468.4]
+  assign _T_89 = period_count == 16'hff; // @[qei.scala 85:29:@4485.8]
+  assign _T_92 = period_count + 16'h1; // @[qei.scala 89:40:@4491.10]
+  assign _T_93 = period_count + 16'h1; // @[qei.scala 89:40:@4492.10]
+  assign _GEN_6 = _T_89 ? period_count : qei_period_count; // @[qei.scala 85:40:@4486.8]
+  assign _GEN_7 = _T_89 ? 16'h0 : _T_93; // @[qei.scala 85:40:@4486.8]
+  assign _GEN_8 = count_pulses ? period_count : _GEN_6; // @[qei.scala 82:24:@4480.6]
+  assign _GEN_9 = count_pulses ? 16'h0 : _GEN_7; // @[qei.scala 82:24:@4480.6]
+  assign _GEN_10 = period_sel ? _GEN_8 : qei_period_count; // @[qei.scala 81:20:@4479.4]
+  assign _GEN_11 = period_sel ? _GEN_9 : period_count; // @[qei.scala 81:20:@4479.4]
+  assign _T_94 = period_sel ? qei_period_count : qei_speed_count; // @[qei.scala 94:30:@4496.4]
+  assign _T_96 = {speed_enable,count_sel_2x}; // @[Cat.scala 30:58:@4498.4]
+  assign _T_97 = {29'h0,period_sel}; // @[Cat.scala 30:58:@4499.4]
+  assign _T_101 = io_reg_cfg_di[0]; // @[qei.scala 106:40:@4511.8]
+  assign _T_102 = io_reg_cfg_di[1]; // @[qei.scala 107:40:@4513.8]
+  assign _T_103 = io_reg_cfg_di[2]; // @[qei.scala 108:40:@4515.8]
+  assign _GEN_12 = io_reg_cfg_we ? _T_101 : count_sel_2x; // @[qei.scala 105:28:@4510.6]
+  assign _GEN_13 = io_reg_cfg_we ? _T_102 : speed_enable; // @[qei.scala 105:28:@4510.6]
+  assign _GEN_14 = io_reg_cfg_we ? _T_103 : period_sel; // @[qei.scala 105:28:@4510.6]
+  assign _GEN_15 = io_reg_count_we ? io_reg_count_di : _GEN_1; // @[qei.scala 103:25:@4506.4]
+  assign _GEN_16 = io_reg_count_we ? count_sel_2x : _GEN_12; // @[qei.scala 103:25:@4506.4]
+  assign _GEN_17 = io_reg_count_we ? speed_enable : _GEN_13; // @[qei.scala 103:25:@4506.4]
+  assign _GEN_18 = io_reg_count_we ? period_sel : _GEN_14; // @[qei.scala 103:25:@4506.4]
+  assign io_reg_count_do = count_reg; // @[qei.scala 49:23:@4423.4]
+  assign io_reg_cfg_do = {_T_97,_T_96}; // @[qei.scala 97:24:@4501.4]
+  assign io_reg_speed_do = $signed(qei_output); // @[qei.scala 100:24:@4504.4]
+  assign io_fb_period = period_sel; // @[qei.scala 101:24:@4505.4]
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE
+  integer initvar;
+  initial begin
+    `ifdef INIT_RANDOM
+      `INIT_RANDOM
+    `endif
+    `ifndef VERILATOR
+      #0.002 begin end
+    `endif
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_0 = {1{`RANDOM}};
+  quad_a_delayed = _RAND_0[2:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_1 = {1{`RANDOM}};
+  quad_b_delayed = _RAND_1[2:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_2 = {1{`RANDOM}};
+  count_reg = _RAND_2[31:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_3 = {1{`RANDOM}};
+  count_reg_2 = _RAND_3[15:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_4 = {1{`RANDOM}};
+  period_count = _RAND_4[15:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_5 = {1{`RANDOM}};
+  speed_enable = _RAND_5[0:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_6 = {1{`RANDOM}};
+  count_sel_2x = _RAND_6[0:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_7 = {1{`RANDOM}};
+  qei_output = _RAND_7[15:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_8 = {1{`RANDOM}};
+  qei_speed_count = _RAND_8[15:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_9 = {1{`RANDOM}};
+  qei_period_count = _RAND_9[15:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_10 = {1{`RANDOM}};
+  period_sel = _RAND_10[0:0];
+  `endif // RANDOMIZE_REG_INIT
+  end
+`endif // RANDOMIZE
+  always @(posedge clock) begin
+    if (reset) begin
+      quad_a_delayed <= 3'h0;
+    end else begin
+      quad_a_delayed <= _T_54;
+    end
+    if (reset) begin
+      quad_b_delayed <= 3'h0;
+    end else begin
+      quad_b_delayed <= _T_58;
+    end
+    if (reset) begin
+      count_reg <= 32'h0;
+    end else begin
+      if (io_reg_count_we) begin
+        count_reg <= io_reg_count_di;
+      end else begin
+        if (count_pulses) begin
+          if (count_direction) begin
+            count_reg <= _T_77;
+          end else begin
+            count_reg <= _T_81;
+          end
+        end
+      end
+    end
+    if (reset) begin
+      count_reg_2 <= 16'h0;
+    end else begin
+      if (_T_82) begin
+        if (io_raw_irq) begin
+          count_reg_2 <= 16'h0;
+        end else begin
+          count_reg_2 <= _T_86;
+        end
+      end
+    end
+    if (reset) begin
+      period_count <= 16'h0;
+    end else begin
+      if (period_sel) begin
+        if (count_pulses) begin
+          period_count <= 16'h0;
+        end else begin
+          if (_T_89) begin
+            period_count <= 16'h0;
+          end else begin
+            period_count <= _T_93;
+          end
+        end
+      end
+    end
+    if (reset) begin
+      speed_enable <= 1'h1;
+    end else begin
+      if (!(io_reg_count_we)) begin
+        if (io_reg_cfg_we) begin
+          speed_enable <= _T_102;
+        end
+      end
+    end
+    if (reset) begin
+      count_sel_2x <= 1'h1;
+    end else begin
+      if (!(io_reg_count_we)) begin
+        if (io_reg_cfg_we) begin
+          count_sel_2x <= _T_101;
+        end
+      end
+    end
+    if (reset) begin
+      qei_output <= 16'h0;
+    end else begin
+      if (period_sel) begin
+        qei_output <= qei_period_count;
+      end else begin
+        qei_output <= qei_speed_count;
+      end
+    end
+    if (reset) begin
+      qei_speed_count <= 16'h0;
+    end else begin
+      if (_T_82) begin
+        if (io_raw_irq) begin
+          qei_speed_count <= count_reg_2;
+        end
+      end
+    end
+    if (reset) begin
+      qei_period_count <= 16'h1fff;
+    end else begin
+      if (period_sel) begin
+        if (count_pulses) begin
+          qei_period_count <= period_count;
+        end else begin
+          if (_T_89) begin
+            qei_period_count <= period_count;
+          end
+        end
+      end
+    end
+    if (reset) begin
+      period_sel <= 1'h0;
+    end else begin
+      if (!(io_reg_count_we)) begin
+        if (io_reg_cfg_we) begin
+          period_sel <= _T_103;
+        end
+      end
+    end
+  end
+endmodule
+module vedic_2x2( // @[:@4519.2]
+  input  [1:0] io_a, // @[:@4522.4]
+  input  [1:0] io_b, // @[:@4522.4]
+  output [3:0] io_c // @[:@4522.4]
+);
+  wire  _T_11; // @[multiplier.scala 25:21:@4524.4]
+  wire  _T_12; // @[multiplier.scala 25:31:@4525.4]
+  wire  result0; // @[multiplier.scala 25:25:@4526.4]
+  wire  _T_13; // @[multiplier.scala 26:21:@4527.4]
+  wire  temp0; // @[multiplier.scala 26:25:@4529.4]
+  wire  _T_16; // @[multiplier.scala 27:31:@4531.4]
+  wire  temp1; // @[multiplier.scala 27:25:@4532.4]
+  wire  temp2; // @[multiplier.scala 28:25:@4535.4]
+  wire  result1; // @[multiplier.scala 31:23:@4536.4]
+  wire  temp3; // @[multiplier.scala 32:23:@4537.4]
+  wire  result2; // @[multiplier.scala 34:23:@4538.4]
+  wire  result3; // @[multiplier.scala 35:23:@4539.4]
+  wire [1:0] _T_19; // @[Cat.scala 30:58:@4540.4]
+  wire [1:0] _T_20; // @[Cat.scala 30:58:@4541.4]
+  assign _T_11 = io_a[0]; // @[multiplier.scala 25:21:@4524.4]
+  assign _T_12 = io_b[0]; // @[multiplier.scala 25:31:@4525.4]
+  assign result0 = _T_11 & _T_12; // @[multiplier.scala 25:25:@4526.4]
+  assign _T_13 = io_a[1]; // @[multiplier.scala 26:21:@4527.4]
+  assign temp0 = _T_13 & _T_12; // @[multiplier.scala 26:25:@4529.4]
+  assign _T_16 = io_b[1]; // @[multiplier.scala 27:31:@4531.4]
+  assign temp1 = _T_11 & _T_16; // @[multiplier.scala 27:25:@4532.4]
+  assign temp2 = _T_13 & _T_16; // @[multiplier.scala 28:25:@4535.4]
+  assign result1 = temp0 ^ temp1; // @[multiplier.scala 31:23:@4536.4]
+  assign temp3 = temp0 & temp1; // @[multiplier.scala 32:23:@4537.4]
+  assign result2 = temp2 ^ temp3; // @[multiplier.scala 34:23:@4538.4]
+  assign result3 = temp2 & temp3; // @[multiplier.scala 35:23:@4539.4]
+  assign _T_19 = {result1,result0}; // @[Cat.scala 30:58:@4540.4]
+  assign _T_20 = {result3,result2}; // @[Cat.scala 30:58:@4541.4]
+  assign io_c = {_T_20,_T_19}; // @[multiplier.scala 37:15:@4543.4]
+endmodule
+module vedic_4x4( // @[:@4623.2]
+  input  [3:0] io_a, // @[:@4626.4]
+  input  [3:0] io_b, // @[:@4626.4]
+  output [7:0] io_c // @[:@4626.4]
+);
+  wire [1:0] z1_io_a; // @[multiplier.scala 64:23:@4639.4]
+  wire [1:0] z1_io_b; // @[multiplier.scala 64:23:@4639.4]
+  wire [3:0] z1_io_c; // @[multiplier.scala 64:23:@4639.4]
+  wire [1:0] z2_io_a; // @[multiplier.scala 69:23:@4647.4]
+  wire [1:0] z2_io_b; // @[multiplier.scala 69:23:@4647.4]
+  wire [3:0] z2_io_c; // @[multiplier.scala 69:23:@4647.4]
+  wire [1:0] z3_io_a; // @[multiplier.scala 73:23:@4655.4]
+  wire [1:0] z3_io_b; // @[multiplier.scala 73:23:@4655.4]
+  wire [3:0] z3_io_c; // @[multiplier.scala 73:23:@4655.4]
+  wire [1:0] z4_io_a; // @[multiplier.scala 78:23:@4663.4]
+  wire [1:0] z4_io_b; // @[multiplier.scala 78:23:@4663.4]
+  wire [3:0] z4_io_c; // @[multiplier.scala 78:23:@4663.4]
+  wire [3:0] q0; // @[multiplier.scala 49:21:@4628.4 multiplier.scala 67:15:@4646.4]
+  wire [1:0] _T_31; // @[multiplier.scala 83:37:@4671.4]
+  wire [3:0] temp1; // @[Cat.scala 30:58:@4672.4]
+  wire [3:0] q1; // @[multiplier.scala 50:21:@4629.4 multiplier.scala 72:15:@4654.4]
+  wire [4:0] _T_34; // @[multiplier.scala 84:26:@4675.4]
+  wire [3:0] q4; // @[multiplier.scala 84:26:@4676.4]
+  wire [3:0] q2; // @[multiplier.scala 51:21:@4630.4 multiplier.scala 76:15:@4662.4]
+  wire [5:0] temp2; // @[Cat.scala 30:58:@4679.4]
+  wire [3:0] q3; // @[multiplier.scala 52:21:@4631.4 multiplier.scala 81:15:@4670.4]
+  wire [5:0] temp3; // @[Cat.scala 30:58:@4682.4]
+  wire [6:0] _T_42; // @[multiplier.scala 87:24:@4684.4]
+  wire [5:0] q5; // @[multiplier.scala 87:24:@4685.4]
+  wire [5:0] temp4; // @[Cat.scala 30:58:@4688.4]
+  wire [6:0] _T_47; // @[multiplier.scala 89:24:@4690.4]
+  wire [5:0] q6; // @[multiplier.scala 89:24:@4691.4]
+  wire [1:0] result1; // @[multiplier.scala 91:19:@4693.4]
+  vedic_2x2 z1 ( // @[multiplier.scala 64:23:@4639.4]
+    .io_a(z1_io_a),
+    .io_b(z1_io_b),
+    .io_c(z1_io_c)
+  );
+  vedic_2x2 z2 ( // @[multiplier.scala 69:23:@4647.4]
+    .io_a(z2_io_a),
+    .io_b(z2_io_b),
+    .io_c(z2_io_c)
+  );
+  vedic_2x2 z3 ( // @[multiplier.scala 73:23:@4655.4]
+    .io_a(z3_io_a),
+    .io_b(z3_io_b),
+    .io_c(z3_io_c)
+  );
+  vedic_2x2 z4 ( // @[multiplier.scala 78:23:@4663.4]
+    .io_a(z4_io_a),
+    .io_b(z4_io_b),
+    .io_c(z4_io_c)
+  );
+  assign q0 = z1_io_c; // @[multiplier.scala 49:21:@4628.4 multiplier.scala 67:15:@4646.4]
+  assign _T_31 = q0[3:2]; // @[multiplier.scala 83:37:@4671.4]
+  assign temp1 = {2'h0,_T_31}; // @[Cat.scala 30:58:@4672.4]
+  assign q1 = z2_io_c; // @[multiplier.scala 50:21:@4629.4 multiplier.scala 72:15:@4654.4]
+  assign _T_34 = q1 + temp1; // @[multiplier.scala 84:26:@4675.4]
+  assign q4 = q1 + temp1; // @[multiplier.scala 84:26:@4676.4]
+  assign q2 = z3_io_c; // @[multiplier.scala 51:21:@4630.4 multiplier.scala 76:15:@4662.4]
+  assign temp2 = {2'h0,q2}; // @[Cat.scala 30:58:@4679.4]
+  assign q3 = z4_io_c; // @[multiplier.scala 52:21:@4631.4 multiplier.scala 81:15:@4670.4]
+  assign temp3 = {q3,2'h0}; // @[Cat.scala 30:58:@4682.4]
+  assign _T_42 = temp2 + temp3; // @[multiplier.scala 87:24:@4684.4]
+  assign q5 = temp2 + temp3; // @[multiplier.scala 87:24:@4685.4]
+  assign temp4 = {2'h0,q4}; // @[Cat.scala 30:58:@4688.4]
+  assign _T_47 = temp4 + q5; // @[multiplier.scala 89:24:@4690.4]
+  assign q6 = temp4 + q5; // @[multiplier.scala 89:24:@4691.4]
+  assign result1 = q0[1:0]; // @[multiplier.scala 91:19:@4693.4]
+  assign io_c = {q6,result1}; // @[multiplier.scala 94:15:@4696.4]
+  assign z1_io_a = io_a[1:0]; // @[multiplier.scala 65:15:@4643.4]
+  assign z1_io_b = io_b[1:0]; // @[multiplier.scala 66:15:@4645.4]
+  assign z2_io_a = io_a[3:2]; // @[multiplier.scala 70:15:@4651.4]
+  assign z2_io_b = io_b[1:0]; // @[multiplier.scala 71:15:@4653.4]
+  assign z3_io_a = io_a[1:0]; // @[multiplier.scala 74:15:@4659.4]
+  assign z3_io_b = io_b[3:2]; // @[multiplier.scala 75:15:@4661.4]
+  assign z4_io_a = io_a[3:2]; // @[multiplier.scala 79:15:@4667.4]
+  assign z4_io_b = io_b[3:2]; // @[multiplier.scala 80:15:@4669.4]
+endmodule
+module vedic_8x8( // @[:@5235.2]
+  input  [7:0]  io_a, // @[:@5238.4]
+  input  [7:0]  io_b, // @[:@5238.4]
+  output [15:0] io_c // @[:@5238.4]
+);
+  wire [3:0] z1_io_a; // @[multiplier.scala 188:22:@5252.4]
+  wire [3:0] z1_io_b; // @[multiplier.scala 188:22:@5252.4]
+  wire [7:0] z1_io_c; // @[multiplier.scala 188:22:@5252.4]
+  wire [3:0] z2_io_a; // @[multiplier.scala 193:22:@5260.4]
+  wire [3:0] z2_io_b; // @[multiplier.scala 193:22:@5260.4]
+  wire [7:0] z2_io_c; // @[multiplier.scala 193:22:@5260.4]
+  wire [3:0] z3_io_a; // @[multiplier.scala 198:22:@5268.4]
+  wire [3:0] z3_io_b; // @[multiplier.scala 198:22:@5268.4]
+  wire [7:0] z3_io_c; // @[multiplier.scala 198:22:@5268.4]
+  wire [3:0] z4_io_a; // @[multiplier.scala 203:22:@5276.4]
+  wire [3:0] z4_io_b; // @[multiplier.scala 203:22:@5276.4]
+  wire [7:0] z4_io_c; // @[multiplier.scala 203:22:@5276.4]
+  wire [15:0] q0; // @[multiplier.scala 171:20:@5240.4 multiplier.scala 191:14:@5259.4]
+  wire [3:0] _T_31; // @[multiplier.scala 210:36:@5284.4]
+  wire [7:0] temp1; // @[Cat.scala 30:58:@5285.4]
+  wire [15:0] q1; // @[multiplier.scala 172:20:@5241.4 multiplier.scala 196:14:@5267.4]
+  wire [7:0] _T_33; // @[multiplier.scala 211:19:@5287.4]
+  wire [8:0] _T_34; // @[multiplier.scala 211:25:@5288.4]
+  wire [7:0] q4; // @[multiplier.scala 211:25:@5289.4]
+  wire [15:0] q2; // @[multiplier.scala 173:20:@5242.4 multiplier.scala 201:14:@5275.4]
+  wire [7:0] _T_37; // @[multiplier.scala 212:36:@5291.4]
+  wire [11:0] temp2; // @[Cat.scala 30:58:@5292.4]
+  wire [15:0] q3; // @[multiplier.scala 174:20:@5243.4 multiplier.scala 206:14:@5283.4]
+  wire [7:0] _T_39; // @[multiplier.scala 213:23:@5294.4]
+  wire [11:0] temp3; // @[Cat.scala 30:58:@5295.4]
+  wire [12:0] _T_42; // @[multiplier.scala 214:23:@5297.4]
+  wire [11:0] q5; // @[multiplier.scala 214:23:@5298.4]
+  wire [11:0] temp4; // @[Cat.scala 30:58:@5301.4]
+  wire [12:0] _T_47; // @[multiplier.scala 218:23:@5303.4]
+  wire [11:0] q6; // @[multiplier.scala 218:23:@5304.4]
+  wire [3:0] result1; // @[multiplier.scala 220:19:@5306.4]
+  vedic_4x4 z1 ( // @[multiplier.scala 188:22:@5252.4]
+    .io_a(z1_io_a),
+    .io_b(z1_io_b),
+    .io_c(z1_io_c)
+  );
+  vedic_4x4 z2 ( // @[multiplier.scala 193:22:@5260.4]
+    .io_a(z2_io_a),
+    .io_b(z2_io_b),
+    .io_c(z2_io_c)
+  );
+  vedic_4x4 z3 ( // @[multiplier.scala 198:22:@5268.4]
+    .io_a(z3_io_a),
+    .io_b(z3_io_b),
+    .io_c(z3_io_c)
+  );
+  vedic_4x4 z4 ( // @[multiplier.scala 203:22:@5276.4]
+    .io_a(z4_io_a),
+    .io_b(z4_io_b),
+    .io_c(z4_io_c)
+  );
+  assign q0 = {{8'd0}, z1_io_c}; // @[multiplier.scala 171:20:@5240.4 multiplier.scala 191:14:@5259.4]
+  assign _T_31 = q0[7:4]; // @[multiplier.scala 210:36:@5284.4]
+  assign temp1 = {4'h0,_T_31}; // @[Cat.scala 30:58:@5285.4]
+  assign q1 = {{8'd0}, z2_io_c}; // @[multiplier.scala 172:20:@5241.4 multiplier.scala 196:14:@5267.4]
+  assign _T_33 = q1[7:0]; // @[multiplier.scala 211:19:@5287.4]
+  assign _T_34 = _T_33 + temp1; // @[multiplier.scala 211:25:@5288.4]
+  assign q4 = _T_33 + temp1; // @[multiplier.scala 211:25:@5289.4]
+  assign q2 = {{8'd0}, z3_io_c}; // @[multiplier.scala 173:20:@5242.4 multiplier.scala 201:14:@5275.4]
+  assign _T_37 = q2[7:0]; // @[multiplier.scala 212:36:@5291.4]
+  assign temp2 = {4'h0,_T_37}; // @[Cat.scala 30:58:@5292.4]
+  assign q3 = {{8'd0}, z4_io_c}; // @[multiplier.scala 174:20:@5243.4 multiplier.scala 206:14:@5283.4]
+  assign _T_39 = q3[7:0]; // @[multiplier.scala 213:23:@5294.4]
+  assign temp3 = {_T_39,4'h0}; // @[Cat.scala 30:58:@5295.4]
+  assign _T_42 = temp2 + temp3; // @[multiplier.scala 214:23:@5297.4]
+  assign q5 = temp2 + temp3; // @[multiplier.scala 214:23:@5298.4]
+  assign temp4 = {4'h0,q4}; // @[Cat.scala 30:58:@5301.4]
+  assign _T_47 = temp4 + q5; // @[multiplier.scala 218:23:@5303.4]
+  assign q6 = temp4 + q5; // @[multiplier.scala 218:23:@5304.4]
+  assign result1 = q0[3:0]; // @[multiplier.scala 220:19:@5306.4]
+  assign io_c = {q6,result1}; // @[multiplier.scala 224:15:@5309.4]
+  assign z1_io_a = io_a[3:0]; // @[multiplier.scala 189:14:@5256.4]
+  assign z1_io_b = io_b[3:0]; // @[multiplier.scala 190:14:@5258.4]
+  assign z2_io_a = io_a[7:4]; // @[multiplier.scala 194:14:@5264.4]
+  assign z2_io_b = io_b[3:0]; // @[multiplier.scala 195:14:@5266.4]
+  assign z3_io_a = io_a[3:0]; // @[multiplier.scala 199:14:@5272.4]
+  assign z3_io_b = io_b[7:4]; // @[multiplier.scala 200:14:@5274.4]
+  assign z4_io_a = io_a[7:4]; // @[multiplier.scala 204:14:@5280.4]
+  assign z4_io_b = io_b[7:4]; // @[multiplier.scala 205:14:@5282.4]
+endmodule
+module vedic_16x16( // @[:@7074.2]
+  input  [15:0] io_a, // @[:@7077.4]
+  input  [15:0] io_b, // @[:@7077.4]
+  output [31:0] io_c // @[:@7077.4]
+);
+  wire [7:0] z1_io_a; // @[multiplier.scala 254:30:@7099.4]
+  wire [7:0] z1_io_b; // @[multiplier.scala 254:30:@7099.4]
+  wire [15:0] z1_io_c; // @[multiplier.scala 254:30:@7099.4]
+  wire [7:0] z2_io_a; // @[multiplier.scala 259:30:@7107.4]
+  wire [7:0] z2_io_b; // @[multiplier.scala 259:30:@7107.4]
+  wire [15:0] z2_io_c; // @[multiplier.scala 259:30:@7107.4]
+  wire [7:0] z3_io_a; // @[multiplier.scala 264:30:@7115.4]
+  wire [7:0] z3_io_b; // @[multiplier.scala 264:30:@7115.4]
+  wire [15:0] z3_io_c; // @[multiplier.scala 264:30:@7115.4]
+  wire [3:0] z4_io_a; // @[multiplier.scala 269:30:@7123.4]
+  wire [3:0] z4_io_b; // @[multiplier.scala 269:30:@7123.4]
+  wire [7:0] z4_io_c; // @[multiplier.scala 269:30:@7123.4]
+  wire [15:0] _T_22; // @[multiplier.scala 250:25:@7090.4]
+  wire [15:0] _T_23; // @[multiplier.scala 250:25:@7091.4]
+  wire [15:0] _T_24; // @[multiplier.scala 250:38:@7092.4]
+  wire [16:0] _T_26; // @[multiplier.scala 250:41:@7093.4]
+  wire [15:0] in1_complement; // @[multiplier.scala 250:41:@7094.4]
+  wire  _T_27; // @[multiplier.scala 251:32:@7095.4]
+  wire [15:0] _T_29; // @[multiplier.scala 251:64:@7097.4]
+  wire [15:0] input1; // @[multiplier.scala 251:27:@7098.4]
+  wire [7:0] _T_32; // @[multiplier.scala 260:31:@7110.4]
+  wire [7:0] _T_35; // @[multiplier.scala 266:29:@7120.4]
+  wire [15:0] q0; // @[multiplier.scala 236:28:@7079.4 multiplier.scala 257:22:@7106.4]
+  wire [7:0] _T_39; // @[multiplier.scala 275:44:@7131.4]
+  wire [15:0] _T_40; // @[Cat.scala 30:58:@7132.4]
+  wire [15:0] q1; // @[multiplier.scala 237:28:@7080.4 multiplier.scala 262:22:@7114.4]
+  wire [17:0] temp1; // @[multiplier.scala 241:28:@7083.4 multiplier.scala 275:22:@7133.4]
+  wire [17:0] _GEN_0; // @[multiplier.scala 276:34:@7135.4]
+  wire [18:0] _T_42; // @[multiplier.scala 276:34:@7135.4]
+  wire [17:0] _T_43; // @[multiplier.scala 276:34:@7136.4]
+  wire [15:0] q2; // @[multiplier.scala 238:28:@7081.4 multiplier.scala 267:22:@7122.4]
+  wire [23:0] temp2; // @[Cat.scala 30:58:@7139.4]
+  wire [15:0] q3; // @[multiplier.scala 239:28:@7082.4 multiplier.scala 272:22:@7130.4]
+  wire [23:0] temp3; // @[Cat.scala 30:58:@7142.4]
+  wire [24:0] _T_50; // @[multiplier.scala 279:31:@7144.4]
+  wire [23:0] q5; // @[multiplier.scala 279:31:@7145.4]
+  wire [15:0] q4; // @[multiplier.scala 246:28:@7087.4 multiplier.scala 276:22:@7137.4]
+  wire [23:0] temp4; // @[Cat.scala 30:58:@7148.4]
+  wire [24:0] _T_55; // @[multiplier.scala 281:31:@7150.4]
+  wire [23:0] q6; // @[multiplier.scala 281:31:@7151.4]
+  wire [7:0] result1; // @[multiplier.scala 283:26:@7153.4]
+  wire [31:0] result; // @[Cat.scala 30:58:@7155.4]
+  wire [31:0] _T_57; // @[multiplier.scala 286:28:@7156.4]
+  wire [31:0] _T_58; // @[multiplier.scala 286:43:@7157.4]
+  wire [32:0] _T_60; // @[multiplier.scala 286:46:@7158.4]
+  wire [31:0] _T_61; // @[multiplier.scala 286:46:@7159.4]
+  wire [31:0] result_complement; // @[multiplier.scala 286:46:@7160.4]
+  wire [31:0] _T_63; // @[multiplier.scala 288:70:@7162.4]
+  vedic_8x8 z1 ( // @[multiplier.scala 254:30:@7099.4]
+    .io_a(z1_io_a),
+    .io_b(z1_io_b),
+    .io_c(z1_io_c)
+  );
+  vedic_8x8 z2 ( // @[multiplier.scala 259:30:@7107.4]
+    .io_a(z2_io_a),
+    .io_b(z2_io_b),
+    .io_c(z2_io_c)
+  );
+  vedic_8x8 z3 ( // @[multiplier.scala 264:30:@7115.4]
+    .io_a(z3_io_a),
+    .io_b(z3_io_b),
+    .io_c(z3_io_c)
+  );
+  vedic_4x4 z4 ( // @[multiplier.scala 269:30:@7123.4]
+    .io_a(z4_io_a),
+    .io_b(z4_io_b),
+    .io_c(z4_io_c)
+  );
+  assign _T_22 = ~ io_a; // @[multiplier.scala 250:25:@7090.4]
+  assign _T_23 = $signed(_T_22); // @[multiplier.scala 250:25:@7091.4]
+  assign _T_24 = $unsigned(_T_23); // @[multiplier.scala 250:38:@7092.4]
+  assign _T_26 = _T_24 + 16'h1; // @[multiplier.scala 250:41:@7093.4]
+  assign in1_complement = _T_24 + 16'h1; // @[multiplier.scala 250:41:@7094.4]
+  assign _T_27 = io_a[15]; // @[multiplier.scala 251:32:@7095.4]
+  assign _T_29 = $unsigned(io_a); // @[multiplier.scala 251:64:@7097.4]
+  assign input1 = _T_27 ? in1_complement : _T_29; // @[multiplier.scala 251:27:@7098.4]
+  assign _T_32 = input1[15:8]; // @[multiplier.scala 260:31:@7110.4]
+  assign _T_35 = io_b[15:8]; // @[multiplier.scala 266:29:@7120.4]
+  assign q0 = z1_io_c; // @[multiplier.scala 236:28:@7079.4 multiplier.scala 257:22:@7106.4]
+  assign _T_39 = q0[15:8]; // @[multiplier.scala 275:44:@7131.4]
+  assign _T_40 = {8'h0,_T_39}; // @[Cat.scala 30:58:@7132.4]
+  assign q1 = z2_io_c; // @[multiplier.scala 237:28:@7080.4 multiplier.scala 262:22:@7114.4]
+  assign temp1 = {{2'd0}, _T_40}; // @[multiplier.scala 241:28:@7083.4 multiplier.scala 275:22:@7133.4]
+  assign _GEN_0 = {{2'd0}, q1}; // @[multiplier.scala 276:34:@7135.4]
+  assign _T_42 = _GEN_0 + temp1; // @[multiplier.scala 276:34:@7135.4]
+  assign _T_43 = _GEN_0 + temp1; // @[multiplier.scala 276:34:@7136.4]
+  assign q2 = z3_io_c; // @[multiplier.scala 238:28:@7081.4 multiplier.scala 267:22:@7122.4]
+  assign temp2 = {8'h0,q2}; // @[Cat.scala 30:58:@7139.4]
+  assign q3 = {{8'd0}, z4_io_c}; // @[multiplier.scala 239:28:@7082.4 multiplier.scala 272:22:@7130.4]
+  assign temp3 = {q3,8'h0}; // @[Cat.scala 30:58:@7142.4]
+  assign _T_50 = temp2 + temp3; // @[multiplier.scala 279:31:@7144.4]
+  assign q5 = temp2 + temp3; // @[multiplier.scala 279:31:@7145.4]
+  assign q4 = _T_43[15:0]; // @[multiplier.scala 246:28:@7087.4 multiplier.scala 276:22:@7137.4]
+  assign temp4 = {8'h0,q4}; // @[Cat.scala 30:58:@7148.4]
+  assign _T_55 = temp4 + q5; // @[multiplier.scala 281:31:@7150.4]
+  assign q6 = temp4 + q5; // @[multiplier.scala 281:31:@7151.4]
+  assign result1 = q0[7:0]; // @[multiplier.scala 283:26:@7153.4]
+  assign result = {q6,result1}; // @[Cat.scala 30:58:@7155.4]
+  assign _T_57 = ~ result; // @[multiplier.scala 286:28:@7156.4]
+  assign _T_58 = $signed(_T_57); // @[multiplier.scala 286:43:@7157.4]
+  assign _T_60 = $signed(_T_58) + $signed(32'sh1); // @[multiplier.scala 286:46:@7158.4]
+  assign _T_61 = $signed(_T_58) + $signed(32'sh1); // @[multiplier.scala 286:46:@7159.4]
+  assign result_complement = $signed(_T_61); // @[multiplier.scala 286:46:@7160.4]
+  assign _T_63 = $signed(result); // @[multiplier.scala 288:70:@7162.4]
+  assign io_c = _T_27 ? $signed(result_complement) : $signed(_T_63); // @[multiplier.scala 289:22:@7164.4]
+  assign z1_io_a = input1[7:0]; // @[multiplier.scala 255:22:@7103.4]
+  assign z1_io_b = io_b[7:0]; // @[multiplier.scala 256:22:@7105.4]
+  assign z2_io_a = input1[15:8]; // @[multiplier.scala 260:22:@7111.4]
+  assign z2_io_b = io_b[7:0]; // @[multiplier.scala 261:22:@7113.4]
+  assign z3_io_a = input1[7:0]; // @[multiplier.scala 265:22:@7119.4]
+  assign z3_io_b = io_b[15:8]; // @[multiplier.scala 266:22:@7121.4]
+  assign z4_io_a = _T_32[3:0]; // @[multiplier.scala 270:22:@7127.4]
+  assign z4_io_b = _T_35[3:0]; // @[multiplier.scala 271:22:@7129.4]
+endmodule
+module PID_Controller( // @[:@12460.2]
+  input         clock, // @[:@12461.4]
+  input         reset, // @[:@12462.4]
+  input         io_fb_period, // @[:@12463.4]
+  input         io_raw_irq, // @[:@12463.4]
+  input         io_reg_kp_we, // @[:@12463.4]
+  input  [15:0] io_reg_kp_di, // @[:@12463.4]
+  output [15:0] io_reg_kp_do, // @[:@12463.4]
+  input         io_reg_ki_we, // @[:@12463.4]
+  input  [15:0] io_reg_ki_di, // @[:@12463.4]
+  output [15:0] io_reg_ki_do, // @[:@12463.4]
+  input         io_reg_kd_we, // @[:@12463.4]
+  input  [15:0] io_reg_kd_di, // @[:@12463.4]
+  output [15:0] io_reg_kd_do, // @[:@12463.4]
+  input         io_reg_ref_we, // @[:@12463.4]
+  input  [15:0] io_reg_ref_di, // @[:@12463.4]
+  output [15:0] io_reg_ref_do, // @[:@12463.4]
+  input         io_reg_fb_we, // @[:@12463.4]
+  input  [15:0] io_reg_fb_di, // @[:@12463.4]
+  output [15:0] io_reg_fb_do, // @[:@12463.4]
+  input         io_reg_cfg_we, // @[:@12463.4]
+  input  [15:0] io_reg_cfg_di, // @[:@12463.4]
+  output [15:0] io_reg_cfg_do, // @[:@12463.4]
+  input  [15:0] io_speed_fb_in, // @[:@12463.4]
+  output [15:0] io_pid_out // @[:@12463.4]
+);
+  wire [15:0] mul_kp_io_a; // @[pid.scala 110:25:@12513.4]
+  wire [15:0] mul_kp_io_b; // @[pid.scala 110:25:@12513.4]
+  wire [31:0] mul_kp_io_c; // @[pid.scala 110:25:@12513.4]
+  wire [15:0] mul_ki_io_a; // @[pid.scala 116:25:@12521.4]
+  wire [15:0] mul_ki_io_b; // @[pid.scala 116:25:@12521.4]
+  wire [31:0] mul_ki_io_c; // @[pid.scala 116:25:@12521.4]
+  wire [15:0] mul_kd_io_a; // @[pid.scala 122:25:@12529.4]
+  wire [15:0] mul_kd_io_b; // @[pid.scala 122:25:@12529.4]
+  wire [31:0] mul_kd_io_c; // @[pid.scala 122:25:@12529.4]
+  reg [15:0] kp; // @[pid.scala 56:26:@12465.4]
+  reg [31:0] _RAND_0;
+  reg [15:0] ki; // @[pid.scala 57:26:@12466.4]
+  reg [31:0] _RAND_1;
+  reg [15:0] kd; // @[pid.scala 58:26:@12467.4]
+  reg [31:0] _RAND_2;
+  reg [15:0] ref$; // @[pid.scala 59:26:@12468.4]
+  reg [31:0] _RAND_3;
+  reg [15:0] feedback; // @[pid.scala 60:26:@12469.4]
+  reg [31:0] _RAND_4;
+  reg [15:0] sigma_old; // @[pid.scala 61:26:@12470.4]
+  reg [31:0] _RAND_5;
+  reg  fb_sel; // @[pid.scala 62:26:@12471.4]
+  reg [31:0] _RAND_6;
+  reg [15:0] e_prev1; // @[pid.scala 64:26:@12472.4]
+  reg [31:0] _RAND_7;
+  reg [15:0] e_prev2; // @[pid.scala 65:26:@12473.4]
+  reg [31:0] _RAND_8;
+  reg [15:0] reg_pid_out; // @[pid.scala 66:28:@12474.4]
+  reg [31:0] _RAND_9;
+  wire [15:0] _GEN_0; // @[pid.scala 70:22:@12476.4]
+  wire [15:0] _GEN_1; // @[pid.scala 75:22:@12480.4]
+  wire [15:0] _GEN_2; // @[pid.scala 80:22:@12484.4]
+  wire [15:0] _GEN_3; // @[pid.scala 86:23:@12488.4]
+  wire [15:0] _GEN_4; // @[pid.scala 93:24:@12493.6]
+  wire [15:0] _GEN_5; // @[pid.scala 92:16:@12492.4]
+  wire [31:0] _T_70; // @[Cat.scala 30:58:@12500.4]
+  wire [31:0] _T_71; // @[pid.scala 100:49:@12501.4]
+  wire  _T_72; // @[pid.scala 102:28:@12504.6]
+  wire  _GEN_6; // @[pid.scala 101:23:@12503.4]
+  wire [16:0] _T_73; // @[pid.scala 106:27:@12507.4]
+  wire [15:0] _T_74; // @[pid.scala 106:27:@12508.4]
+  wire [16:0] _T_75; // @[pid.scala 107:27:@12510.4]
+  wire [15:0] _T_76; // @[pid.scala 107:27:@12511.4]
+  wire [15:0] sigma_new; // @[pid.scala 107:27:@12512.4]
+  wire [15:0] _T_78; // @[pid.scala 113:30:@12519.4]
+  wire [15:0] prop_out; // @[pid.scala 113:43:@12520.4]
+  wire [15:0] _T_80; // @[pid.scala 119:33:@12527.4]
+  wire [15:0] integral_out; // @[pid.scala 119:46:@12528.4]
+  wire [15:0] _T_82; // @[pid.scala 125:35:@12535.4]
+  wire [15:0] derivative_out; // @[pid.scala 125:48:@12536.4]
+  wire [16:0] _T_83; // @[pid.scala 128:28:@12537.4]
+  wire [15:0] _T_84; // @[pid.scala 128:28:@12538.4]
+  wire [15:0] pi_sum; // @[pid.scala 128:28:@12539.4]
+  wire  _T_85; // @[pid.scala 129:34:@12540.4]
+  wire  _T_86; // @[pid.scala 129:54:@12541.4]
+  wire  _T_87; // @[pid.scala 129:39:@12542.4]
+  wire  _T_88; // @[pid.scala 129:69:@12543.4]
+  wire  _T_90; // @[pid.scala 129:62:@12544.4]
+  wire  _T_91; // @[pid.scala 129:59:@12545.4]
+  wire  _T_94; // @[pid.scala 130:26:@12547.4]
+  wire  _T_97; // @[pid.scala 130:43:@12549.4]
+  wire  _T_98; // @[pid.scala 130:40:@12550.4]
+  wire  _T_100; // @[pid.scala 130:61:@12552.4]
+  wire  pi_sum_overflow; // @[pid.scala 129:75:@12553.4]
+  wire [16:0] _T_101; // @[pid.scala 135:29:@12556.8]
+  wire [15:0] _T_102; // @[pid.scala 135:29:@12557.8]
+  wire [15:0] _T_103; // @[pid.scala 135:29:@12558.8]
+  wire [16:0] _T_104; // @[pid.scala 137:24:@12562.8]
+  wire [15:0] _T_105; // @[pid.scala 137:24:@12563.8]
+  wire [15:0] _T_106; // @[pid.scala 137:24:@12564.8]
+  wire [15:0] _GEN_7; // @[pid.scala 134:23:@12555.6]
+  wire [16:0] _T_107; // @[pid.scala 141:27:@12569.6]
+  wire [15:0] _T_108; // @[pid.scala 141:27:@12570.6]
+  wire [15:0] _T_109; // @[pid.scala 141:27:@12571.6]
+  wire [15:0] _GEN_8; // @[pid.scala 132:20:@12554.4]
+  wire [15:0] _GEN_9; // @[pid.scala 132:20:@12554.4]
+  wire [15:0] _GEN_10; // @[pid.scala 132:20:@12554.4]
+  wire [15:0] _GEN_11; // @[pid.scala 132:20:@12554.4]
+  wire  _T_110; // @[pid.scala 144:54:@12574.4]
+  wire  _T_111; // @[pid.scala 144:40:@12575.4]
+  wire [15:0] _GEN_12; // @[pid.scala 100:17:@12502.4]
+  vedic_16x16 mul_kp ( // @[pid.scala 110:25:@12513.4]
+    .io_a(mul_kp_io_a),
+    .io_b(mul_kp_io_b),
+    .io_c(mul_kp_io_c)
+  );
+  vedic_16x16 mul_ki ( // @[pid.scala 116:25:@12521.4]
+    .io_a(mul_ki_io_a),
+    .io_b(mul_ki_io_b),
+    .io_c(mul_ki_io_c)
+  );
+  vedic_16x16 mul_kd ( // @[pid.scala 122:25:@12529.4]
+    .io_a(mul_kd_io_a),
+    .io_b(mul_kd_io_b),
+    .io_c(mul_kd_io_c)
+  );
+  assign _GEN_0 = io_reg_kp_we ? $signed(io_reg_kp_di) : $signed(kp); // @[pid.scala 70:22:@12476.4]
+  assign _GEN_1 = io_reg_ki_we ? $signed(io_reg_ki_di) : $signed(ki); // @[pid.scala 75:22:@12480.4]
+  assign _GEN_2 = io_reg_kd_we ? $signed(io_reg_kd_di) : $signed(kd); // @[pid.scala 80:22:@12484.4]
+  assign _GEN_3 = io_reg_ref_we ? $signed(io_reg_ref_di) : $signed(ref$); // @[pid.scala 86:23:@12488.4]
+  assign _GEN_4 = io_reg_fb_we ? $signed(io_reg_fb_di) : $signed(feedback); // @[pid.scala 93:24:@12493.6]
+  assign _GEN_5 = fb_sel ? $signed(_GEN_4) : $signed(io_speed_fb_in); // @[pid.scala 92:16:@12492.4]
+  assign _T_70 = {31'h0,fb_sel}; // @[Cat.scala 30:58:@12500.4]
+  assign _T_71 = $signed(_T_70); // @[pid.scala 100:49:@12501.4]
+  assign _T_72 = io_reg_cfg_di[0]; // @[pid.scala 102:28:@12504.6]
+  assign _GEN_6 = io_reg_cfg_we ? _T_72 : fb_sel; // @[pid.scala 101:23:@12503.4]
+  assign _T_73 = $signed(e_prev1) - $signed(e_prev2); // @[pid.scala 106:27:@12507.4]
+  assign _T_74 = $signed(e_prev1) - $signed(e_prev2); // @[pid.scala 106:27:@12508.4]
+  assign _T_75 = $signed(e_prev1) + $signed(sigma_old); // @[pid.scala 107:27:@12510.4]
+  assign _T_76 = $signed(e_prev1) + $signed(sigma_old); // @[pid.scala 107:27:@12511.4]
+  assign sigma_new = $signed(_T_76); // @[pid.scala 107:27:@12512.4]
+  assign _T_78 = mul_kp_io_c[15:0]; // @[pid.scala 113:30:@12519.4]
+  assign prop_out = $signed(_T_78); // @[pid.scala 113:43:@12520.4]
+  assign _T_80 = mul_ki_io_c[15:0]; // @[pid.scala 119:33:@12527.4]
+  assign integral_out = $signed(_T_80); // @[pid.scala 119:46:@12528.4]
+  assign _T_82 = mul_kd_io_c[15:0]; // @[pid.scala 125:35:@12535.4]
+  assign derivative_out = $signed(_T_82); // @[pid.scala 125:48:@12536.4]
+  assign _T_83 = $signed(prop_out) + $signed(integral_out); // @[pid.scala 128:28:@12537.4]
+  assign _T_84 = $signed(prop_out) + $signed(integral_out); // @[pid.scala 128:28:@12538.4]
+  assign pi_sum = $signed(_T_84); // @[pid.scala 128:28:@12539.4]
+  assign _T_85 = prop_out[15]; // @[pid.scala 129:34:@12540.4]
+  assign _T_86 = integral_out[15]; // @[pid.scala 129:54:@12541.4]
+  assign _T_87 = _T_85 & _T_86; // @[pid.scala 129:39:@12542.4]
+  assign _T_88 = pi_sum[15]; // @[pid.scala 129:69:@12543.4]
+  assign _T_90 = _T_88 == 1'h0; // @[pid.scala 129:62:@12544.4]
+  assign _T_91 = _T_87 & _T_90; // @[pid.scala 129:59:@12545.4]
+  assign _T_94 = _T_85 == 1'h0; // @[pid.scala 130:26:@12547.4]
+  assign _T_97 = _T_86 == 1'h0; // @[pid.scala 130:43:@12549.4]
+  assign _T_98 = _T_94 & _T_97; // @[pid.scala 130:40:@12550.4]
+  assign _T_100 = _T_98 & _T_88; // @[pid.scala 130:61:@12552.4]
+  assign pi_sum_overflow = _T_91 | _T_100; // @[pid.scala 129:75:@12553.4]
+  assign _T_101 = $signed(feedback) - $signed(ref$); // @[pid.scala 135:29:@12556.8]
+  assign _T_102 = $signed(feedback) - $signed(ref$); // @[pid.scala 135:29:@12557.8]
+  assign _T_103 = $signed(_T_102); // @[pid.scala 135:29:@12558.8]
+  assign _T_104 = $signed(ref$) - $signed(feedback); // @[pid.scala 137:24:@12562.8]
+  assign _T_105 = $signed(ref$) - $signed(feedback); // @[pid.scala 137:24:@12563.8]
+  assign _T_106 = $signed(_T_105); // @[pid.scala 137:24:@12564.8]
+  assign _GEN_7 = io_fb_period ? $signed(_T_103) : $signed(_T_106); // @[pid.scala 134:23:@12555.6]
+  assign _T_107 = $signed(pi_sum) + $signed(derivative_out); // @[pid.scala 141:27:@12569.6]
+  assign _T_108 = $signed(pi_sum) + $signed(derivative_out); // @[pid.scala 141:27:@12570.6]
+  assign _T_109 = $signed(_T_108); // @[pid.scala 141:27:@12571.6]
+  assign _GEN_8 = io_raw_irq ? $signed(_GEN_7) : $signed(e_prev1); // @[pid.scala 132:20:@12554.4]
+  assign _GEN_9 = io_raw_irq ? $signed(e_prev1) : $signed(e_prev2); // @[pid.scala 132:20:@12554.4]
+  assign _GEN_10 = io_raw_irq ? $signed(sigma_new) : $signed(sigma_old); // @[pid.scala 132:20:@12554.4]
+  assign _GEN_11 = io_raw_irq ? $signed(_T_109) : $signed(reg_pid_out); // @[pid.scala 132:20:@12554.4]
+  assign _T_110 = reg_pid_out[15]; // @[pid.scala 144:54:@12574.4]
+  assign _T_111 = pi_sum_overflow | _T_110; // @[pid.scala 144:40:@12575.4]
+  assign io_reg_kp_do = kp; // @[pid.scala 69:17:@12475.4]
+  assign io_reg_ki_do = ki; // @[pid.scala 74:17:@12479.4]
+  assign io_reg_kd_do = kd; // @[pid.scala 79:17:@12483.4]
+  assign io_reg_ref_do = ref$; // @[pid.scala 85:17:@12487.4]
+  assign io_reg_fb_do = feedback; // @[pid.scala 90:17:@12491.4]
+  assign _GEN_12 = _T_71[15:0]; // @[pid.scala 100:17:@12502.4]
+  assign io_reg_cfg_do = $signed(_GEN_12); // @[pid.scala 100:17:@12502.4]
+  assign io_pid_out = _T_111 ? $signed(16'sh0) : $signed(reg_pid_out); // @[pid.scala 144:17:@12577.4]
+  assign mul_kp_io_a = e_prev1; // @[pid.scala 111:17:@12516.4]
+  assign mul_kp_io_b = $unsigned(kp); // @[pid.scala 112:17:@12518.4]
+  assign mul_ki_io_a = $signed(_T_76); // @[pid.scala 117:17:@12524.4]
+  assign mul_ki_io_b = $unsigned(ki); // @[pid.scala 118:17:@12526.4]
+  assign mul_kd_io_a = $signed(_T_74); // @[pid.scala 123:17:@12532.4]
+  assign mul_kd_io_b = $unsigned(kd); // @[pid.scala 124:17:@12534.4]
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE
+  integer initvar;
+  initial begin
+    `ifdef INIT_RANDOM
+      `INIT_RANDOM
+    `endif
+    `ifndef VERILATOR
+      #0.002 begin end
+    `endif
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_0 = {1{`RANDOM}};
+  kp = _RAND_0[15:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_1 = {1{`RANDOM}};
+  ki = _RAND_1[15:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_2 = {1{`RANDOM}};
+  kd = _RAND_2[15:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_3 = {1{`RANDOM}};
+  ref$ = _RAND_3[15:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_4 = {1{`RANDOM}};
+  feedback = _RAND_4[15:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_5 = {1{`RANDOM}};
+  sigma_old = _RAND_5[15:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_6 = {1{`RANDOM}};
+  fb_sel = _RAND_6[0:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_7 = {1{`RANDOM}};
+  e_prev1 = _RAND_7[15:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_8 = {1{`RANDOM}};
+  e_prev2 = _RAND_8[15:0];
+  `endif // RANDOMIZE_REG_INIT
+  `ifdef RANDOMIZE_REG_INIT
+  _RAND_9 = {1{`RANDOM}};
+  reg_pid_out = _RAND_9[15:0];
+  `endif // RANDOMIZE_REG_INIT
+  end
+`endif // RANDOMIZE
+  always @(posedge clock) begin
+    if (reset) begin
+      kp <= 16'sh1;
+    end else begin
+      if (io_reg_kp_we) begin
+        kp <= io_reg_kp_di;
+      end
+    end
+    if (reset) begin
+      ki <= 16'sh0;
+    end else begin
+      if (io_reg_ki_we) begin
+        ki <= io_reg_ki_di;
+      end
+    end
+    if (reset) begin
+      kd <= 16'sh0;
+    end else begin
+      if (io_reg_kd_we) begin
+        kd <= io_reg_kd_di;
+      end
+    end
+    if (reset) begin
+      ref$ <= 16'sh14;
+    end else begin
+      if (io_reg_ref_we) begin
+        ref$ <= io_reg_ref_di;
+      end
+    end
+    if (reset) begin
+      feedback <= 16'sh0;
+    end else begin
+      if (fb_sel) begin
+        if (io_reg_fb_we) begin
+          feedback <= io_reg_fb_di;
+        end
+      end else begin
+        feedback <= io_speed_fb_in;
+      end
+    end
+    if (reset) begin
+      sigma_old <= 16'sh0;
+    end else begin
+      if (io_raw_irq) begin
+        sigma_old <= sigma_new;
+      end
+    end
+    if (reset) begin
+      fb_sel <= 1'h0;
+    end else begin
+      if (io_reg_cfg_we) begin
+        fb_sel <= _T_72;
+      end
+    end
+    if (reset) begin
+      e_prev1 <= 16'sh0;
+    end else begin
+      if (io_raw_irq) begin
+        if (io_fb_period) begin
+          e_prev1 <= _T_103;
+        end else begin
+          e_prev1 <= _T_106;
+        end
+      end
+    end
+    if (reset) begin
+      e_prev2 <= 16'sh0;
+    end else begin
+      if (io_raw_irq) begin
+        e_prev2 <= e_prev1;
+      end
+    end
+    if (reset) begin
+      reg_pid_out <= 16'sh0;
+    end else begin
+      if (io_raw_irq) begin
+        reg_pid_out <= _T_109;
+      end
+    end
+  end
+endmodule
+module Motor_Top( // @[:@12579.2]
+  input         clock, // @[:@12580.4]
+  input         reset, // @[:@12581.4]
+  input  [15:0] io_wbs_m2s_addr, // @[:@12582.4]
+  input  [31:0] io_wbs_m2s_data, // @[:@12582.4]
+  input         io_wbs_m2s_we, // @[:@12582.4]
+  input  [3:0]  io_wbs_m2s_sel, // @[:@12582.4]
+  input         io_wbs_m2s_stb, // @[:@12582.4]
+  output        io_wbs_ack_o, // @[:@12582.4]
+  output [31:0] io_wbs_data_o, // @[:@12582.4]
+  input         io_ba_match, // @[:@12582.4]
+  output        io_motor_irq, // @[:@12582.4]
+  input         io_qei_ch_a, // @[:@12582.4]
+  input         io_qei_ch_b, // @[:@12582.4]
+  output        io_pwm_high, // @[:@12582.4]
+  output        io_pwm_low // @[:@12582.4]
+);
+  wire  interlink_clock; // @[motor_top.scala 37:26:@12584.4]
+  wire  interlink_reset; // @[motor_top.scala 37:26:@12584.4]
+  wire [31:0] interlink_io_bus_adr_i; // @[motor_top.scala 37:26:@12584.4]
+  wire [3:0] interlink_io_bus_sel_i; // @[motor_top.scala 37:26:@12584.4]
+  wire  interlink_io_bus_we_i; // @[motor_top.scala 37:26:@12584.4]
+  wire  interlink_io_bus_stb_i; // @[motor_top.scala 37:26:@12584.4]
+  wire  interlink_io_bus_ack_o; // @[motor_top.scala 37:26:@12584.4]
+  wire [31:0] interlink_io_bus_dat_o; // @[motor_top.scala 37:26:@12584.4]
+  wire  interlink_io_tmr_val_we; // @[motor_top.scala 37:26:@12584.4]
+  wire [31:0] interlink_io_tmr_val_do; // @[motor_top.scala 37:26:@12584.4]
+  wire  interlink_io_tmr_dat_we; // @[motor_top.scala 37:26:@12584.4]
+  wire [31:0] interlink_io_tmr_dat_do; // @[motor_top.scala 37:26:@12584.4]
+  wire  interlink_io_tmr_duty_we; // @[motor_top.scala 37:26:@12584.4]
+  wire [31:0] interlink_io_tmr_duty_do; // @[motor_top.scala 37:26:@12584.4]
+  wire  interlink_io_tmr_cfg_we; // @[motor_top.scala 37:26:@12584.4]
+  wire [31:0] interlink_io_tmr_cfg_do; // @[motor_top.scala 37:26:@12584.4]
+  wire  interlink_io_qei_count_we; // @[motor_top.scala 37:26:@12584.4]
+  wire [31:0] interlink_io_qei_count_do; // @[motor_top.scala 37:26:@12584.4]
+  wire  interlink_io_qei_cfg_we; // @[motor_top.scala 37:26:@12584.4]
+  wire [31:0] interlink_io_qei_cfg_do; // @[motor_top.scala 37:26:@12584.4]
+  wire [15:0] interlink_io_qei_speed_do; // @[motor_top.scala 37:26:@12584.4]
+  wire  interlink_io_pid_kp_we; // @[motor_top.scala 37:26:@12584.4]
+  wire [15:0] interlink_io_pid_kp_do; // @[motor_top.scala 37:26:@12584.4]
+  wire  interlink_io_pid_ki_we; // @[motor_top.scala 37:26:@12584.4]
+  wire [15:0] interlink_io_pid_ki_do; // @[motor_top.scala 37:26:@12584.4]
+  wire  interlink_io_pid_kd_we; // @[motor_top.scala 37:26:@12584.4]
+  wire [15:0] interlink_io_pid_kd_do; // @[motor_top.scala 37:26:@12584.4]
+  wire  interlink_io_pid_ref_we; // @[motor_top.scala 37:26:@12584.4]
+  wire [15:0] interlink_io_pid_ref_do; // @[motor_top.scala 37:26:@12584.4]
+  wire  interlink_io_pid_fb_we; // @[motor_top.scala 37:26:@12584.4]
+  wire [15:0] interlink_io_pid_fb_do; // @[motor_top.scala 37:26:@12584.4]
+  wire  interlink_io_pid_cfg_we; // @[motor_top.scala 37:26:@12584.4]
+  wire [15:0] interlink_io_pid_cfg_do; // @[motor_top.scala 37:26:@12584.4]
+  wire  interlink_io_ba_match; // @[motor_top.scala 37:26:@12584.4]
+  wire  pwm_clock; // @[motor_top.scala 53:37:@12595.4]
+  wire  pwm_reset; // @[motor_top.scala 53:37:@12595.4]
+  wire  pwm_io_reg_val_we; // @[motor_top.scala 53:37:@12595.4]
+  wire [31:0] pwm_io_reg_val_di; // @[motor_top.scala 53:37:@12595.4]
+  wire [31:0] pwm_io_reg_val_do; // @[motor_top.scala 53:37:@12595.4]
+  wire  pwm_io_reg_cfg_we; // @[motor_top.scala 53:37:@12595.4]
+  wire [31:0] pwm_io_reg_cfg_di; // @[motor_top.scala 53:37:@12595.4]
+  wire [31:0] pwm_io_reg_cfg_do; // @[motor_top.scala 53:37:@12595.4]
+  wire  pwm_io_reg_dat_we; // @[motor_top.scala 53:37:@12595.4]
+  wire [31:0] pwm_io_reg_dat_di; // @[motor_top.scala 53:37:@12595.4]
+  wire [31:0] pwm_io_reg_dat_do; // @[motor_top.scala 53:37:@12595.4]
+  wire  pwm_io_reg_duty_we; // @[motor_top.scala 53:37:@12595.4]
+  wire [31:0] pwm_io_reg_duty_di; // @[motor_top.scala 53:37:@12595.4]
+  wire [31:0] pwm_io_reg_duty_do; // @[motor_top.scala 53:37:@12595.4]
+  wire [15:0] pwm_io_reg_pid_out; // @[motor_top.scala 53:37:@12595.4]
+  wire  pwm_io_pwm_h; // @[motor_top.scala 53:37:@12595.4]
+  wire  pwm_io_pwm_l; // @[motor_top.scala 53:37:@12595.4]
+  wire  pwm_io_irq_out; // @[motor_top.scala 53:37:@12595.4]
+  wire  pwm_io_rawirq_out; // @[motor_top.scala 53:37:@12595.4]
+  wire  qei_clock; // @[motor_top.scala 82:37:@12615.4]
+  wire  qei_reset; // @[motor_top.scala 82:37:@12615.4]
+  wire  qei_io_quad_a; // @[motor_top.scala 82:37:@12615.4]
+  wire  qei_io_quad_b; // @[motor_top.scala 82:37:@12615.4]
+  wire  qei_io_raw_irq; // @[motor_top.scala 82:37:@12615.4]
+  wire  qei_io_reg_count_we; // @[motor_top.scala 82:37:@12615.4]
+  wire [31:0] qei_io_reg_count_di; // @[motor_top.scala 82:37:@12615.4]
+  wire [31:0] qei_io_reg_count_do; // @[motor_top.scala 82:37:@12615.4]
+  wire  qei_io_reg_cfg_we; // @[motor_top.scala 82:37:@12615.4]
+  wire [31:0] qei_io_reg_cfg_di; // @[motor_top.scala 82:37:@12615.4]
+  wire [31:0] qei_io_reg_cfg_do; // @[motor_top.scala 82:37:@12615.4]
+  wire [15:0] qei_io_reg_speed_do; // @[motor_top.scala 82:37:@12615.4]
+  wire  qei_io_fb_period; // @[motor_top.scala 82:37:@12615.4]
+  wire  pid_clock; // @[motor_top.scala 98:37:@12628.4]
+  wire  pid_reset; // @[motor_top.scala 98:37:@12628.4]
+  wire  pid_io_fb_period; // @[motor_top.scala 98:37:@12628.4]
+  wire  pid_io_raw_irq; // @[motor_top.scala 98:37:@12628.4]
+  wire  pid_io_reg_kp_we; // @[motor_top.scala 98:37:@12628.4]
+  wire [15:0] pid_io_reg_kp_di; // @[motor_top.scala 98:37:@12628.4]
+  wire [15:0] pid_io_reg_kp_do; // @[motor_top.scala 98:37:@12628.4]
+  wire  pid_io_reg_ki_we; // @[motor_top.scala 98:37:@12628.4]
+  wire [15:0] pid_io_reg_ki_di; // @[motor_top.scala 98:37:@12628.4]
+  wire [15:0] pid_io_reg_ki_do; // @[motor_top.scala 98:37:@12628.4]
+  wire  pid_io_reg_kd_we; // @[motor_top.scala 98:37:@12628.4]
+  wire [15:0] pid_io_reg_kd_di; // @[motor_top.scala 98:37:@12628.4]
+  wire [15:0] pid_io_reg_kd_do; // @[motor_top.scala 98:37:@12628.4]
+  wire  pid_io_reg_ref_we; // @[motor_top.scala 98:37:@12628.4]
+  wire [15:0] pid_io_reg_ref_di; // @[motor_top.scala 98:37:@12628.4]
+  wire [15:0] pid_io_reg_ref_do; // @[motor_top.scala 98:37:@12628.4]
+  wire  pid_io_reg_fb_we; // @[motor_top.scala 98:37:@12628.4]
+  wire [15:0] pid_io_reg_fb_di; // @[motor_top.scala 98:37:@12628.4]
+  wire [15:0] pid_io_reg_fb_do; // @[motor_top.scala 98:37:@12628.4]
+  wire  pid_io_reg_cfg_we; // @[motor_top.scala 98:37:@12628.4]
+  wire [15:0] pid_io_reg_cfg_di; // @[motor_top.scala 98:37:@12628.4]
+  wire [15:0] pid_io_reg_cfg_do; // @[motor_top.scala 98:37:@12628.4]
+  wire [15:0] pid_io_speed_fb_in; // @[motor_top.scala 98:37:@12628.4]
+  wire [15:0] pid_io_pid_out; // @[motor_top.scala 98:37:@12628.4]
+  wire [7:0] _T_48; // @[motor_top.scala 103:41:@12634.4]
+  wire [7:0] _T_49; // @[motor_top.scala 103:53:@12635.4]
+  wire [15:0] _T_54; // @[motor_top.scala 115:41:@12649.4]
+  Interlink_Module interlink ( // @[motor_top.scala 37:26:@12584.4]
+    .clock(interlink_clock),
+    .reset(interlink_reset),
+    .io_bus_adr_i(interlink_io_bus_adr_i),
+    .io_bus_sel_i(interlink_io_bus_sel_i),
+    .io_bus_we_i(interlink_io_bus_we_i),
+    .io_bus_stb_i(interlink_io_bus_stb_i),
+    .io_bus_ack_o(interlink_io_bus_ack_o),
+    .io_bus_dat_o(interlink_io_bus_dat_o),
+    .io_tmr_val_we(interlink_io_tmr_val_we),
+    .io_tmr_val_do(interlink_io_tmr_val_do),
+    .io_tmr_dat_we(interlink_io_tmr_dat_we),
+    .io_tmr_dat_do(interlink_io_tmr_dat_do),
+    .io_tmr_duty_we(interlink_io_tmr_duty_we),
+    .io_tmr_duty_do(interlink_io_tmr_duty_do),
+    .io_tmr_cfg_we(interlink_io_tmr_cfg_we),
+    .io_tmr_cfg_do(interlink_io_tmr_cfg_do),
+    .io_qei_count_we(interlink_io_qei_count_we),
+    .io_qei_count_do(interlink_io_qei_count_do),
+    .io_qei_cfg_we(interlink_io_qei_cfg_we),
+    .io_qei_cfg_do(interlink_io_qei_cfg_do),
+    .io_qei_speed_do(interlink_io_qei_speed_do),
+    .io_pid_kp_we(interlink_io_pid_kp_we),
+    .io_pid_kp_do(interlink_io_pid_kp_do),
+    .io_pid_ki_we(interlink_io_pid_ki_we),
+    .io_pid_ki_do(interlink_io_pid_ki_do),
+    .io_pid_kd_we(interlink_io_pid_kd_we),
+    .io_pid_kd_do(interlink_io_pid_kd_do),
+    .io_pid_ref_we(interlink_io_pid_ref_we),
+    .io_pid_ref_do(interlink_io_pid_ref_do),
+    .io_pid_fb_we(interlink_io_pid_fb_we),
+    .io_pid_fb_do(interlink_io_pid_fb_do),
+    .io_pid_cfg_we(interlink_io_pid_cfg_we),
+    .io_pid_cfg_do(interlink_io_pid_cfg_do),
+    .io_ba_match(interlink_io_ba_match)
+  );
+  PWM pwm ( // @[motor_top.scala 53:37:@12595.4]
+    .clock(pwm_clock),
+    .reset(pwm_reset),
+    .io_reg_val_we(pwm_io_reg_val_we),
+    .io_reg_val_di(pwm_io_reg_val_di),
+    .io_reg_val_do(pwm_io_reg_val_do),
+    .io_reg_cfg_we(pwm_io_reg_cfg_we),
+    .io_reg_cfg_di(pwm_io_reg_cfg_di),
+    .io_reg_cfg_do(pwm_io_reg_cfg_do),
+    .io_reg_dat_we(pwm_io_reg_dat_we),
+    .io_reg_dat_di(pwm_io_reg_dat_di),
+    .io_reg_dat_do(pwm_io_reg_dat_do),
+    .io_reg_duty_we(pwm_io_reg_duty_we),
+    .io_reg_duty_di(pwm_io_reg_duty_di),
+    .io_reg_duty_do(pwm_io_reg_duty_do),
+    .io_reg_pid_out(pwm_io_reg_pid_out),
+    .io_pwm_h(pwm_io_pwm_h),
+    .io_pwm_l(pwm_io_pwm_l),
+    .io_irq_out(pwm_io_irq_out),
+    .io_rawirq_out(pwm_io_rawirq_out)
+  );
+  Quad_Encoder qei ( // @[motor_top.scala 82:37:@12615.4]
+    .clock(qei_clock),
+    .reset(qei_reset),
+    .io_quad_a(qei_io_quad_a),
+    .io_quad_b(qei_io_quad_b),
+    .io_raw_irq(qei_io_raw_irq),
+    .io_reg_count_we(qei_io_reg_count_we),
+    .io_reg_count_di(qei_io_reg_count_di),
+    .io_reg_count_do(qei_io_reg_count_do),
+    .io_reg_cfg_we(qei_io_reg_cfg_we),
+    .io_reg_cfg_di(qei_io_reg_cfg_di),
+    .io_reg_cfg_do(qei_io_reg_cfg_do),
+    .io_reg_speed_do(qei_io_reg_speed_do),
+    .io_fb_period(qei_io_fb_period)
+  );
+  PID_Controller pid ( // @[motor_top.scala 98:37:@12628.4]
+    .clock(pid_clock),
+    .reset(pid_reset),
+    .io_fb_period(pid_io_fb_period),
+    .io_raw_irq(pid_io_raw_irq),
+    .io_reg_kp_we(pid_io_reg_kp_we),
+    .io_reg_kp_di(pid_io_reg_kp_di),
+    .io_reg_kp_do(pid_io_reg_kp_do),
+    .io_reg_ki_we(pid_io_reg_ki_we),
+    .io_reg_ki_di(pid_io_reg_ki_di),
+    .io_reg_ki_do(pid_io_reg_ki_do),
+    .io_reg_kd_we(pid_io_reg_kd_we),
+    .io_reg_kd_di(pid_io_reg_kd_di),
+    .io_reg_kd_do(pid_io_reg_kd_do),
+    .io_reg_ref_we(pid_io_reg_ref_we),
+    .io_reg_ref_di(pid_io_reg_ref_di),
+    .io_reg_ref_do(pid_io_reg_ref_do),
+    .io_reg_fb_we(pid_io_reg_fb_we),
+    .io_reg_fb_di(pid_io_reg_fb_di),
+    .io_reg_fb_do(pid_io_reg_fb_do),
+    .io_reg_cfg_we(pid_io_reg_cfg_we),
+    .io_reg_cfg_di(pid_io_reg_cfg_di),
+    .io_reg_cfg_do(pid_io_reg_cfg_do),
+    .io_speed_fb_in(pid_io_speed_fb_in),
+    .io_pid_out(pid_io_pid_out)
+  );
+  assign _T_48 = io_wbs_m2s_data[7:0]; // @[motor_top.scala 103:41:@12634.4]
+  assign _T_49 = $signed(_T_48); // @[motor_top.scala 103:53:@12635.4]
+  assign _T_54 = io_wbs_m2s_data[15:0]; // @[motor_top.scala 115:41:@12649.4]
+  assign io_wbs_ack_o = interlink_io_bus_ack_o; // @[motor_top.scala 50:29:@12594.4]
+  assign io_wbs_data_o = interlink_io_bus_dat_o; // @[motor_top.scala 49:29:@12593.4]
+  assign io_motor_irq = pwm_io_irq_out; // @[motor_top.scala 74:29:@12612.4]
+  assign io_pwm_high = pwm_io_pwm_h; // @[motor_top.scala 77:29:@12613.4]
+  assign io_pwm_low = pwm_io_pwm_l; // @[motor_top.scala 78:29:@12614.4]
+  assign interlink_clock = clock; // @[:@12585.4]
+  assign interlink_reset = reset; // @[:@12586.4]
+  assign interlink_io_bus_adr_i = {{16'd0}, io_wbs_m2s_addr}; // @[motor_top.scala 46:29:@12590.4]
+  assign interlink_io_bus_sel_i = io_wbs_m2s_sel; // @[motor_top.scala 47:29:@12591.4]
+  assign interlink_io_bus_we_i = io_wbs_m2s_we; // @[motor_top.scala 48:29:@12592.4]
+  assign interlink_io_bus_stb_i = io_wbs_m2s_stb; // @[motor_top.scala 44:29:@12588.4]
+  assign interlink_io_tmr_val_do = pwm_io_reg_val_do; // @[motor_top.scala 57:29:@12600.4]
+  assign interlink_io_tmr_dat_do = pwm_io_reg_dat_do; // @[motor_top.scala 65:29:@12606.4]
+  assign interlink_io_tmr_duty_do = pwm_io_reg_duty_do; // @[motor_top.scala 68:29:@12609.4]
+  assign interlink_io_tmr_cfg_do = pwm_io_reg_cfg_do; // @[motor_top.scala 61:29:@12603.4]
+  assign interlink_io_qei_count_do = qei_io_reg_count_do; // @[motor_top.scala 89:29:@12623.4]
+  assign interlink_io_qei_cfg_do = qei_io_reg_cfg_do; // @[motor_top.scala 93:29:@12626.4]
+  assign interlink_io_qei_speed_do = qei_io_reg_speed_do; // @[motor_top.scala 95:29:@12627.4]
+  assign interlink_io_pid_kp_do = pid_io_reg_kp_do; // @[motor_top.scala 104:29:@12637.4]
+  assign interlink_io_pid_ki_do = pid_io_reg_ki_do; // @[motor_top.scala 108:29:@12642.4]
+  assign interlink_io_pid_kd_do = pid_io_reg_kd_do; // @[motor_top.scala 112:29:@12647.4]
+  assign interlink_io_pid_ref_do = pid_io_reg_ref_do; // @[motor_top.scala 116:29:@12652.4]
+  assign interlink_io_pid_fb_do = pid_io_reg_fb_do; // @[motor_top.scala 120:29:@12657.4]
+  assign interlink_io_pid_cfg_do = pid_io_reg_cfg_do; // @[motor_top.scala 124:29:@12662.4]
+  assign interlink_io_ba_match = io_ba_match; // @[motor_top.scala 41:29:@12587.4]
+  assign pwm_clock = clock; // @[:@12596.4]
+  assign pwm_reset = reset; // @[:@12597.4]
+  assign pwm_io_reg_val_we = interlink_io_tmr_val_we; // @[motor_top.scala 55:29:@12598.4]
+  assign pwm_io_reg_val_di = io_wbs_m2s_data; // @[motor_top.scala 56:29:@12599.4]
+  assign pwm_io_reg_cfg_we = interlink_io_tmr_cfg_we; // @[motor_top.scala 59:29:@12601.4]
+  assign pwm_io_reg_cfg_di = io_wbs_m2s_data; // @[motor_top.scala 60:29:@12602.4]
+  assign pwm_io_reg_dat_we = interlink_io_tmr_dat_we; // @[motor_top.scala 63:29:@12604.4]
+  assign pwm_io_reg_dat_di = io_wbs_m2s_data; // @[motor_top.scala 64:29:@12605.4]
+  assign pwm_io_reg_duty_we = interlink_io_tmr_duty_we; // @[motor_top.scala 66:29:@12607.4]
+  assign pwm_io_reg_duty_di = io_wbs_m2s_data; // @[motor_top.scala 67:29:@12608.4]
+  assign pwm_io_reg_pid_out = pid_io_pid_out; // @[motor_top.scala 73:29:@12611.4]
+  assign qei_clock = clock; // @[:@12616.4]
+  assign qei_reset = reset; // @[:@12617.4]
+  assign qei_io_quad_a = io_qei_ch_a; // @[motor_top.scala 83:29:@12618.4]
+  assign qei_io_quad_b = io_qei_ch_b; // @[motor_top.scala 84:29:@12619.4]
+  assign qei_io_raw_irq = pwm_io_rawirq_out; // @[motor_top.scala 85:29:@12620.4]
+  assign qei_io_reg_count_we = interlink_io_qei_count_we; // @[motor_top.scala 87:29:@12621.4]
+  assign qei_io_reg_count_di = io_wbs_m2s_data; // @[motor_top.scala 88:29:@12622.4]
+  assign qei_io_reg_cfg_we = interlink_io_qei_cfg_we; // @[motor_top.scala 91:29:@12624.4]
+  assign qei_io_reg_cfg_di = io_wbs_m2s_data; // @[motor_top.scala 92:29:@12625.4]
+  assign pid_clock = clock; // @[:@12629.4]
+  assign pid_reset = reset; // @[:@12630.4]
+  assign pid_io_fb_period = qei_io_fb_period; // @[motor_top.scala 99:29:@12631.4]
+  assign pid_io_raw_irq = pwm_io_rawirq_out; // @[motor_top.scala 127:29:@12664.4]
+  assign pid_io_reg_kp_we = interlink_io_pid_kp_we; // @[motor_top.scala 102:29:@12633.4]
+  assign pid_io_reg_kp_di = {{8{_T_49[7]}},_T_49}; // @[motor_top.scala 103:29:@12636.4]
+  assign pid_io_reg_ki_we = interlink_io_pid_ki_we; // @[motor_top.scala 106:29:@12638.4]
+  assign pid_io_reg_ki_di = {{8{_T_49[7]}},_T_49}; // @[motor_top.scala 107:29:@12641.4]
+  assign pid_io_reg_kd_we = interlink_io_pid_kd_we; // @[motor_top.scala 110:29:@12643.4]
+  assign pid_io_reg_kd_di = {{8{_T_49[7]}},_T_49}; // @[motor_top.scala 111:29:@12646.4]
+  assign pid_io_reg_ref_we = interlink_io_pid_ref_we; // @[motor_top.scala 114:29:@12648.4]
+  assign pid_io_reg_ref_di = $signed(_T_54); // @[motor_top.scala 115:29:@12651.4]
+  assign pid_io_reg_fb_we = interlink_io_pid_fb_we; // @[motor_top.scala 118:29:@12653.4]
+  assign pid_io_reg_fb_di = $signed(_T_54); // @[motor_top.scala 119:29:@12656.4]
+  assign pid_io_reg_cfg_we = interlink_io_pid_cfg_we; // @[motor_top.scala 122:29:@12658.4]
+  assign pid_io_reg_cfg_di = $signed(_T_54); // @[motor_top.scala 123:29:@12661.4]
+  assign pid_io_speed_fb_in = qei_io_reg_speed_do; // @[motor_top.scala 100:29:@12632.4]
+endmodule
diff --git a/verilog/rtl/Processor_Tile.v b/verilog/rtl/Processor_Tile.v
new file mode 100644
index 0000000..6bc19e4
--- /dev/null
+++ b/verilog/rtl/Processor_Tile.v
@@ -0,0 +1,244 @@
+module Processor_Tile( // @[:@12742.2]
+  input   clock, // @[:@12743.4]
+  input   reset, // @[:@12744.4]
+  output  io_uart_tx, // @[:@12745.4]
+  input   io_uart_rx, // @[:@12745.4]
+  output  io_spi_cs, // @[:@12745.4]
+  output  io_spi_clk, // @[:@12745.4]
+  output  io_spi_mosi, // @[:@12745.4]
+  input   io_spi_miso, // @[:@12745.4]
+  input   io_qei_ch_a, // @[:@12745.4]
+  input   io_qei_ch_b, // @[:@12745.4]
+  output  io_pwm_high, // @[:@12745.4]
+  output  io_pwm_low // @[:@12745.4]
+);
+  wire  core_clock; // @[processor_tile.scala 52:32:@12747.4]
+  wire  core_reset; // @[processor_tile.scala 52:32:@12747.4]
+  wire  core_io_irq_uart_irq; // @[processor_tile.scala 52:32:@12747.4]
+  wire  core_io_irq_spi_irq; // @[processor_tile.scala 52:32:@12747.4]
+  wire  core_io_irq_motor_irq; // @[processor_tile.scala 52:32:@12747.4]
+  wire [31:0] core_io_ibus_addr; // @[processor_tile.scala 52:32:@12747.4]
+  wire [31:0] core_io_ibus_inst; // @[processor_tile.scala 52:32:@12747.4]
+  wire  core_io_ibus_valid; // @[processor_tile.scala 52:32:@12747.4]
+  wire [31:0] core_io_dbus_addr; // @[processor_tile.scala 52:32:@12747.4]
+  wire [31:0] core_io_dbus_wdata; // @[processor_tile.scala 52:32:@12747.4]
+  wire [31:0] core_io_dbus_rdata; // @[processor_tile.scala 52:32:@12747.4]
+  wire  core_io_dbus_rd_en; // @[processor_tile.scala 52:32:@12747.4]
+  wire  core_io_dbus_wr_en; // @[processor_tile.scala 52:32:@12747.4]
+  wire [1:0] core_io_dbus_st_type; // @[processor_tile.scala 52:32:@12747.4]
+  wire [2:0] core_io_dbus_ld_type; // @[processor_tile.scala 52:32:@12747.4]
+  wire  core_io_dbus_valid; // @[processor_tile.scala 52:32:@12747.4]
+  wire  wb_inter_connect_clock; // @[processor_tile.scala 53:32:@12750.4]
+  wire  wb_inter_connect_reset; // @[processor_tile.scala 53:32:@12750.4]
+  wire [31:0] wb_inter_connect_io_dbus_addr; // @[processor_tile.scala 53:32:@12750.4]
+  wire [31:0] wb_inter_connect_io_dbus_wdata; // @[processor_tile.scala 53:32:@12750.4]
+  wire [31:0] wb_inter_connect_io_dbus_rdata; // @[processor_tile.scala 53:32:@12750.4]
+  wire  wb_inter_connect_io_dbus_rd_en; // @[processor_tile.scala 53:32:@12750.4]
+  wire  wb_inter_connect_io_dbus_wr_en; // @[processor_tile.scala 53:32:@12750.4]
+  wire [1:0] wb_inter_connect_io_dbus_st_type; // @[processor_tile.scala 53:32:@12750.4]
+  wire [2:0] wb_inter_connect_io_dbus_ld_type; // @[processor_tile.scala 53:32:@12750.4]
+  wire  wb_inter_connect_io_dbus_valid; // @[processor_tile.scala 53:32:@12750.4]
+  wire [31:0] wb_inter_connect_io_ibus_addr; // @[processor_tile.scala 53:32:@12750.4]
+  wire [31:0] wb_inter_connect_io_ibus_inst; // @[processor_tile.scala 53:32:@12750.4]
+  wire  wb_inter_connect_io_ibus_valid; // @[processor_tile.scala 53:32:@12750.4]
+  wire [8:0] wb_inter_connect_io_imem_io_addr; // @[processor_tile.scala 53:32:@12750.4]
+  wire [31:0] wb_inter_connect_io_imem_io_rdata; // @[processor_tile.scala 53:32:@12750.4]
+  wire [31:0] wb_inter_connect_io_imem_io_wdata; // @[processor_tile.scala 53:32:@12750.4]
+  wire  wb_inter_connect_io_imem_io_wr_en; // @[processor_tile.scala 53:32:@12750.4]
+  wire  wb_inter_connect_io_imem_io_cs; // @[processor_tile.scala 53:32:@12750.4]
+  wire [7:0] wb_inter_connect_io_dmem_io_addr; // @[processor_tile.scala 53:32:@12750.4]
+  wire [31:0] wb_inter_connect_io_dmem_io_wdata; // @[processor_tile.scala 53:32:@12750.4]
+  wire [31:0] wb_inter_connect_io_dmem_io_rdata; // @[processor_tile.scala 53:32:@12750.4]
+  wire  wb_inter_connect_io_dmem_io_cs; // @[processor_tile.scala 53:32:@12750.4]
+  wire  wb_inter_connect_io_dmem_io_wr_en; // @[processor_tile.scala 53:32:@12750.4]
+  wire [3:0] wb_inter_connect_io_dmem_io_st_type; // @[processor_tile.scala 53:32:@12750.4]
+  wire [15:0] wb_inter_connect_io_wbm_m2s_addr; // @[processor_tile.scala 53:32:@12750.4]
+  wire [31:0] wb_inter_connect_io_wbm_m2s_data; // @[processor_tile.scala 53:32:@12750.4]
+  wire  wb_inter_connect_io_wbm_m2s_we; // @[processor_tile.scala 53:32:@12750.4]
+  wire [3:0] wb_inter_connect_io_wbm_m2s_sel; // @[processor_tile.scala 53:32:@12750.4]
+  wire  wb_inter_connect_io_wbm_m2s_stb; // @[processor_tile.scala 53:32:@12750.4]
+  wire  wb_inter_connect_io_uart_tx; // @[processor_tile.scala 53:32:@12750.4]
+  wire  wb_inter_connect_io_uart_rx; // @[processor_tile.scala 53:32:@12750.4]
+  wire  wb_inter_connect_io_uart_irq; // @[processor_tile.scala 53:32:@12750.4]
+  wire  wb_inter_connect_io_spi_cs; // @[processor_tile.scala 53:32:@12750.4]
+  wire  wb_inter_connect_io_spi_clk; // @[processor_tile.scala 53:32:@12750.4]
+  wire  wb_inter_connect_io_spi_mosi; // @[processor_tile.scala 53:32:@12750.4]
+  wire  wb_inter_connect_io_spi_miso; // @[processor_tile.scala 53:32:@12750.4]
+  wire  wb_inter_connect_io_spi_irq; // @[processor_tile.scala 53:32:@12750.4]
+  wire  wb_inter_connect_io_motor_ack_i; // @[processor_tile.scala 53:32:@12750.4]
+  wire [31:0] wb_inter_connect_io_motor_data_i; // @[processor_tile.scala 53:32:@12750.4]
+  wire  wb_inter_connect_io_motor_addr_sel; // @[processor_tile.scala 53:32:@12750.4]
+  wire  motor_clock; // @[processor_tile.scala 55:32:@12753.4]
+  wire  motor_reset; // @[processor_tile.scala 55:32:@12753.4]
+  wire [15:0] motor_io_wbs_m2s_addr; // @[processor_tile.scala 55:32:@12753.4]
+  wire [31:0] motor_io_wbs_m2s_data; // @[processor_tile.scala 55:32:@12753.4]
+  wire  motor_io_wbs_m2s_we; // @[processor_tile.scala 55:32:@12753.4]
+  wire [3:0] motor_io_wbs_m2s_sel; // @[processor_tile.scala 55:32:@12753.4]
+  wire  motor_io_wbs_m2s_stb; // @[processor_tile.scala 55:32:@12753.4]
+  wire  motor_io_wbs_ack_o; // @[processor_tile.scala 55:32:@12753.4]
+  wire [31:0] motor_io_wbs_data_o; // @[processor_tile.scala 55:32:@12753.4]
+  wire  motor_io_ba_match; // @[processor_tile.scala 55:32:@12753.4]
+  wire  motor_io_motor_irq; // @[processor_tile.scala 55:32:@12753.4]
+  wire  motor_io_qei_ch_a; // @[processor_tile.scala 55:32:@12753.4]
+  wire  motor_io_qei_ch_b; // @[processor_tile.scala 55:32:@12753.4]
+  wire  motor_io_pwm_high; // @[processor_tile.scala 55:32:@12753.4]
+  wire  motor_io_pwm_low; // @[processor_tile.scala 55:32:@12753.4]
+  wire  imem_clock; // @[processor_tile.scala 56:32:@12756.4]
+  wire [8:0] imem_io_addr; // @[processor_tile.scala 56:32:@12756.4]
+  wire [31:0] imem_io_rdata; // @[processor_tile.scala 56:32:@12756.4]
+  wire [31:0] imem_io_wdata; // @[processor_tile.scala 56:32:@12756.4]
+  wire  imem_io_wr_en; // @[processor_tile.scala 56:32:@12756.4]
+  wire  imem_io_cs; // @[processor_tile.scala 56:32:@12756.4]
+  wire  dmem_clock; // @[processor_tile.scala 57:32:@12759.4]
+  wire [7:0] dmem_io_addr; // @[processor_tile.scala 57:32:@12759.4]
+  wire [31:0] dmem_io_wdata; // @[processor_tile.scala 57:32:@12759.4]
+  wire [31:0] dmem_io_rdata; // @[processor_tile.scala 57:32:@12759.4]
+  wire  dmem_io_cs; // @[processor_tile.scala 57:32:@12759.4]
+  wire  dmem_io_wr_en; // @[processor_tile.scala 57:32:@12759.4]
+  wire [3:0] dmem_io_st_type; // @[processor_tile.scala 57:32:@12759.4]
+  Core core ( // @[processor_tile.scala 52:32:@12747.4]
+    .clock(core_clock),
+    .reset(core_reset),
+    .io_irq_uart_irq(core_io_irq_uart_irq),
+    .io_irq_spi_irq(core_io_irq_spi_irq),
+    .io_irq_motor_irq(core_io_irq_motor_irq),
+    .io_ibus_addr(core_io_ibus_addr),
+    .io_ibus_inst(core_io_ibus_inst),
+    .io_ibus_valid(core_io_ibus_valid),
+    .io_dbus_addr(core_io_dbus_addr),
+    .io_dbus_wdata(core_io_dbus_wdata),
+    .io_dbus_rdata(core_io_dbus_rdata),
+    .io_dbus_rd_en(core_io_dbus_rd_en),
+    .io_dbus_wr_en(core_io_dbus_wr_en),
+    .io_dbus_st_type(core_io_dbus_st_type),
+    .io_dbus_ld_type(core_io_dbus_ld_type),
+    .io_dbus_valid(core_io_dbus_valid)
+  );
+  WB_InterConnect wb_inter_connect ( // @[processor_tile.scala 53:32:@12750.4]
+    .clock(wb_inter_connect_clock),
+    .reset(wb_inter_connect_reset),
+    .io_dbus_addr(wb_inter_connect_io_dbus_addr),
+    .io_dbus_wdata(wb_inter_connect_io_dbus_wdata),
+    .io_dbus_rdata(wb_inter_connect_io_dbus_rdata),
+    .io_dbus_rd_en(wb_inter_connect_io_dbus_rd_en),
+    .io_dbus_wr_en(wb_inter_connect_io_dbus_wr_en),
+    .io_dbus_st_type(wb_inter_connect_io_dbus_st_type),
+    .io_dbus_ld_type(wb_inter_connect_io_dbus_ld_type),
+    .io_dbus_valid(wb_inter_connect_io_dbus_valid),
+    .io_ibus_addr(wb_inter_connect_io_ibus_addr),
+    .io_ibus_inst(wb_inter_connect_io_ibus_inst),
+    .io_ibus_valid(wb_inter_connect_io_ibus_valid),
+    .io_imem_io_addr(wb_inter_connect_io_imem_io_addr),
+    .io_imem_io_rdata(wb_inter_connect_io_imem_io_rdata),
+    .io_imem_io_wdata(wb_inter_connect_io_imem_io_wdata),
+    .io_imem_io_wr_en(wb_inter_connect_io_imem_io_wr_en),
+    .io_imem_io_cs(wb_inter_connect_io_imem_io_cs),
+    .io_dmem_io_addr(wb_inter_connect_io_dmem_io_addr),
+    .io_dmem_io_wdata(wb_inter_connect_io_dmem_io_wdata),
+    .io_dmem_io_rdata(wb_inter_connect_io_dmem_io_rdata),
+    .io_dmem_io_cs(wb_inter_connect_io_dmem_io_cs),
+    .io_dmem_io_wr_en(wb_inter_connect_io_dmem_io_wr_en),
+    .io_dmem_io_st_type(wb_inter_connect_io_dmem_io_st_type),
+    .io_wbm_m2s_addr(wb_inter_connect_io_wbm_m2s_addr),
+    .io_wbm_m2s_data(wb_inter_connect_io_wbm_m2s_data),
+    .io_wbm_m2s_we(wb_inter_connect_io_wbm_m2s_we),
+    .io_wbm_m2s_sel(wb_inter_connect_io_wbm_m2s_sel),
+    .io_wbm_m2s_stb(wb_inter_connect_io_wbm_m2s_stb),
+    .io_uart_tx(wb_inter_connect_io_uart_tx),
+    .io_uart_rx(wb_inter_connect_io_uart_rx),
+    .io_uart_irq(wb_inter_connect_io_uart_irq),
+    .io_spi_cs(wb_inter_connect_io_spi_cs),
+    .io_spi_clk(wb_inter_connect_io_spi_clk),
+    .io_spi_mosi(wb_inter_connect_io_spi_mosi),
+    .io_spi_miso(wb_inter_connect_io_spi_miso),
+    .io_spi_irq(wb_inter_connect_io_spi_irq),
+    .io_motor_ack_i(wb_inter_connect_io_motor_ack_i),
+    .io_motor_data_i(wb_inter_connect_io_motor_data_i),
+    .io_motor_addr_sel(wb_inter_connect_io_motor_addr_sel)
+  );
+  Motor_Top motor ( // @[processor_tile.scala 55:32:@12753.4]
+    .clock(motor_clock),
+    .reset(motor_reset),
+    .io_wbs_m2s_addr(motor_io_wbs_m2s_addr),
+    .io_wbs_m2s_data(motor_io_wbs_m2s_data),
+    .io_wbs_m2s_we(motor_io_wbs_m2s_we),
+    .io_wbs_m2s_sel(motor_io_wbs_m2s_sel),
+    .io_wbs_m2s_stb(motor_io_wbs_m2s_stb),
+    .io_wbs_ack_o(motor_io_wbs_ack_o),
+    .io_wbs_data_o(motor_io_wbs_data_o),
+    .io_ba_match(motor_io_ba_match),
+    .io_motor_irq(motor_io_motor_irq),
+    .io_qei_ch_a(motor_io_qei_ch_a),
+    .io_qei_ch_b(motor_io_qei_ch_b),
+    .io_pwm_high(motor_io_pwm_high),
+    .io_pwm_low(motor_io_pwm_low)
+  );
+  IMem imem ( // @[processor_tile.scala 56:32:@12756.4]
+    .clock(imem_clock),
+    .io_addr(imem_io_addr),
+    .io_rdata(imem_io_rdata),
+    .io_wdata(imem_io_wdata),
+    .io_wr_en(imem_io_wr_en),
+    .io_cs(imem_io_cs)
+  );
+  DMem dmem ( // @[processor_tile.scala 57:32:@12759.4]
+    .clock(dmem_clock),
+    .io_addr(dmem_io_addr),
+    .io_wdata(dmem_io_wdata),
+    .io_rdata(dmem_io_rdata),
+    .io_cs(dmem_io_cs),
+    .io_wr_en(dmem_io_wr_en),
+    .io_st_type(dmem_io_st_type)
+  );
+  assign io_uart_tx = wb_inter_connect_io_uart_tx; // @[processor_tile.scala 69:32:@12791.4]
+  assign io_spi_cs = wb_inter_connect_io_spi_cs; // @[processor_tile.scala 74:32:@12794.4]
+  assign io_spi_clk = wb_inter_connect_io_spi_clk; // @[processor_tile.scala 75:32:@12795.4]
+  assign io_spi_mosi = wb_inter_connect_io_spi_mosi; // @[processor_tile.scala 76:32:@12796.4]
+  assign io_pwm_high = motor_io_pwm_high; // @[processor_tile.scala 95:24:@12810.4]
+  assign io_pwm_low = motor_io_pwm_low; // @[processor_tile.scala 96:24:@12811.4]
+  assign core_clock = clock; // @[:@12748.4]
+  assign core_reset = reset; // @[:@12749.4]
+  assign core_io_irq_uart_irq = wb_inter_connect_io_uart_irq; // @[processor_tile.scala 71:32:@12793.4]
+  assign core_io_irq_spi_irq = wb_inter_connect_io_spi_irq; // @[processor_tile.scala 78:32:@12798.4]
+  assign core_io_irq_motor_irq = motor_io_motor_irq; // @[processor_tile.scala 97:25:@12812.4]
+  assign core_io_ibus_inst = wb_inter_connect_io_ibus_inst; // @[processor_tile.scala 65:24:@12781.4]
+  assign core_io_ibus_valid = wb_inter_connect_io_ibus_valid; // @[processor_tile.scala 65:24:@12780.4]
+  assign core_io_dbus_rdata = wb_inter_connect_io_dbus_rdata; // @[processor_tile.scala 66:24:@12788.4]
+  assign core_io_dbus_valid = wb_inter_connect_io_dbus_valid; // @[processor_tile.scala 66:24:@12783.4]
+  assign wb_inter_connect_clock = clock; // @[:@12751.4]
+  assign wb_inter_connect_reset = reset; // @[:@12752.4]
+  assign wb_inter_connect_io_dbus_addr = core_io_dbus_addr; // @[processor_tile.scala 66:24:@12790.4]
+  assign wb_inter_connect_io_dbus_wdata = core_io_dbus_wdata; // @[processor_tile.scala 66:24:@12789.4]
+  assign wb_inter_connect_io_dbus_rd_en = core_io_dbus_rd_en; // @[processor_tile.scala 66:24:@12787.4]
+  assign wb_inter_connect_io_dbus_wr_en = core_io_dbus_wr_en; // @[processor_tile.scala 66:24:@12786.4]
+  assign wb_inter_connect_io_dbus_st_type = core_io_dbus_st_type; // @[processor_tile.scala 66:24:@12785.4]
+  assign wb_inter_connect_io_dbus_ld_type = core_io_dbus_ld_type; // @[processor_tile.scala 66:24:@12784.4]
+  assign wb_inter_connect_io_ibus_addr = core_io_ibus_addr; // @[processor_tile.scala 65:24:@12782.4]
+  assign wb_inter_connect_io_imem_io_rdata = imem_io_rdata; // @[processor_tile.scala 60:11:@12769.4]
+  assign wb_inter_connect_io_dmem_io_rdata = dmem_io_rdata; // @[processor_tile.scala 61:11:@12777.4]
+  assign wb_inter_connect_io_uart_rx = io_uart_rx; // @[processor_tile.scala 70:32:@12792.4]
+  assign wb_inter_connect_io_spi_miso = io_spi_miso; // @[processor_tile.scala 77:32:@12797.4]
+  assign wb_inter_connect_io_motor_ack_i = motor_io_wbs_ack_o; // @[processor_tile.scala 90:35:@12806.4]
+  assign wb_inter_connect_io_motor_data_i = motor_io_wbs_data_o; // @[processor_tile.scala 89:36:@12805.4]
+  assign motor_clock = clock; // @[:@12754.4]
+  assign motor_reset = reset; // @[:@12755.4]
+  assign motor_io_wbs_m2s_addr = wb_inter_connect_io_wbm_m2s_addr; // @[processor_tile.scala 88:28:@12804.4]
+  assign motor_io_wbs_m2s_data = wb_inter_connect_io_wbm_m2s_data; // @[processor_tile.scala 88:28:@12803.4]
+  assign motor_io_wbs_m2s_we = wb_inter_connect_io_wbm_m2s_we; // @[processor_tile.scala 88:28:@12802.4]
+  assign motor_io_wbs_m2s_sel = wb_inter_connect_io_wbm_m2s_sel; // @[processor_tile.scala 88:28:@12801.4]
+  assign motor_io_wbs_m2s_stb = wb_inter_connect_io_wbm_m2s_stb; // @[processor_tile.scala 88:28:@12800.4]
+  assign motor_io_ba_match = wb_inter_connect_io_motor_addr_sel; // @[processor_tile.scala 92:24:@12807.4]
+  assign motor_io_qei_ch_a = io_qei_ch_a; // @[processor_tile.scala 93:24:@12808.4]
+  assign motor_io_qei_ch_b = io_qei_ch_b; // @[processor_tile.scala 94:24:@12809.4]
+  assign imem_clock = clock; // @[:@12757.4]
+  assign imem_io_addr = wb_inter_connect_io_imem_io_addr; // @[processor_tile.scala 60:11:@12770.4]
+  assign imem_io_wdata = wb_inter_connect_io_imem_io_wdata; // @[processor_tile.scala 60:11:@12768.4]
+  assign imem_io_wr_en = wb_inter_connect_io_imem_io_wr_en; // @[processor_tile.scala 60:11:@12767.4]
+  assign imem_io_cs = wb_inter_connect_io_imem_io_cs; // @[processor_tile.scala 60:11:@12766.4]
+  assign dmem_clock = clock; // @[:@12760.4]
+  assign dmem_io_addr = wb_inter_connect_io_dmem_io_addr; // @[processor_tile.scala 61:11:@12779.4]
+  assign dmem_io_wdata = wb_inter_connect_io_dmem_io_wdata; // @[processor_tile.scala 61:11:@12778.4]
+  assign dmem_io_cs = wb_inter_connect_io_dmem_io_cs; // @[processor_tile.scala 61:11:@12776.4]
+  assign dmem_io_wr_en = wb_inter_connect_io_dmem_io_wr_en; // @[processor_tile.scala 61:11:@12775.4]
+  assign dmem_io_st_type = wb_inter_connect_io_dmem_io_st_type; // @[processor_tile.scala 61:11:@12774.4]
+endmodule