
 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.12+45 (git sha1 UNKNOWN, gcc 8.3.1 -fPIC -Os)

[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.

1. Executing Verilog-2005 frontend: /home/ali112000/mpw5/UETRV-ECORE/caravel/verilog/rtl/defines.v
Parsing SystemVerilog input from `/home/ali112000/mpw5/UETRV-ECORE/caravel/verilog/rtl/defines.v' to AST representation.
Successfully finished Verilog frontend.

2. Executing Verilog-2005 frontend: /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v
Parsing SystemVerilog input from `/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v' to AST representation.
Generating RTLIL representation for module `\DMem_Interface'.
Generating RTLIL representation for module `\BMem'.
Generating RTLIL representation for module `\IMem_Interface'.
Generating RTLIL representation for module `\WBM_DBus'.
Generating RTLIL representation for module `\UARTTx'.
Generating RTLIL representation for module `\UARTRx'.
Generating RTLIL representation for module `\UART'.
Generating RTLIL representation for module `\SPI'.
Generating RTLIL representation for module `\WB_InterConnect'.
Successfully finished Verilog frontend.

3. Generating Graphviz representation of design.
Writing dot description to `/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/synthesis/hierarchy.dot'.
Dumping module WB_InterConnect to page 1.

4. Executing HIERARCHY pass (managing design hierarchy).

4.1. Analyzing design hierarchy..
Top module:  \WB_InterConnect
Used module:     \SPI
Used module:     \UART
Used module:         \UARTRx
Used module:         \UARTTx
Used module:     \WBM_DBus
Used module:     \IMem_Interface
Used module:         \BMem
Used module:     \DMem_Interface

4.2. Analyzing design hierarchy..
Top module:  \WB_InterConnect
Used module:     \SPI
Used module:     \UART
Used module:         \UARTRx
Used module:         \UARTTx
Used module:     \WBM_DBus
Used module:     \IMem_Interface
Used module:         \BMem
Used module:     \DMem_Interface
Removed 0 unused modules.

5. Executing TRIBUF pass.

6. Executing SYNTH pass.

6.1. Executing HIERARCHY pass (managing design hierarchy).

6.1.1. Analyzing design hierarchy..
Top module:  \WB_InterConnect
Used module:     \SPI
Used module:     \UART
Used module:         \UARTRx
Used module:         \UARTTx
Used module:     \WBM_DBus
Used module:     \IMem_Interface
Used module:         \BMem
Used module:     \DMem_Interface

6.1.2. Analyzing design hierarchy..
Top module:  \WB_InterConnect
Used module:     \SPI
Used module:     \UART
Used module:         \UARTRx
Used module:         \UARTTx
Used module:     \WBM_DBus
Used module:     \IMem_Interface
Used module:         \BMem
Used module:     \DMem_Interface
Removed 0 unused modules.

6.2. Executing PROC pass (convert processes to netlists).

6.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

6.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 59 switch rules as full_case in process $proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3500$763 in module SPI.
Marked 12 switch rules as full_case in process $proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2880$622 in module UART.
Marked 13 switch rules as full_case in process $proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2540$575 in module UARTRx.
Marked 8 switch rules as full_case in process $proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2323$537 in module UARTTx.
Marked 3 switch rules as full_case in process $proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2112$493 in module IMem_Interface.
Marked 218 switch rules as full_case in process $proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:1070$461 in module BMem.
Marked 2 switch rules as full_case in process $proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:140$23 in module DMem_Interface.
Removed a total of 0 dead cases.

6.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 15 redundant assignments.
Promoted 8 assignments to connections.

6.2.4. Executing PROC_INIT pass (extract init attributes).

6.2.5. Executing PROC_ARST pass (detect async resets in processes).

6.2.6. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\WB_InterConnect.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:4189$783'.
Creating decoders for process `\SPI.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3500$763'.
     1/30: $0\wait_one_tick_done[0:0]
     2/30: $0\p_status[2:0]
     3/30: $0\clock_cnt[4:0]
     4/30: $0\bit_e[0:0]
     5/30: $0\bit_tmt[0:0]
     6/30: $0\tx_shift_data[7:0]
     7/30: $0\rx_shift_data[7:0]
     8/30: $0\n_status[2:0]
     9/30: $0\pending_data[0:0]
    10/30: $0\data_cnt[5:0]
    11/30: $0\bit_rrdy[0:0]
    12/30: $0\bit_trdy[0:0]
    13/30: $0\bit_roe[0:0]
    14/30: $0\bit_toe[0:0]
    15/30: $0\bit_en_io[0:0]
    16/30: $0\bit_sso[0:0]
    17/30: $0\bit_ie[0:0]
    18/30: $0\bit_irrdy[0:0]
    19/30: $0\bit_itrdy[0:0]
    20/30: $0\bit_itoe[0:0]
    21/30: $0\bit_iroe[0:0]
    22/30: $0\rx_latch_flag[0:0]
    23/30: $0\reg_ssmask[0:0]
    24/30: $0\reg_txdata[7:0]
    25/30: $0\reg_rxdata[7:0]
    26/30: $0\read_wait_done[0:0]
    27/30: $0\mosi_r[0:0]
    28/30: $0\sclk_r[0:0]
    29/30: $0\ack_o[0:0]
    30/30: $0\rd_data[7:0]
Creating decoders for process `\UART.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2880$622'.
     1/9: $0\rd_data[7:0]
     2/9: $0\ack[0:0]
     3/9: $0\status_r[7:0]
     4/9: $0\txen[0:0]
     5/9: $0\int_mask_r[7:0]
     6/9: $0\baud_r[9:0]
     7/9: $0\control_r[7:0]
     8/9: $0\rx_data_r[7:0]
     9/9: $0\tx_data_r[7:0]
Creating decoders for process `\UARTRx.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2540$575'.
     1/6: $0\valid[0:0]
     2/6: $0\state[0:0]
     3/6: $0\debounce[8:0]
     4/6: $0\data_count[3:0]
     5/6: $0\shifter[7:0]
     6/6: $0\prescaler[9:0]
Creating decoders for process `\UARTTx.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2323$537'.
     1/4: $0\out[0:0]
     2/4: $0\shifter[8:0]
     3/4: $0\counter[3:0]
     4/4: $0\prescaler[9:0]
Creating decoders for process `\IMem_Interface.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2112$493'.
     1/3: $0\imem_ibus_valid[0:0]
     2/3: $0\bmem_ibus_sel[0:0]
     3/3: $0\ack[0:0]
Creating decoders for process `\BMem.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:1070$461'.
     1/1: $0\bmem_data[31:0]
Creating decoders for process `\DMem_Interface.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:140$23'.
     1/2: $0\ack[0:0]
     2/2: $0\ack2[0:0]

6.2.7. Executing PROC_DLATCH pass (convert process syncs to latches).

6.2.8. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\WB_InterConnect.\imem_sel' using process `\WB_InterConnect.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:4189$783'.
  created $dff cell `$procdff$1876' with positive edge clock.
Creating register for signal `\WB_InterConnect.\dmem_sel' using process `\WB_InterConnect.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:4189$783'.
  created $dff cell `$procdff$1877' with positive edge clock.
Creating register for signal `\WB_InterConnect.\uart_sel' using process `\WB_InterConnect.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:4189$783'.
  created $dff cell `$procdff$1878' with positive edge clock.
Creating register for signal `\WB_InterConnect.\spi_sel' using process `\WB_InterConnect.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:4189$783'.
  created $dff cell `$procdff$1879' with positive edge clock.
Creating register for signal `\WB_InterConnect.\motor_sel' using process `\WB_InterConnect.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:4189$783'.
  created $dff cell `$procdff$1880' with positive edge clock.
Creating register for signal `\SPI.\rd_data' using process `\SPI.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3500$763'.
  created $dff cell `$procdff$1881' with positive edge clock.
Creating register for signal `\SPI.\ack_o' using process `\SPI.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3500$763'.
  created $dff cell `$procdff$1882' with positive edge clock.
Creating register for signal `\SPI.\sclk_r' using process `\SPI.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3500$763'.
  created $dff cell `$procdff$1883' with positive edge clock.
Creating register for signal `\SPI.\mosi_r' using process `\SPI.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3500$763'.
  created $dff cell `$procdff$1884' with positive edge clock.
Creating register for signal `\SPI.\read_wait_done' using process `\SPI.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3500$763'.
  created $dff cell `$procdff$1885' with positive edge clock.
Creating register for signal `\SPI.\reg_rxdata' using process `\SPI.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3500$763'.
  created $dff cell `$procdff$1886' with positive edge clock.
Creating register for signal `\SPI.\reg_txdata' using process `\SPI.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3500$763'.
  created $dff cell `$procdff$1887' with positive edge clock.
Creating register for signal `\SPI.\reg_ssmask' using process `\SPI.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3500$763'.
  created $dff cell `$procdff$1888' with positive edge clock.
Creating register for signal `\SPI.\rx_shift_data' using process `\SPI.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3500$763'.
  created $dff cell `$procdff$1889' with positive edge clock.
Creating register for signal `\SPI.\tx_shift_data' using process `\SPI.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3500$763'.
  created $dff cell `$procdff$1890' with positive edge clock.
Creating register for signal `\SPI.\rx_latch_flag' using process `\SPI.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3500$763'.
  created $dff cell `$procdff$1891' with positive edge clock.
Creating register for signal `\SPI.\bit_iroe' using process `\SPI.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3500$763'.
  created $dff cell `$procdff$1892' with positive edge clock.
Creating register for signal `\SPI.\bit_itoe' using process `\SPI.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3500$763'.
  created $dff cell `$procdff$1893' with positive edge clock.
Creating register for signal `\SPI.\bit_itrdy' using process `\SPI.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3500$763'.
  created $dff cell `$procdff$1894' with positive edge clock.
Creating register for signal `\SPI.\bit_irrdy' using process `\SPI.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3500$763'.
  created $dff cell `$procdff$1895' with positive edge clock.
Creating register for signal `\SPI.\bit_ie' using process `\SPI.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3500$763'.
  created $dff cell `$procdff$1896' with positive edge clock.
Creating register for signal `\SPI.\bit_sso' using process `\SPI.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3500$763'.
  created $dff cell `$procdff$1897' with positive edge clock.
Creating register for signal `\SPI.\bit_en_io' using process `\SPI.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3500$763'.
  created $dff cell `$procdff$1898' with positive edge clock.
Creating register for signal `\SPI.\bit_toe' using process `\SPI.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3500$763'.
  created $dff cell `$procdff$1899' with positive edge clock.
Creating register for signal `\SPI.\bit_roe' using process `\SPI.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3500$763'.
  created $dff cell `$procdff$1900' with positive edge clock.
Creating register for signal `\SPI.\bit_trdy' using process `\SPI.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3500$763'.
  created $dff cell `$procdff$1901' with positive edge clock.
Creating register for signal `\SPI.\bit_rrdy' using process `\SPI.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3500$763'.
  created $dff cell `$procdff$1902' with positive edge clock.
Creating register for signal `\SPI.\bit_tmt' using process `\SPI.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3500$763'.
  created $dff cell `$procdff$1903' with positive edge clock.
Creating register for signal `\SPI.\bit_e' using process `\SPI.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3500$763'.
  created $dff cell `$procdff$1904' with positive edge clock.
Creating register for signal `\SPI.\clock_cnt' using process `\SPI.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3500$763'.
  created $dff cell `$procdff$1905' with positive edge clock.
Creating register for signal `\SPI.\data_cnt' using process `\SPI.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3500$763'.
  created $dff cell `$procdff$1906' with positive edge clock.
Creating register for signal `\SPI.\pending_data' using process `\SPI.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3500$763'.
  created $dff cell `$procdff$1907' with positive edge clock.
Creating register for signal `\SPI.\n_status' using process `\SPI.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3500$763'.
  created $dff cell `$procdff$1908' with positive edge clock.
Creating register for signal `\SPI.\p_status' using process `\SPI.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3500$763'.
  created $dff cell `$procdff$1909' with positive edge clock.
Creating register for signal `\SPI.\wait_one_tick_done' using process `\SPI.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3500$763'.
  created $dff cell `$procdff$1910' with positive edge clock.
Creating register for signal `\UART.\ack' using process `\UART.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2880$622'.
  created $dff cell `$procdff$1911' with positive edge clock.
Creating register for signal `\UART.\txen' using process `\UART.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2880$622'.
  created $dff cell `$procdff$1912' with positive edge clock.
Creating register for signal `\UART.\tx_data_r' using process `\UART.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2880$622'.
  created $dff cell `$procdff$1913' with positive edge clock.
Creating register for signal `\UART.\rx_data_r' using process `\UART.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2880$622'.
  created $dff cell `$procdff$1914' with positive edge clock.
Creating register for signal `\UART.\control_r' using process `\UART.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2880$622'.
  created $dff cell `$procdff$1915' with positive edge clock.
Creating register for signal `\UART.\baud_r' using process `\UART.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2880$622'.
  created $dff cell `$procdff$1916' with positive edge clock.
Creating register for signal `\UART.\status_r' using process `\UART.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2880$622'.
  created $dff cell `$procdff$1917' with positive edge clock.
Creating register for signal `\UART.\int_mask_r' using process `\UART.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2880$622'.
  created $dff cell `$procdff$1918' with positive edge clock.
Creating register for signal `\UART.\rd_data' using process `\UART.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2880$622'.
  created $dff cell `$procdff$1919' with positive edge clock.
Creating register for signal `\UARTRx.\prescaler' using process `\UARTRx.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2540$575'.
  created $dff cell `$procdff$1920' with positive edge clock.
Creating register for signal `\UARTRx.\shifter' using process `\UARTRx.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2540$575'.
  created $dff cell `$procdff$1921' with positive edge clock.
Creating register for signal `\UARTRx.\data_count' using process `\UARTRx.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2540$575'.
  created $dff cell `$procdff$1922' with positive edge clock.
Creating register for signal `\UARTRx.\debounce' using process `\UARTRx.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2540$575'.
  created $dff cell `$procdff$1923' with positive edge clock.
Creating register for signal `\UARTRx.\valid' using process `\UARTRx.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2540$575'.
  created $dff cell `$procdff$1924' with positive edge clock.
Creating register for signal `\UARTRx.\state' using process `\UARTRx.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2540$575'.
  created $dff cell `$procdff$1925' with positive edge clock.
Creating register for signal `\UARTTx.\prescaler' using process `\UARTTx.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2323$537'.
  created $dff cell `$procdff$1926' with positive edge clock.
Creating register for signal `\UARTTx.\counter' using process `\UARTTx.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2323$537'.
  created $dff cell `$procdff$1927' with positive edge clock.
Creating register for signal `\UARTTx.\shifter' using process `\UARTTx.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2323$537'.
  created $dff cell `$procdff$1928' with positive edge clock.
Creating register for signal `\UARTTx.\out' using process `\UARTTx.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2323$537'.
  created $dff cell `$procdff$1929' with positive edge clock.
Creating register for signal `\IMem_Interface.\ack' using process `\IMem_Interface.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2112$493'.
  created $dff cell `$procdff$1930' with positive edge clock.
Creating register for signal `\IMem_Interface.\wb_select' using process `\IMem_Interface.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2112$493'.
  created $dff cell `$procdff$1931' with positive edge clock.
Creating register for signal `\IMem_Interface.\bmem_ibus_sel' using process `\IMem_Interface.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2112$493'.
  created $dff cell `$procdff$1932' with positive edge clock.
Creating register for signal `\IMem_Interface.\imem_ibus_valid' using process `\IMem_Interface.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2112$493'.
  created $dff cell `$procdff$1933' with positive edge clock.
Creating register for signal `\BMem.\bmem_data' using process `\BMem.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:1070$461'.
  created $dff cell `$procdff$1934' with positive edge clock.
Creating register for signal `\DMem_Interface.\ack2' using process `\DMem_Interface.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:140$23'.
  created $dff cell `$procdff$1935' with positive edge clock.
Creating register for signal `\DMem_Interface.\ack' using process `\DMem_Interface.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:140$23'.
  created $dff cell `$procdff$1936' with positive edge clock.
Creating register for signal `\DMem_Interface.\wb_select' using process `\DMem_Interface.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:140$23'.
  created $dff cell `$procdff$1937' with positive edge clock.
Creating register for signal `\DMem_Interface.\rd_resp' using process `\DMem_Interface.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:140$23'.
  created $dff cell `$procdff$1938' with positive edge clock.

6.2.9. Executing PROC_MEMWR pass (convert process memory writes to cells).

6.2.10. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `WB_InterConnect.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:4189$783'.
Found and cleaned up 85 empty switches in `\SPI.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3500$763'.
Removing empty process `SPI.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3500$763'.
Found and cleaned up 27 empty switches in `\UART.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2880$622'.
Removing empty process `UART.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2880$622'.
Found and cleaned up 33 empty switches in `\UARTRx.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2540$575'.
Removing empty process `UARTRx.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2540$575'.
Found and cleaned up 15 empty switches in `\UARTTx.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2323$537'.
Removing empty process `UARTTx.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2323$537'.
Found and cleaned up 4 empty switches in `\IMem_Interface.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2112$493'.
Removing empty process `IMem_Interface.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2112$493'.
Found and cleaned up 219 empty switches in `\BMem.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:1070$461'.
Removing empty process `BMem.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:1070$461'.
Found and cleaned up 3 empty switches in `\DMem_Interface.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:140$23'.
Removing empty process `DMem_Interface.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:140$23'.
Cleaned up 386 empty switches.

6.2.11. Executing OPT_EXPR pass (perform const folding).
Optimizing module WB_InterConnect.
<suppressed ~1 debug messages>
Optimizing module SPI.
<suppressed ~7 debug messages>
Optimizing module UART.
<suppressed ~9 debug messages>
Optimizing module UARTRx.
<suppressed ~25 debug messages>
Optimizing module UARTTx.
<suppressed ~4 debug messages>
Optimizing module WBM_DBus.
<suppressed ~1 debug messages>
Optimizing module IMem_Interface.
<suppressed ~6 debug messages>
Optimizing module BMem.
<suppressed ~1 debug messages>
Optimizing module DMem_Interface.
<suppressed ~2 debug messages>

6.3. Executing FLATTEN pass (flatten design).
Deleting now unused module SPI.
Deleting now unused module UART.
Deleting now unused module UARTRx.
Deleting now unused module UARTTx.
Deleting now unused module WBM_DBus.
Deleting now unused module IMem_Interface.
Deleting now unused module BMem.
Deleting now unused module DMem_Interface.
<suppressed ~8 debug messages>

6.4. Executing OPT_EXPR pass (perform const folding).
Optimizing module WB_InterConnect.
<suppressed ~2 debug messages>

6.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \WB_InterConnect..
Removed 341 unused cells and 1619 unused wires.
<suppressed ~738 debug messages>

6.6. Executing CHECK pass (checking for obvious problems).
Checking module WB_InterConnect...
Found and reported 0 problems.

6.7. Executing OPT pass (performing simple optimizations).

6.7.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module WB_InterConnect.

6.7.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\WB_InterConnect'.
<suppressed ~90 debug messages>
Removed a total of 30 cells.

6.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \WB_InterConnect..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port B of cell $flatten\spi.$procmux$876: \spi.bit_rrdy -> 1'1
      Replacing known input bits on port A of cell $flatten\spi.$procmux$944: \spi.rx_latch_flag -> 1'0
      Replacing known input bits on port A of cell $flatten\spi.$procmux$990: \spi.ack_o -> 1'0
      Replacing known input bits on port A of cell $flatten\uart.\rxm.$procmux$1097: \uart.rxm.state -> 1'0
      Replacing known input bits on port A of cell $flatten\uart.\rxm.$procmux$1095: \uart.rxm.state -> 1'1
      Replacing known input bits on port A of cell $flatten\uart.\rxm.$procmux$1093: \uart.rxm.state -> 1'1
      Replacing known input bits on port B of cell $flatten\uart.\rxm.$procmux$1102: \uart.rxm.state -> 1'0
      Replacing known input bits on port A of cell $flatten\uart.\rxm.$procmux$1100: \uart.rxm.state -> 1'0
  Analyzing evaluation results.
    dead port 2/2 on $mux $flatten\uart.\rxm.$procmux$1088.
    dead port 2/2 on $mux $flatten\uart.\rxm.$procmux$1097.
    dead port 2/2 on $mux $flatten\uart.\rxm.$procmux$1113.
    dead port 2/2 on $mux $flatten\uart.\rxm.$procmux$1125.
    dead port 2/2 on $mux $flatten\uart.\rxm.$procmux$1138.
    dead port 2/2 on $mux $flatten\uart.\rxm.$procmux$1148.
Removed 6 multiplexer ports.
<suppressed ~62 debug messages>

6.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \WB_InterConnect.
    New ctrl vector for $mux cell $flatten\spi.$procmux$876: { }
    New ctrl vector for $mux cell $flatten\spi.$procmux$944: { }
  Optimizing cells in module \WB_InterConnect.
Performed a total of 2 changes.

6.7.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\WB_InterConnect'.
<suppressed ~15 debug messages>
Removed a total of 5 cells.

6.7.6. Executing OPT_DFF pass (perform DFF optimizations).

6.7.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \WB_InterConnect..
Removed 0 unused cells and 13 unused wires.
<suppressed ~1 debug messages>

6.7.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module WB_InterConnect.

6.7.9. Rerunning OPT passes. (Maybe there is more to do..)

6.7.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \WB_InterConnect..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~64 debug messages>

6.7.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \WB_InterConnect.
Performed a total of 0 changes.

6.7.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\WB_InterConnect'.
Removed a total of 0 cells.

6.7.13. Executing OPT_DFF pass (perform DFF optimizations).

6.7.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \WB_InterConnect..

6.7.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module WB_InterConnect.

6.7.16. Finished OPT passes. (There is nothing left to do.)

6.8. Executing FSM pass (extract and optimize FSM).

6.8.1. Executing FSM_DETECT pass (finding FSMs in design).
Not marking WB_InterConnect.imem.bmem.bmem_data as FSM state register:
    Users of register don't seem to benefit from recoding.
Not marking WB_InterConnect.spi.n_status as FSM state register:
    Users of register don't seem to benefit from recoding.

6.8.2. Executing FSM_EXTRACT pass (extracting FSM from design).

6.8.3. Executing FSM_OPT pass (simple optimizations of FSMs).

6.8.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \WB_InterConnect..

6.8.5. Executing FSM_OPT pass (simple optimizations of FSMs).

6.8.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).

6.8.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

6.8.8. Executing FSM_MAP pass (mapping FSMs to basic logic).

6.9. Executing OPT pass (performing simple optimizations).

6.9.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module WB_InterConnect.

6.9.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\WB_InterConnect'.
Removed a total of 0 cells.

6.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \WB_InterConnect..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~64 debug messages>

6.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \WB_InterConnect.
Performed a total of 0 changes.

6.9.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\WB_InterConnect'.
Removed a total of 0 cells.

6.9.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $flatten\uart.\txm.$procdff$1929 ($dff) from module WB_InterConnect (D = $flatten\uart.\txm.$procmux$1165_Y, Q = \uart.txm.out, rval = 1'1).
Adding EN signal on $auto$ff.cc:262:slice$1939 ($sdff) from module WB_InterConnect (D = \uart.txm.shifter [0], Q = \uart.txm.out).
Adding SRST signal on $flatten\uart.\txm.$procdff$1927 ($dff) from module WB_InterConnect (D = $flatten\uart.\txm.$procmux$1188_Y, Q = \uart.txm.counter, rval = 4'0000).
Adding SRST signal on $flatten\uart.\txm.$procdff$1926 ($dff) from module WB_InterConnect (D = $flatten\uart.\txm.$procmux$1196_Y, Q = \uart.txm.prescaler, rval = 10'0000000000).
Adding EN signal on $auto$ff.cc:262:slice$1944 ($sdff) from module WB_InterConnect (D = $flatten\uart.\txm.$procmux$1194_Y, Q = \uart.txm.prescaler).
Adding SRST signal on $flatten\uart.\rxm.$procdff$1925 ($dff) from module WB_InterConnect (D = $flatten\uart.\rxm.$procmux$1104_Y, Q = \uart.rxm.state, rval = 1'0).
Adding SRST signal on $flatten\uart.\rxm.$procdff$1924 ($dff) from module WB_InterConnect (D = \uart.rxm.data_last, Q = \uart.rxm.valid, rval = 1'0).
Adding SRST signal on $flatten\uart.\rxm.$procdff$1923 ($dff) from module WB_InterConnect (D = $flatten\uart.\rxm.$procmux$1118_Y, Q = \uart.rxm.debounce, rval = 9'000000000).
Adding EN signal on $auto$ff.cc:262:slice$1950 ($sdff) from module WB_InterConnect (D = $flatten\uart.\rxm.$procmux$1118_Y, Q = \uart.rxm.debounce).
Adding EN signal on $flatten\uart.\rxm.$procdff$1922 ($dff) from module WB_InterConnect (D = $flatten\uart.\rxm.$0\data_count[3:0], Q = \uart.rxm.data_count).
Adding SRST signal on $flatten\uart.\rxm.$procdff$1921 ($dff) from module WB_InterConnect (D = $flatten\uart.\rxm.$procmux$1140_Y, Q = \uart.rxm.shifter, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:262:slice$1969 ($sdff) from module WB_InterConnect (D = { \io_uart_rx \uart.rxm.shifter [7:1] }, Q = \uart.rxm.shifter).
Adding SRST signal on $flatten\uart.\rxm.$procdff$1920 ($dff) from module WB_InterConnect (D = $flatten\uart.\rxm.$procmux$1158_Y, Q = \uart.rxm.prescaler, rval = 10'0000000000).
Adding EN signal on $auto$ff.cc:262:slice$1975 ($sdff) from module WB_InterConnect (D = $flatten\uart.\rxm.$procmux$1158_Y, Q = \uart.rxm.prescaler).
Adding SRST signal on $flatten\uart.$procdff$1919 ($dff) from module WB_InterConnect (D = \uart._GEN_3 [7:0], Q = \uart.rd_data, rval = 8'00000000).
Adding SRST signal on $flatten\uart.$procdff$1918 ($dff) from module WB_InterConnect (D = $flatten\uart.$procmux$1047_Y, Q = \uart.int_mask_r, rval = 8'00000001).
Adding EN signal on $auto$ff.cc:262:slice$1984 ($sdff) from module WB_InterConnect (D = \io_dbus_wdata [7:0], Q = \uart.int_mask_r).
Adding SRST signal on $flatten\uart.$procdff$1917 ($dff) from module WB_InterConnect (D = $flatten\uart.$procmux$1028_Y, Q = \uart.status_r, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:262:slice$1994 ($sdff) from module WB_InterConnect (D = $flatten\uart.$procmux$1025_Y [1], Q = \uart.status_r [1]).
Adding EN signal on $auto$ff.cc:262:slice$1994 ($sdff) from module WB_InterConnect (D = \io_dbus_wdata [7:2], Q = \uart.status_r [7:2]).
Adding EN signal on $auto$ff.cc:262:slice$1994 ($sdff) from module WB_InterConnect (D = $flatten\uart.$procmux$1028_Y [0], Q = \uart.status_r [0]).
Adding SRST signal on $flatten\uart.$procdff$1916 ($dff) from module WB_InterConnect (D = $flatten\uart.$procmux$1056_Y, Q = \uart.baud_r, rval = 10'0000001000).
Adding EN signal on $auto$ff.cc:262:slice$2004 ($sdff) from module WB_InterConnect (D = { 2'00 \io_dbus_wdata [7:0] }, Q = \uart.baud_r).
Setting constant 0-bit at position 8 on $auto$ff.cc:262:slice$2005 ($sdffe) from module WB_InterConnect.
Setting constant 0-bit at position 9 on $auto$ff.cc:262:slice$2005 ($sdffe) from module WB_InterConnect.
Adding SRST signal on $flatten\uart.$procdff$1915 ($dff) from module WB_InterConnect (D = $flatten\uart.$procmux$1067_Y, Q = \uart.control_r, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:262:slice$2011 ($sdff) from module WB_InterConnect (D = \io_dbus_wdata [7:0], Q = \uart.control_r).
Adding SRST signal on $flatten\uart.$procdff$1914 ($dff) from module WB_InterConnect (D = $flatten\uart.$procmux$1072_Y, Q = \uart.rx_data_r, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:262:slice$2019 ($sdff) from module WB_InterConnect (D = \uart.rxm.shifter, Q = \uart.rx_data_r).
Adding SRST signal on $flatten\uart.$procdff$1913 ($dff) from module WB_InterConnect (D = $flatten\uart.$procmux$1079_Y, Q = \uart.tx_data_r, rval = 8'01001010).
Adding EN signal on $auto$ff.cc:262:slice$2021 ($sdff) from module WB_InterConnect (D = \io_dbus_wdata [7:0], Q = \uart.tx_data_r).
Adding SRST signal on $flatten\uart.$procdff$1912 ($dff) from module WB_InterConnect (D = \uart.sel_reg_tx, Q = \uart.txen, rval = 1'0).
Adding SRST signal on $flatten\spi.$procdff$1909 ($dff) from module WB_InterConnect (D = \spi.n_status, Q = \spi.p_status, rval = 3'000).
Adding SRST signal on $flatten\spi.$procdff$1908 ($dff) from module WB_InterConnect (D = $flatten\spi.$procmux$846_Y, Q = \spi.n_status, rval = 3'000).
Adding EN signal on $auto$ff.cc:262:slice$2031 ($sdff) from module WB_InterConnect (D = $flatten\spi.$procmux$846_Y, Q = \spi.n_status).
Adding SRST signal on $flatten\spi.$procdff$1907 ($dff) from module WB_InterConnect (D = $flatten\spi.$procmux$854_Y, Q = \spi.pending_data, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$2035 ($sdff) from module WB_InterConnect (D = $flatten\spi.$procmux$854_Y, Q = \spi.pending_data).
Adding SRST signal on $flatten\spi.$procdff$1906 ($dff) from module WB_InterConnect (D = $flatten\spi.$procmux$859_Y, Q = \spi.data_cnt, rval = 6'000000).
Adding EN signal on $auto$ff.cc:262:slice$2039 ($sdff) from module WB_InterConnect (D = \spi._T_308, Q = \spi.data_cnt).
Adding SRST signal on $flatten\spi.$procdff$1905 ($dff) from module WB_InterConnect (D = \spi._T_224, Q = \spi.clock_cnt, rval = 5'00000).
Adding SRST signal on $flatten\spi.$procdff$1904 ($dff) from module WB_InterConnect (D = \spi._T_131, Q = \spi.bit_e, rval = 1'0).
Adding SRST signal on $flatten\spi.$procdff$1903 ($dff) from module WB_InterConnect (D = $flatten\spi.$procmux$805_Y, Q = \spi.bit_tmt, rval = 1'1).
Adding SRST signal on $flatten\spi.$procdff$1902 ($dff) from module WB_InterConnect (D = $flatten\spi.$procmux$878_Y, Q = \spi.bit_rrdy, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$2048 ($sdff) from module WB_InterConnect (D = $flatten\spi.$procmux$878_Y, Q = \spi.bit_rrdy).
Adding SRST signal on $flatten\spi.$procdff$1901 ($dff) from module WB_InterConnect (D = $flatten\spi.$procmux$883_Y, Q = \spi.bit_trdy, rval = 1'1).
Adding EN signal on $auto$ff.cc:262:slice$2052 ($sdff) from module WB_InterConnect (D = 1'0, Q = \spi.bit_trdy).
Adding SRST signal on $flatten\spi.$procdff$1900 ($dff) from module WB_InterConnect (D = $flatten\spi.$procmux$896_Y, Q = \spi.bit_roe, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$2056 ($sdff) from module WB_InterConnect (D = $flatten\spi.$procmux$896_Y, Q = \spi.bit_roe).
Adding SRST signal on $flatten\spi.$procdff$1899 ($dff) from module WB_InterConnect (D = $flatten\spi.$procmux$904_Y, Q = \spi.bit_toe, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$2064 ($sdff) from module WB_InterConnect (D = $flatten\spi.$procmux$904_Y, Q = \spi.bit_toe).
Adding SRST signal on $flatten\spi.$procdff$1898 ($dff) from module WB_InterConnect (D = $flatten\spi.$procmux$909_Y, Q = \spi.bit_en_io, rval = 1'1).
Adding EN signal on $auto$ff.cc:262:slice$2068 ($sdff) from module WB_InterConnect (D = \io_dbus_wdata [6], Q = \spi.bit_en_io).
Adding SRST signal on $flatten\spi.$procdff$1897 ($dff) from module WB_InterConnect (D = $flatten\spi.$procmux$914_Y, Q = \spi.bit_sso, rval = 1'1).
Adding EN signal on $auto$ff.cc:262:slice$2070 ($sdff) from module WB_InterConnect (D = \io_dbus_wdata [7], Q = \spi.bit_sso).
Adding SRST signal on $flatten\spi.$procdff$1896 ($dff) from module WB_InterConnect (D = $flatten\spi.$procmux$919_Y, Q = \spi.bit_ie, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$2072 ($sdff) from module WB_InterConnect (D = \io_dbus_wdata [5], Q = \spi.bit_ie).
Adding SRST signal on $flatten\spi.$procdff$1895 ($dff) from module WB_InterConnect (D = $flatten\spi.$procmux$924_Y, Q = \spi.bit_irrdy, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$2074 ($sdff) from module WB_InterConnect (D = \io_dbus_wdata [4], Q = \spi.bit_irrdy).
Adding SRST signal on $flatten\spi.$procdff$1894 ($dff) from module WB_InterConnect (D = $flatten\spi.$procmux$929_Y, Q = \spi.bit_itrdy, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$2076 ($sdff) from module WB_InterConnect (D = \io_dbus_wdata [3], Q = \spi.bit_itrdy).
Adding SRST signal on $flatten\spi.$procdff$1893 ($dff) from module WB_InterConnect (D = $flatten\spi.$procmux$934_Y, Q = \spi.bit_itoe, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$2078 ($sdff) from module WB_InterConnect (D = \io_dbus_wdata [1], Q = \spi.bit_itoe).
Adding SRST signal on $flatten\spi.$procdff$1892 ($dff) from module WB_InterConnect (D = $flatten\spi.$procmux$939_Y, Q = \spi.bit_iroe, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$2080 ($sdff) from module WB_InterConnect (D = \io_dbus_wdata [0], Q = \spi.bit_iroe).
Adding SRST signal on $flatten\spi.$procdff$1891 ($dff) from module WB_InterConnect (D = $flatten\spi.$procmux$947_Y, Q = \spi.rx_latch_flag, rval = 1'0).
Adding SRST signal on $flatten\spi.$procdff$1890 ($dff) from module WB_InterConnect (D = \spi._GEN_48 [7:1], Q = \spi.tx_shift_data [7:1], rval = 7'0000000).
Adding SRST signal on $flatten\spi.$procdff$1890 ($dff) from module WB_InterConnect (D = \spi._GEN_46 [0], Q = \spi.tx_shift_data [0], rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$2084 ($sdff) from module WB_InterConnect (D = 1'0, Q = \spi.tx_shift_data [0]).
Setting constant 0-bit at position 0 on $auto$ff.cc:262:slice$2087 ($sdffe) from module WB_InterConnect.
Adding EN signal on $auto$ff.cc:262:slice$2083 ($sdff) from module WB_InterConnect (D = \spi._GEN_48 [7:1], Q = \spi.tx_shift_data [7:1]).
Adding SRST signal on $flatten\spi.$procdff$1889 ($dff) from module WB_InterConnect (D = \spi._GEN_19 [7:0], Q = \spi.rx_shift_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:262:slice$2097 ($sdff) from module WB_InterConnect (D = { \spi.rx_shift_data [6:0] \io_spi_miso }, Q = \spi.rx_shift_data).
Adding SRST signal on $flatten\spi.$procdff$1888 ($dff) from module WB_InterConnect (D = $flatten\spi.$procmux$952_Y, Q = \spi.reg_ssmask, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$2099 ($sdff) from module WB_InterConnect (D = \io_dbus_wdata [0], Q = \spi.reg_ssmask).
Adding SRST signal on $flatten\spi.$procdff$1887 ($dff) from module WB_InterConnect (D = $flatten\spi.$procmux$957_Y, Q = \spi.reg_txdata, rval = 8'00110101).
Adding EN signal on $auto$ff.cc:262:slice$2101 ($sdff) from module WB_InterConnect (D = \io_dbus_wdata [7:0], Q = \spi.reg_txdata).
Adding SRST signal on $flatten\spi.$procdff$1886 ($dff) from module WB_InterConnect (D = $flatten\spi.$procmux$962_Y, Q = \spi.reg_rxdata, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:262:slice$2103 ($sdff) from module WB_InterConnect (D = \spi.rx_shift_data, Q = \spi.reg_rxdata).
Adding SRST signal on $flatten\spi.$procdff$1885 ($dff) from module WB_InterConnect (D = $flatten\spi.$procmux$967_Y, Q = \spi.read_wait_done, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$2105 ($sdff) from module WB_InterConnect (D = 1'1, Q = \spi.read_wait_done).
Adding SRST signal on $flatten\spi.$procdff$1884 ($dff) from module WB_InterConnect (D = $flatten\spi.$procmux$980_Y, Q = \spi.mosi_r, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$2109 ($sdff) from module WB_InterConnect (D = $flatten\spi.$procmux$980_Y, Q = \spi.mosi_r).
Adding SRST signal on $flatten\spi.$procdff$1883 ($dff) from module WB_InterConnect (D = $flatten\spi.$procmux$985_Y, Q = \spi.sclk_r, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$2117 ($sdff) from module WB_InterConnect (D = \spi._T_204, Q = \spi.sclk_r).
Adding SRST signal on $flatten\spi.$procdff$1882 ($dff) from module WB_InterConnect (D = $flatten\spi.$procmux$990_Y, Q = \spi.ack_o, rval = 1'0).
Adding SRST signal on $flatten\spi.$procdff$1881 ($dff) from module WB_InterConnect (D = $flatten\spi.$procmux$1013_Y, Q = \spi.rd_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:262:slice$2122 ($sdff) from module WB_InterConnect (D = $flatten\spi.$procmux$1011_Y, Q = \spi.rd_data).
Adding SRST signal on $flatten\imem.\bmem.$procdff$1934 ($dff) from module WB_InterConnect (D = { $flatten\imem.\bmem.$procmux$1863_Y [4] $flatten\imem.\bmem.$procmux$1863_Y [1:0] }, Q = { \imem.bmem.bmem_data [4] \imem.bmem.bmem_data [1:0] }, rval = 3'000).
Adding SRST signal on $flatten\imem.\bmem.$procdff$1934 ($dff) from module WB_InterConnect (D = $flatten\imem.\bmem.$procmux$1827_Y [12], Q = \imem.bmem.bmem_data [12], rval = 1'0).
Adding SRST signal on $flatten\imem.\bmem.$procdff$1934 ($dff) from module WB_InterConnect (D = $flatten\imem.\bmem.$procmux$1824_Y [14], Q = \imem.bmem.bmem_data [14], rval = 1'0).
Adding SRST signal on $flatten\imem.\bmem.$procdff$1934 ($dff) from module WB_InterConnect (D = { $flatten\imem.\bmem.$procmux$1839_Y [11] $flatten\imem.\bmem.$procmux$1839_Y [9] }, Q = { \imem.bmem.bmem_data [11] \imem.bmem.bmem_data [9] }, rval = 2'00).
Adding SRST signal on $flatten\imem.\bmem.$procdff$1934 ($dff) from module WB_InterConnect (D = $flatten\imem.\bmem.$procmux$1848_Y [7], Q = \imem.bmem.bmem_data [7], rval = 1'0).
Adding SRST signal on $flatten\imem.\bmem.$procdff$1934 ($dff) from module WB_InterConnect (D = $flatten\imem.\bmem.$procmux$1851_Y [10], Q = \imem.bmem.bmem_data [10], rval = 1'0).
Adding SRST signal on $flatten\imem.\bmem.$procdff$1934 ($dff) from module WB_InterConnect (D = { $flatten\imem.\bmem.$procmux$1857_Y [31:23] $flatten\imem.\bmem.$procmux$1857_Y [21:15] $flatten\imem.\bmem.$procmux$1857_Y [13] $flatten\imem.\bmem.$procmux$1857_Y [8] }, Q = { \imem.bmem.bmem_data [31:23] \imem.bmem.bmem_data [21:15] \imem.bmem.bmem_data [13] \imem.bmem.bmem_data [8] }, rval = 18'000000000000000000).
Adding SRST signal on $flatten\imem.\bmem.$procdff$1934 ($dff) from module WB_InterConnect (D = { $flatten\imem.\bmem.$procmux$1860_Y [22] $flatten\imem.\bmem.$procmux$1860_Y [6:5] $flatten\imem.\bmem.$procmux$1860_Y [3:2] }, Q = { \imem.bmem.bmem_data [22] \imem.bmem.bmem_data [6:5] \imem.bmem.bmem_data [3:2] }, rval = 5'00000).
Adding EN signal on $auto$ff.cc:262:slice$2143 ($sdff) from module WB_InterConnect (D = { $flatten\imem.\bmem.$procmux$1860_Y [22] $flatten\imem.\bmem.$procmux$1860_Y [6:5] $flatten\imem.\bmem.$procmux$1860_Y [3:2] }, Q = { \imem.bmem.bmem_data [22] \imem.bmem.bmem_data [6:5] \imem.bmem.bmem_data [3:2] }).
Adding EN signal on $auto$ff.cc:262:slice$2140 ($sdff) from module WB_InterConnect (D = { $flatten\imem.\bmem.$procmux$1857_Y [31:23] $flatten\imem.\bmem.$procmux$1857_Y [21:15] $flatten\imem.\bmem.$procmux$1857_Y [13] $flatten\imem.\bmem.$procmux$1857_Y [8] }, Q = { \imem.bmem.bmem_data [31:23] \imem.bmem.bmem_data [21:15] \imem.bmem.bmem_data [13] \imem.bmem.bmem_data [8] }).
Adding EN signal on $auto$ff.cc:262:slice$2137 ($sdff) from module WB_InterConnect (D = $flatten\imem.\bmem.$procmux$1851_Y [10], Q = \imem.bmem.bmem_data [10]).
Adding EN signal on $auto$ff.cc:262:slice$2134 ($sdff) from module WB_InterConnect (D = $flatten\imem.\bmem.$procmux$1848_Y [7], Q = \imem.bmem.bmem_data [7]).
Adding EN signal on $auto$ff.cc:262:slice$2131 ($sdff) from module WB_InterConnect (D = { $flatten\imem.\bmem.$procmux$1839_Y [11] $flatten\imem.\bmem.$procmux$1839_Y [9] }, Q = { \imem.bmem.bmem_data [11] \imem.bmem.bmem_data [9] }).
Adding EN signal on $auto$ff.cc:262:slice$2128 ($sdff) from module WB_InterConnect (D = $flatten\imem.\bmem.$procmux$1824_Y [14], Q = \imem.bmem.bmem_data [14]).
Adding EN signal on $auto$ff.cc:262:slice$2125 ($sdff) from module WB_InterConnect (D = $flatten\imem.\bmem.$procmux$1827_Y [12], Q = \imem.bmem.bmem_data [12]).
Adding EN signal on $auto$ff.cc:262:slice$2124 ($sdff) from module WB_InterConnect (D = { $flatten\imem.\bmem.$procmux$1863_Y [4] $flatten\imem.\bmem.$procmux$1863_Y [1:0] }, Q = { \imem.bmem.bmem_data [4] \imem.bmem.bmem_data [1:0] }).
Adding SRST signal on $flatten\imem.$procdff$1933 ($dff) from module WB_InterConnect (D = \imem._T_80, Q = \imem.imem_ibus_valid, rval = 1'1).
Adding SRST signal on $flatten\imem.$procdff$1932 ($dff) from module WB_InterConnect (D = \imem._T_68, Q = \imem.bmem_ibus_sel, rval = 1'0).
Adding SRST signal on $flatten\imem.$procdff$1930 ($dff) from module WB_InterConnect (D = $flatten\imem.$procmux$1207_Y, Q = \imem.ack, rval = 1'1).
Adding EN signal on $auto$ff.cc:262:slice$2172 ($sdff) from module WB_InterConnect (D = \io_wbm_m2s_stb, Q = \imem.ack).
Adding SRST signal on $flatten\dmem.$procdff$1936 ($dff) from module WB_InterConnect (D = \io_wbm_m2s_stb, Q = \dmem.ack, rval = 1'0).
Adding SRST signal on $flatten\dmem.$procdff$1935 ($dff) from module WB_InterConnect (D = $flatten\dmem.$procmux$1871_Y, Q = \dmem.ack2, rval = 1'0).
Adding EN signal on $auto$ff.cc:262:slice$2175 ($sdff) from module WB_InterConnect (D = \io_wbm_m2s_stb, Q = \dmem.ack2).

6.9.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \WB_InterConnect..
Removed 101 unused cells and 101 unused wires.
<suppressed ~103 debug messages>

6.9.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module WB_InterConnect.
<suppressed ~17 debug messages>

6.9.9. Rerunning OPT passes. (Maybe there is more to do..)

6.9.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \WB_InterConnect..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~40 debug messages>

6.9.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \WB_InterConnect.
Performed a total of 0 changes.

6.9.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\WB_InterConnect'.
<suppressed ~39 debug messages>
Removed a total of 13 cells.

6.9.13. Executing OPT_DFF pass (perform DFF optimizations).

6.9.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \WB_InterConnect..
Removed 0 unused cells and 13 unused wires.
<suppressed ~1 debug messages>

6.9.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module WB_InterConnect.

6.9.16. Rerunning OPT passes. (Maybe there is more to do..)

6.9.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \WB_InterConnect..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~41 debug messages>

6.9.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \WB_InterConnect.
Performed a total of 0 changes.

6.9.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\WB_InterConnect'.
Removed a total of 0 cells.

6.9.20. Executing OPT_DFF pass (perform DFF optimizations).

6.9.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \WB_InterConnect..

6.9.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module WB_InterConnect.

6.9.23. Finished OPT passes. (There is nothing left to do.)

6.10. Executing WREDUCE pass (reducing word size of cells).
Removed top 3 bits (of 4) from port B of cell WB_InterConnect.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:4060$766 ($eq).
Removed top 2 bits (of 4) from port B of cell WB_InterConnect.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:4061$767 ($eq).
Removed top 2 bits (of 4) from port B of cell WB_InterConnect.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:4062$768 ($eq).
Removed top 1 bits (of 4) from port B of cell WB_InterConnect.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:4063$769 ($eq).
Removed top 2 bits (of 4) from port B of cell WB_InterConnect.$flatten\dmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:81$11 ($eq).
Removed top 1 bits (of 4) from port B of cell WB_InterConnect.$flatten\dmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:77$9 ($eq).
Removed top 2 bits (of 4) from port B of cell WB_InterConnect.$flatten\dmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:75$8 ($eq).
Removed top 7 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:604$26 ($eq).
Removed top 6 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:605$27 ($eq).
Removed top 6 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:606$28 ($eq).
Removed top 5 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:607$29 ($eq).
Removed top 5 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:608$30 ($eq).
Removed top 5 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:609$31 ($eq).
Removed top 5 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:610$32 ($eq).
Removed top 4 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:611$33 ($eq).
Removed top 4 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:612$34 ($eq).
Removed top 4 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:613$35 ($eq).
Removed top 4 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:614$36 ($eq).
Removed top 4 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:615$37 ($eq).
Removed top 4 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:616$38 ($eq).
Removed top 4 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:617$39 ($eq).
Removed top 4 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:618$40 ($eq).
Removed top 3 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:619$41 ($eq).
Removed top 3 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:620$42 ($eq).
Removed top 3 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:621$43 ($eq).
Removed top 3 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:622$44 ($eq).
Removed top 3 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:623$45 ($eq).
Removed top 3 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:624$46 ($eq).
Removed top 3 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:625$47 ($eq).
Removed top 3 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:626$48 ($eq).
Removed top 3 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:627$49 ($eq).
Removed top 3 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:628$50 ($eq).
Removed top 3 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:629$51 ($eq).
Removed top 3 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:630$52 ($eq).
Removed top 3 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:631$53 ($eq).
Removed top 3 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:632$54 ($eq).
Removed top 3 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:633$55 ($eq).
Removed top 3 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:634$56 ($eq).
Removed top 2 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:635$57 ($eq).
Removed top 2 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:636$58 ($eq).
Removed top 2 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:637$59 ($eq).
Removed top 2 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:638$60 ($eq).
Removed top 2 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:639$61 ($eq).
Removed top 2 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:640$62 ($eq).
Removed top 2 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:641$63 ($eq).
Removed top 2 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:642$64 ($eq).
Removed top 2 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:643$65 ($eq).
Removed top 2 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:644$66 ($eq).
Removed top 2 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:645$67 ($eq).
Removed top 2 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:646$68 ($eq).
Removed top 2 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:647$69 ($eq).
Removed top 2 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:648$70 ($eq).
Removed top 2 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:649$71 ($eq).
Removed top 2 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:650$72 ($eq).
Removed top 2 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:651$73 ($eq).
Removed top 2 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:652$74 ($eq).
Removed top 2 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:653$75 ($eq).
Removed top 2 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:654$76 ($eq).
Removed top 2 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:655$77 ($eq).
Removed top 2 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:656$78 ($eq).
Removed top 2 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:657$79 ($eq).
Removed top 2 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:658$80 ($eq).
Removed top 2 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:659$81 ($eq).
Removed top 2 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:660$82 ($eq).
Removed top 2 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:661$83 ($eq).
Removed top 2 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:662$84 ($eq).
Removed top 2 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:663$85 ($eq).
Removed top 2 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:664$86 ($eq).
Removed top 2 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:665$87 ($eq).
Removed top 2 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:666$88 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:667$89 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:668$90 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:669$91 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:670$92 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:671$93 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:672$94 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:673$95 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:674$96 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:675$97 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:676$98 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:677$99 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:678$100 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:679$101 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:680$102 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:681$103 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:682$104 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:683$105 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:684$106 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:685$107 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:686$108 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:687$109 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:688$110 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:689$111 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:690$112 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:691$113 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:692$114 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:693$115 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:694$116 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:695$117 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:696$118 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:697$119 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:698$120 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:699$121 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:700$122 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:701$123 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:702$124 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:703$125 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:704$126 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:705$127 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:706$128 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:707$129 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:708$130 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:709$131 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:710$132 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:711$133 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:712$134 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:713$135 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:714$136 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:715$137 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:716$138 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:717$139 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:718$140 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:719$141 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:720$142 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:721$143 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:722$144 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:723$145 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:724$146 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:725$147 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:726$148 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:727$149 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:728$150 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:729$151 ($eq).
Removed top 1 bits (of 8) from port A of cell WB_InterConnect.$flatten\imem.\bmem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:730$152 ($eq).
Removed cell WB_InterConnect.$flatten\imem.\bmem.$procmux$1212 ($mux).
Removed top 6 bits (of 32) from mux cell WB_InterConnect.$flatten\imem.\bmem.$procmux$1215 ($mux).
Removed top 6 bits (of 32) from mux cell WB_InterConnect.$flatten\imem.\bmem.$procmux$1218 ($mux).
Removed top 6 bits (of 32) from mux cell WB_InterConnect.$flatten\imem.\bmem.$procmux$1221 ($mux).
Removed top 6 bits (of 32) from mux cell WB_InterConnect.$flatten\imem.\bmem.$procmux$1224 ($mux).
Removed top 27 bits (of 32) from mux cell WB_InterConnect.$flatten\imem.\bmem.$procmux$1863 ($mux).
Removed top 3 bits (of 4) from port B of cell WB_InterConnect.$flatten\imem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2041$476 ($eq).
Removed top 1 bits (of 4) from port B of cell WB_InterConnect.$flatten\imem.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2029$465 ($eq).
Removed top 2 bits (of 4) from mux cell WB_InterConnect.$flatten\wbm_dbus.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2195$511 ($mux).
Removed top 1 bits (of 2) from port B of cell WB_InterConnect.$flatten\wbm_dbus.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2194$510 ($eq).
Removed top 1 bits (of 3) from port B of cell WB_InterConnect.$flatten\wbm_dbus.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2189$505 ($eq).
Removed top 1 bits (of 3) from port B of cell WB_InterConnect.$flatten\wbm_dbus.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2184$501 ($eq).
Removed top 2 bits (of 3) from port B of cell WB_InterConnect.$flatten\wbm_dbus.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2183$500 ($eq).
Removed top 3 bits (of 4) from mux cell WB_InterConnect.$flatten\wbm_dbus.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2179$497 ($mux).
Removed top 1 bits (of 2) from port B of cell WB_InterConnect.$flatten\wbm_dbus.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2176$494 ($eq).
Removed top 1 bits (of 2) from port B of cell WB_InterConnect.$auto$opt_dff.cc:198:make_patterns_logic$1953 ($ne).
Removed top 2 bits (of 10) from port A of cell WB_InterConnect.$flatten\uart.\rxm.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2444$540 ($sub).
Removed top 9 bits (of 10) from port B of cell WB_InterConnect.$flatten\uart.\rxm.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2444$540 ($sub).
Removed top 2 bits (of 11) from port Y of cell WB_InterConnect.$flatten\uart.\rxm.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2444$540 ($sub).
Removed top 9 bits (of 10) from port B of cell WB_InterConnect.$flatten\uart.\rxm.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2447$541 ($sub).
Removed top 1 bits (of 11) from port Y of cell WB_InterConnect.$flatten\uart.\rxm.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2447$541 ($sub).
Removed top 2 bits (of 9) from port B of cell WB_InterConnect.$flatten\uart.\rxm.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2453$544 ($eq).
Removed top 8 bits (of 9) from port B of cell WB_InterConnect.$flatten\uart.\rxm.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2457$548 ($add).
Removed top 3 bits (of 4) from port B of cell WB_InterConnect.$flatten\uart.\rxm.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2465$556 ($sub).
Removed top 1 bits (of 5) from port Y of cell WB_InterConnect.$flatten\uart.\rxm.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2465$556 ($sub).
Removed cell WB_InterConnect.$flatten\uart.\rxm.$procmux$1109 ($mux).
Removed cell WB_InterConnect.$flatten\uart.\rxm.$procmux$1111 ($mux).
Removed cell WB_InterConnect.$flatten\uart.\rxm.$procmux$1116 ($mux).
Removed cell WB_InterConnect.$flatten\uart.\rxm.$procmux$1123 ($mux).
Removed cell WB_InterConnect.$flatten\uart.\rxm.$procmux$1128 ($mux).
Removed cell WB_InterConnect.$flatten\uart.\rxm.$procmux$1130 ($mux).
Removed cell WB_InterConnect.$flatten\uart.\rxm.$procmux$1154 ($mux).
Removed cell WB_InterConnect.$flatten\uart.\rxm.$procmux$1156 ($mux).
Removed cell WB_InterConnect.$flatten\uart.\rxm.$procmux$1158 ($mux).
Removed top 9 bits (of 10) from port B of cell WB_InterConnect.$flatten\uart.\txm.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2263$527 ($sub).
Removed top 1 bits (of 11) from port Y of cell WB_InterConnect.$flatten\uart.\txm.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2263$527 ($sub).
Removed top 3 bits (of 4) from port B of cell WB_InterConnect.$flatten\uart.\txm.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2267$529 ($sub).
Removed top 1 bits (of 5) from port Y of cell WB_InterConnect.$flatten\uart.\txm.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2267$529 ($sub).
Removed top 7 bits (of 8) from mux cell WB_InterConnect.$flatten\uart.$procmux$1028 ($mux).
Removed top 6 bits (of 8) from mux cell WB_InterConnect.$flatten\uart.$procmux$1025 ($mux).
Removed top 2 bits (of 10) from mux cell WB_InterConnect.$flatten\uart.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2777$600 ($mux).
Removed top 2 bits (of 10) from mux cell WB_InterConnect.$flatten\uart.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2776$599 ($mux).
Removed top 6 bits (of 8) from port B of cell WB_InterConnect.$flatten\uart.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2762$585 ($eq).
Removed top 1 bits (of 3) from port B of cell WB_InterConnect.$auto$opt_dff.cc:198:make_patterns_logic$2092 ($ne).
Removed top 1 bits (of 2) from port B of cell WB_InterConnect.$auto$opt_dff.cc:198:make_patterns_logic$2061 ($ne).
Removed top 5 bits (of 6) from port B of cell WB_InterConnect.$auto$opt_dff.cc:198:make_patterns_logic$2034 ($ne).
Removed top 7 bits (of 8) from mux cell WB_InterConnect.$flatten\spi.$procmux$999 ($mux).
Removed cell WB_InterConnect.$flatten\spi.$procmux$977 ($mux).
Removed cell WB_InterConnect.$flatten\spi.$procmux$975 ($mux).
Removed cell WB_InterConnect.$flatten\spi.$procmux$901 ($mux).
Removed cell WB_InterConnect.$flatten\spi.$procmux$894 ($mux).
Removed cell WB_InterConnect.$flatten\spi.$procmux$873 ($mux).
Removed cell WB_InterConnect.$flatten\spi.$procmux$851 ($mux).
Removed top 2 bits (of 3) from mux cell WB_InterConnect.$flatten\spi.$procmux$844 ($mux).
Removed top 2 bits (of 3) from mux cell WB_InterConnect.$flatten\spi.$procmux$835 ($mux).
Removed cell WB_InterConnect.$flatten\spi.$procmux$823 ($mux).
Removed top 1 bits (of 9) from mux cell WB_InterConnect.$flatten\spi.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3325$741 ($mux).
Removed top 8 bits (of 9) from mux cell WB_InterConnect.$flatten\spi.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3323$739 ($mux).
Removed cell WB_InterConnect.$flatten\spi.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3321$737 ($mux).
Removed top 5 bits (of 6) from port B of cell WB_InterConnect.$flatten\spi.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3311$731 ($add).
Removed top 4 bits (of 6) from port B of cell WB_InterConnect.$flatten\spi.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3292$712 ($eq).
Removed top 3 bits (of 6) from port B of cell WB_InterConnect.$flatten\spi.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3285$705 ($eq).
Removed top 5 bits (of 6) from port B of cell WB_InterConnect.$flatten\spi.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3282$702 ($eq).
Removed top 1 bits (of 3) from port B of cell WB_InterConnect.$flatten\spi.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3281$701 ($eq).
Removed top 4 bits (of 5) from port B of cell WB_InterConnect.$flatten\spi.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3278$698 ($add).
Removed top 1 bits (of 3) from port B of cell WB_InterConnect.$flatten\spi.$ne$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3271$691 ($ne).
Removed top 1 bits (of 3) from port B of cell WB_InterConnect.$flatten\spi.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3270$690 ($eq).
Removed top 3 bits (of 5) from port B of cell WB_InterConnect.$flatten\spi.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3261$682 ($eq).
Removed top 1 bits (of 3) from port B of cell WB_InterConnect.$flatten\spi.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3260$681 ($eq).
Removed top 2 bits (of 3) from port B of cell WB_InterConnect.$flatten\spi.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3249$670 ($eq).
Removed top 5 bits (of 8) from port B of cell WB_InterConnect.$flatten\spi.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3209$640 ($eq).
Removed top 5 bits (of 8) from port B of cell WB_InterConnect.$flatten\spi.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3207$638 ($eq).
Removed top 6 bits (of 8) from port B of cell WB_InterConnect.$flatten\spi.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3205$636 ($eq).
Removed top 7 bits (of 8) from port B of cell WB_InterConnect.$flatten\spi.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3203$634 ($eq).
Removed top 9 bits (of 32) from mux cell WB_InterConnect.$flatten\imem.\bmem.$procmux$1860 ($mux).
Removed top 6 bits (of 32) from wire WB_InterConnect.$flatten\imem.\bmem.$procmux$1215_Y.
Removed top 6 bits (of 32) from wire WB_InterConnect.$flatten\imem.\bmem.$procmux$1218_Y.
Removed top 9 bits (of 32) from wire WB_InterConnect.$flatten\imem.\bmem.$procmux$1860_Y.
Removed top 2 bits (of 3) from wire WB_InterConnect.$flatten\spi.$procmux$835_Y.
Removed top 2 bits (of 3) from wire WB_InterConnect.$flatten\spi.$procmux$844_Y.
Removed top 7 bits (of 8) from wire WB_InterConnect.$flatten\spi.$procmux$999_Y.
Removed top 6 bits (of 8) from wire WB_InterConnect.$flatten\uart.$procmux$1025_Y.
Removed top 7 bits (of 8) from wire WB_InterConnect.$flatten\uart.$procmux$1028_Y.

6.11. Executing PEEPOPT pass (run peephole optimizers).

6.12. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \WB_InterConnect..
Removed 0 unused cells and 25 unused wires.
<suppressed ~1 debug messages>

6.13. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module WB_InterConnect:
  creating $macc model for $flatten\spi.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3278$698 ($add).
  creating $macc model for $flatten\spi.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3311$731 ($add).
  creating $macc model for $flatten\uart.\rxm.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2457$548 ($add).
  creating $macc model for $flatten\uart.\rxm.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2444$540 ($sub).
  creating $macc model for $flatten\uart.\rxm.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2447$541 ($sub).
  creating $macc model for $flatten\uart.\rxm.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2465$556 ($sub).
  creating $macc model for $flatten\uart.\txm.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2263$527 ($sub).
  creating $macc model for $flatten\uart.\txm.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2267$529 ($sub).
  creating $alu model for $macc $flatten\uart.\txm.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2267$529.
  creating $alu model for $macc $flatten\uart.\txm.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2263$527.
  creating $alu model for $macc $flatten\uart.\rxm.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2465$556.
  creating $alu model for $macc $flatten\uart.\rxm.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2447$541.
  creating $alu model for $macc $flatten\uart.\rxm.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2444$540.
  creating $alu model for $macc $flatten\uart.\rxm.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2457$548.
  creating $alu model for $macc $flatten\spi.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3311$731.
  creating $alu model for $macc $flatten\spi.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3278$698.
  creating $alu cell for $flatten\spi.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3278$698: $auto$alumacc.cc:485:replace_alu$2185
  creating $alu cell for $flatten\spi.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3311$731: $auto$alumacc.cc:485:replace_alu$2188
  creating $alu cell for $flatten\uart.\rxm.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2457$548: $auto$alumacc.cc:485:replace_alu$2191
  creating $alu cell for $flatten\uart.\rxm.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2444$540: $auto$alumacc.cc:485:replace_alu$2194
  creating $alu cell for $flatten\uart.\rxm.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2447$541: $auto$alumacc.cc:485:replace_alu$2197
  creating $alu cell for $flatten\uart.\rxm.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2465$556: $auto$alumacc.cc:485:replace_alu$2200
  creating $alu cell for $flatten\uart.\txm.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2263$527: $auto$alumacc.cc:485:replace_alu$2203
  creating $alu cell for $flatten\uart.\txm.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2267$529: $auto$alumacc.cc:485:replace_alu$2206
  created 8 $alu and 0 $macc cells.

6.14. Executing SHARE pass (SAT-based resource sharing).

6.15. Executing OPT pass (performing simple optimizations).

6.15.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module WB_InterConnect.
<suppressed ~1 debug messages>

6.15.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\WB_InterConnect'.
Removed a total of 0 cells.

6.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \WB_InterConnect..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~39 debug messages>

6.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \WB_InterConnect.
Performed a total of 0 changes.

6.15.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\WB_InterConnect'.
<suppressed ~3 debug messages>
Removed a total of 1 cells.

6.15.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$ff.cc:262:slice$1960 ($dffe) from module WB_InterConnect (D = \uart.rxm._T_46, Q = \uart.rxm.data_count, rval = 4'1000).

6.15.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \WB_InterConnect..
Removed 1 unused cells and 2 unused wires.
<suppressed ~2 debug messages>

6.15.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module WB_InterConnect.

6.15.9. Rerunning OPT passes. (Maybe there is more to do..)

6.15.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \WB_InterConnect..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~37 debug messages>

6.15.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \WB_InterConnect.
Performed a total of 0 changes.

6.15.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\WB_InterConnect'.
Removed a total of 0 cells.

6.15.13. Executing OPT_DFF pass (perform DFF optimizations).

6.15.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \WB_InterConnect..

6.15.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module WB_InterConnect.

6.15.16. Finished OPT passes. (There is nothing left to do.)

6.16. Executing MEMORY pass.

6.16.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.

6.16.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
Performed a total of 0 transformations.

6.16.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).

6.16.4. Executing MEMORY_DFF pass (merging $dff cells to $memrd).

6.16.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \WB_InterConnect..

6.16.6. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).

6.16.7. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
Performed a total of 0 transformations.

6.16.8. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \WB_InterConnect..

6.16.9. Executing MEMORY_COLLECT pass (generating $mem cells).

6.17. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \WB_InterConnect..

6.18. Executing OPT pass (performing simple optimizations).

6.18.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module WB_InterConnect.
<suppressed ~22 debug messages>

6.18.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\WB_InterConnect'.
<suppressed ~3 debug messages>
Removed a total of 1 cells.

6.18.3. Executing OPT_DFF pass (perform DFF optimizations).

6.18.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \WB_InterConnect..
Removed 0 unused cells and 9 unused wires.
<suppressed ~1 debug messages>

6.18.5. Finished fast OPT passes.

6.19. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).

6.20. Executing OPT pass (performing simple optimizations).

6.20.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module WB_InterConnect.

6.20.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\WB_InterConnect'.
Removed a total of 0 cells.

6.20.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \WB_InterConnect..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~28 debug messages>

6.20.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1215:
      Old ports: A=26'00000000001000000001100111, B=26'11000000010000000100010011, Y=$auto$wreduce.cc:454:run$2177 [25:0]
      New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:454:run$2177 [4] $auto$wreduce.cc:454:run$2177 [2] }
      New connections: { $auto$wreduce.cc:454:run$2177 [25:5] $auto$wreduce.cc:454:run$2177 [3] $auto$wreduce.cc:454:run$2177 [1:0] } = { $auto$wreduce.cc:454:run$2177 [4] $auto$wreduce.cc:454:run$2177 [4] 7'0000000 $auto$wreduce.cc:454:run$2177 [4] $auto$wreduce.cc:454:run$2177 [2] 6'000000 $auto$wreduce.cc:454:run$2177 [4] 1'0 $auto$wreduce.cc:454:run$2177 [2] $auto$wreduce.cc:454:run$2177 [2] 3'011 }
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1227:
      Old ports: A={ 6'000000 $flatten\imem.\bmem.$procmux$1224_Y [25:0] }, B=32'11111100000001111101110011100011, Y=$flatten\imem.\bmem.$procmux$1227_Y
      New ports: A={ 1'0 $flatten\imem.\bmem.$procmux$1224_Y [25:0] }, B=27'100000001111101110011100011, Y=$flatten\imem.\bmem.$procmux$1227_Y [26:0]
      New connections: $flatten\imem.\bmem.$procmux$1227_Y [31:27] = { $flatten\imem.\bmem.$procmux$1227_Y [26] $flatten\imem.\bmem.$procmux$1227_Y [26] $flatten\imem.\bmem.$procmux$1227_Y [26] $flatten\imem.\bmem.$procmux$1227_Y [26] $flatten\imem.\bmem.$procmux$1227_Y [26] }
    Consolidated identical input bits for $mux cell $flatten\spi.$procmux$1002:
      Old ports: A={ 7'0000000 $auto$wreduce.cc:454:run$2182 [0] }, B={ \spi.bit_sso \spi.bit_en_io \spi.bit_ie \spi.bit_irrdy \spi.bit_itrdy 1'0 \spi.bit_itoe \spi.bit_iroe }, Y=$flatten\spi.$procmux$1002_Y
      New ports: A={ 6'000000 $auto$wreduce.cc:454:run$2182 [0] }, B={ \spi.bit_sso \spi.bit_en_io \spi.bit_ie \spi.bit_irrdy \spi.bit_itrdy \spi.bit_itoe \spi.bit_iroe }, Y={ $flatten\spi.$procmux$1002_Y [7:3] $flatten\spi.$procmux$1002_Y [1:0] }
      New connections: $flatten\spi.$procmux$1002_Y [2] = 1'0
    Consolidated identical input bits for $mux cell $flatten\spi.$procmux$818:
      Old ports: A=3'101, B=3'000, Y=$flatten\spi.$procmux$818_Y
      New ports: A=1'1, B=1'0, Y=$flatten\spi.$procmux$818_Y [0]
      New connections: $flatten\spi.$procmux$818_Y [2:1] = { $flatten\spi.$procmux$818_Y [0] 1'0 }
    Consolidated identical input bits for $mux cell $flatten\spi.$procmux$829:
      Old ports: A=3'011, B=3'100, Y=$flatten\spi.$procmux$829_Y
      New ports: A=2'01, B=2'10, Y={ $flatten\spi.$procmux$829_Y [2] $flatten\spi.$procmux$829_Y [0] }
      New connections: $flatten\spi.$procmux$829_Y [1] = $flatten\spi.$procmux$829_Y [0]
    Consolidated identical input bits for $mux cell $flatten\spi.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:3325$741:
      Old ports: A={ \spi.tx_shift_data [6:1] 2'00 }, B={ \spi.reg_txdata [6:0] 1'0 }, Y=\spi._GEN_48 [7:0]
      New ports: A={ \spi.tx_shift_data [6:1] 1'0 }, B=\spi.reg_txdata [6:0], Y=\spi._GEN_48 [7:1]
      New connections: \spi._GEN_48 [0] = 1'0
    Consolidated identical input bits for $mux cell $flatten\wbm_dbus.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2180$498:
      Old ports: A={ 3'000 \wbm_dbus._T_41 }, B=4'0011, Y=\wbm_dbus._GEN_1
      New ports: A={ 1'0 \wbm_dbus._T_41 }, B=2'11, Y=\wbm_dbus._GEN_1 [1:0]
      New connections: \wbm_dbus._GEN_1 [3:2] = 2'00
    Consolidated identical input bits for $mux cell $flatten\wbm_dbus.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2188$504:
      Old ports: A=4'0011, B=4'1100, Y=\wbm_dbus._T_49
      New ports: A=2'01, B=2'10, Y={ \wbm_dbus._T_49 [2] \wbm_dbus._T_49 [0] }
      New connections: { \wbm_dbus._T_49 [3] \wbm_dbus._T_49 [1] } = { \wbm_dbus._T_49 [2] \wbm_dbus._T_49 [0] }
    Consolidated identical input bits for $mux cell $flatten\wbm_dbus.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2196$512:
      Old ports: A={ 2'00 \wbm_dbus._GEN_3 [1:0] }, B=4'0100, Y=\wbm_dbus._GEN_4
      New ports: A={ 1'0 \wbm_dbus._GEN_3 [1:0] }, B=3'100, Y=\wbm_dbus._GEN_4 [2:0]
      New connections: \wbm_dbus._GEN_4 [3] = 1'0
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1218:
      Old ports: A=$auto$wreduce.cc:454:run$2177 [25:0], B=26'10100000010010010000000011, Y=$auto$wreduce.cc:454:run$2178 [25:0]
      New ports: A={ $auto$wreduce.cc:454:run$2177 [4] 1'0 $auto$wreduce.cc:454:run$2177 [4] $auto$wreduce.cc:454:run$2177 [2] }, B=4'1100, Y={ $auto$wreduce.cc:454:run$2178 [16] $auto$wreduce.cc:454:run$2178 [10] $auto$wreduce.cc:454:run$2178 [4] $auto$wreduce.cc:454:run$2178 [2] }
      New connections: { $auto$wreduce.cc:454:run$2178 [25:17] $auto$wreduce.cc:454:run$2178 [15:11] $auto$wreduce.cc:454:run$2178 [9:5] $auto$wreduce.cc:454:run$2178 [3] $auto$wreduce.cc:454:run$2178 [1:0] } = { $auto$wreduce.cc:454:run$2178 [16] $auto$wreduce.cc:454:run$2178 [4] $auto$wreduce.cc:454:run$2178 [10] 6'000000 $auto$wreduce.cc:454:run$2178 [2] 1'0 $auto$wreduce.cc:454:run$2178 [10] 3'000 $auto$wreduce.cc:454:run$2178 [4] 1'0 $auto$wreduce.cc:454:run$2178 [2] $auto$wreduce.cc:454:run$2178 [2] 3'011 }
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1230:
      Old ports: A=$flatten\imem.\bmem.$procmux$1227_Y, B=32'11111110110001000010011110000011, Y=$flatten\imem.\bmem.$procmux$1230_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1227_Y [26:0], B=27'110110001000010011110000011, Y=$flatten\imem.\bmem.$procmux$1230_Y [26:0]
      New connections: $flatten\imem.\bmem.$procmux$1230_Y [31:27] = { $flatten\imem.\bmem.$procmux$1230_Y [26] $flatten\imem.\bmem.$procmux$1230_Y [26] $flatten\imem.\bmem.$procmux$1230_Y [26] $flatten\imem.\bmem.$procmux$1230_Y [26] $flatten\imem.\bmem.$procmux$1230_Y [26] }
    Consolidated identical input bits for $mux cell $flatten\spi.$procmux$820:
      Old ports: A=3'000, B=$flatten\spi.$procmux$818_Y, Y=$flatten\spi.$procmux$820_Y
      New ports: A=1'0, B=$flatten\spi.$procmux$818_Y [0], Y=$flatten\spi.$procmux$820_Y [0]
      New connections: $flatten\spi.$procmux$820_Y [2:1] = { $flatten\spi.$procmux$820_Y [0] 1'0 }
    Consolidated identical input bits for $mux cell $flatten\wbm_dbus.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/../../verilog/rtl/WB_InterConnect.v:2181$499:
      Old ports: A=\wbm_dbus._GEN_1, B=4'1111, Y=\wbm_dbus.st_sel_vec
      New ports: A={ 1'0 \wbm_dbus._GEN_1 [1:0] }, B=3'111, Y=\wbm_dbus.st_sel_vec [2:0]
      New connections: \wbm_dbus.st_sel_vec [3] = \wbm_dbus.st_sel_vec [2]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1221:
      Old ports: A=$auto$wreduce.cc:454:run$2178 [25:0], B=26'10110000010010000010000011, Y=$flatten\imem.\bmem.$procmux$1221_Y [25:0]
      New ports: A={ $auto$wreduce.cc:454:run$2178 [16] $auto$wreduce.cc:454:run$2178 [10] $auto$wreduce.cc:454:run$2178 [10] 1'0 $auto$wreduce.cc:454:run$2178 [4] $auto$wreduce.cc:454:run$2178 [2] }, B=6'110100, Y={ $flatten\imem.\bmem.$procmux$1221_Y [16] $flatten\imem.\bmem.$procmux$1221_Y [13] $flatten\imem.\bmem.$procmux$1221_Y [10] $flatten\imem.\bmem.$procmux$1221_Y [7] $flatten\imem.\bmem.$procmux$1221_Y [4] $flatten\imem.\bmem.$procmux$1221_Y [2] }
      New connections: { $flatten\imem.\bmem.$procmux$1221_Y [25:17] $flatten\imem.\bmem.$procmux$1221_Y [15:14] $flatten\imem.\bmem.$procmux$1221_Y [12:11] $flatten\imem.\bmem.$procmux$1221_Y [9:8] $flatten\imem.\bmem.$procmux$1221_Y [6:5] $flatten\imem.\bmem.$procmux$1221_Y [3] $flatten\imem.\bmem.$procmux$1221_Y [1:0] } = { $flatten\imem.\bmem.$procmux$1221_Y [16] $flatten\imem.\bmem.$procmux$1221_Y [4] $flatten\imem.\bmem.$procmux$1221_Y [13] $flatten\imem.\bmem.$procmux$1221_Y [7] 5'00000 $flatten\imem.\bmem.$procmux$1221_Y [2] 4'0000 $flatten\imem.\bmem.$procmux$1221_Y [4] $flatten\imem.\bmem.$procmux$1221_Y [2] $flatten\imem.\bmem.$procmux$1221_Y [2] 3'011 }
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1233:
      Old ports: A=$flatten\imem.\bmem.$procmux$1230_Y, B=32'11111110111101000010011000100011, Y=$flatten\imem.\bmem.$procmux$1233_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1230_Y [26:0], B=27'110111101000010011000100011, Y=$flatten\imem.\bmem.$procmux$1233_Y [26:0]
      New connections: $flatten\imem.\bmem.$procmux$1233_Y [31:27] = { $flatten\imem.\bmem.$procmux$1233_Y [26] $flatten\imem.\bmem.$procmux$1233_Y [26] $flatten\imem.\bmem.$procmux$1233_Y [26] $flatten\imem.\bmem.$procmux$1233_Y [26] $flatten\imem.\bmem.$procmux$1233_Y [26] }
    Consolidated identical input bits for $mux cell $flatten\spi.$procmux$825:
      Old ports: A=$flatten\spi.$procmux$820_Y, B=3'101, Y=$flatten\spi.$procmux$825_Y
      New ports: A=$flatten\spi.$procmux$820_Y [0], B=1'1, Y=$flatten\spi.$procmux$825_Y [0]
      New connections: $flatten\spi.$procmux$825_Y [2:1] = { $flatten\spi.$procmux$825_Y [0] 1'0 }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1224:
      Old ports: A=$flatten\imem.\bmem.$procmux$1221_Y [25:0], B=26'00000000000000000000010011, Y=$flatten\imem.\bmem.$procmux$1224_Y [25:0]
      New ports: A={ $flatten\imem.\bmem.$procmux$1221_Y [16] $flatten\imem.\bmem.$procmux$1221_Y [13] $flatten\imem.\bmem.$procmux$1221_Y [10] $flatten\imem.\bmem.$procmux$1221_Y [4] $flatten\imem.\bmem.$procmux$1221_Y [7] $flatten\imem.\bmem.$procmux$1221_Y [4] $flatten\imem.\bmem.$procmux$1221_Y [2] }, B=7'0000010, Y={ $flatten\imem.\bmem.$procmux$1224_Y [16] $flatten\imem.\bmem.$procmux$1224_Y [13] $flatten\imem.\bmem.$procmux$1224_Y [10] $flatten\imem.\bmem.$procmux$1224_Y [8:7] $flatten\imem.\bmem.$procmux$1224_Y [4] $flatten\imem.\bmem.$procmux$1224_Y [2] }
      New connections: { $flatten\imem.\bmem.$procmux$1224_Y [25:17] $flatten\imem.\bmem.$procmux$1224_Y [15:14] $flatten\imem.\bmem.$procmux$1224_Y [12:11] $flatten\imem.\bmem.$procmux$1224_Y [9] $flatten\imem.\bmem.$procmux$1224_Y [6:5] $flatten\imem.\bmem.$procmux$1224_Y [3] $flatten\imem.\bmem.$procmux$1224_Y [1:0] } = { $flatten\imem.\bmem.$procmux$1224_Y [16] $flatten\imem.\bmem.$procmux$1224_Y [8] $flatten\imem.\bmem.$procmux$1224_Y [13] $flatten\imem.\bmem.$procmux$1224_Y [7] 5'00000 $flatten\imem.\bmem.$procmux$1224_Y [2] 4'0000 $flatten\imem.\bmem.$procmux$1224_Y [2] $flatten\imem.\bmem.$procmux$1224_Y [2] 3'011 }
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1236:
      Old ports: A=$flatten\imem.\bmem.$procmux$1233_Y, B=32'11111111111101111000011110010011, Y=$flatten\imem.\bmem.$procmux$1236_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1233_Y [26:0], B=27'111111101111000011110010011, Y=$flatten\imem.\bmem.$procmux$1236_Y [26:0]
      New connections: $flatten\imem.\bmem.$procmux$1236_Y [31:27] = { $flatten\imem.\bmem.$procmux$1236_Y [26] $flatten\imem.\bmem.$procmux$1236_Y [26] $flatten\imem.\bmem.$procmux$1236_Y [26] $flatten\imem.\bmem.$procmux$1236_Y [26] $flatten\imem.\bmem.$procmux$1236_Y [26] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1227:
      Old ports: A={ 1'0 $flatten\imem.\bmem.$procmux$1224_Y [25:0] }, B=27'100000001111101110011100011, Y=$flatten\imem.\bmem.$procmux$1227_Y [26:0]
      New ports: A={ $flatten\imem.\bmem.$procmux$1224_Y [16] $flatten\imem.\bmem.$procmux$1224_Y [7] $flatten\imem.\bmem.$procmux$1224_Y [16] $flatten\imem.\bmem.$procmux$1224_Y [13] 1'0 $flatten\imem.\bmem.$procmux$1224_Y [10] $flatten\imem.\bmem.$procmux$1224_Y [8:7] $flatten\imem.\bmem.$procmux$1224_Y [2] $flatten\imem.\bmem.$procmux$1224_Y [4] $flatten\imem.\bmem.$procmux$1224_Y [2] }, B=11'00101101100, Y={ $flatten\imem.\bmem.$procmux$1227_Y [25] $flatten\imem.\bmem.$procmux$1227_Y [22] $flatten\imem.\bmem.$procmux$1227_Y [16] $flatten\imem.\bmem.$procmux$1227_Y [13] $flatten\imem.\bmem.$procmux$1227_Y [11:10] $flatten\imem.\bmem.$procmux$1227_Y [8:7] $flatten\imem.\bmem.$procmux$1227_Y [5:4] $flatten\imem.\bmem.$procmux$1227_Y [2] }
      New connections: { $flatten\imem.\bmem.$procmux$1227_Y [26] $flatten\imem.\bmem.$procmux$1227_Y [24:23] $flatten\imem.\bmem.$procmux$1227_Y [21:17] $flatten\imem.\bmem.$procmux$1227_Y [15:14] $flatten\imem.\bmem.$procmux$1227_Y [12] $flatten\imem.\bmem.$procmux$1227_Y [9] $flatten\imem.\bmem.$procmux$1227_Y [6] $flatten\imem.\bmem.$procmux$1227_Y [3] $flatten\imem.\bmem.$procmux$1227_Y [1:0] } = { $flatten\imem.\bmem.$procmux$1227_Y [11] $flatten\imem.\bmem.$procmux$1227_Y [8] $flatten\imem.\bmem.$procmux$1227_Y [13] 3'000 $flatten\imem.\bmem.$procmux$1227_Y [11] $flatten\imem.\bmem.$procmux$1227_Y [11] $flatten\imem.\bmem.$procmux$1227_Y [5] $flatten\imem.\bmem.$procmux$1227_Y [11] $flatten\imem.\bmem.$procmux$1227_Y [11] 1'0 $flatten\imem.\bmem.$procmux$1227_Y [5] 3'011 }
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1239:
      Old ports: A=$flatten\imem.\bmem.$procmux$1236_Y, B=32'11111110110001000010011110000011, Y=$flatten\imem.\bmem.$procmux$1239_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1236_Y [26:0], B=27'110110001000010011110000011, Y=$flatten\imem.\bmem.$procmux$1239_Y [26:0]
      New connections: $flatten\imem.\bmem.$procmux$1239_Y [31:27] = { $flatten\imem.\bmem.$procmux$1239_Y [26] $flatten\imem.\bmem.$procmux$1239_Y [26] $flatten\imem.\bmem.$procmux$1239_Y [26] $flatten\imem.\bmem.$procmux$1239_Y [26] $flatten\imem.\bmem.$procmux$1239_Y [26] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1230:
      Old ports: A=$flatten\imem.\bmem.$procmux$1227_Y [26:0], B=27'110110001000010011110000011, Y=$flatten\imem.\bmem.$procmux$1230_Y [26:0]
      New ports: A={ $flatten\imem.\bmem.$procmux$1227_Y [25] $flatten\imem.\bmem.$procmux$1227_Y [8] $flatten\imem.\bmem.$procmux$1227_Y [22] $flatten\imem.\bmem.$procmux$1227_Y [11] $flatten\imem.\bmem.$procmux$1227_Y [16] $flatten\imem.\bmem.$procmux$1227_Y [13] $flatten\imem.\bmem.$procmux$1227_Y [11:10] 1'0 $flatten\imem.\bmem.$procmux$1227_Y [8:7] $flatten\imem.\bmem.$procmux$1227_Y [5:4] $flatten\imem.\bmem.$procmux$1227_Y [2] }, B=14'10110101111000, Y={ $flatten\imem.\bmem.$procmux$1230_Y [25:24] $flatten\imem.\bmem.$procmux$1230_Y [22] $flatten\imem.\bmem.$procmux$1230_Y [18] $flatten\imem.\bmem.$procmux$1230_Y [16] $flatten\imem.\bmem.$procmux$1230_Y [13] $flatten\imem.\bmem.$procmux$1230_Y [11:7] $flatten\imem.\bmem.$procmux$1230_Y [5:4] $flatten\imem.\bmem.$procmux$1230_Y [2] }
      New connections: { $flatten\imem.\bmem.$procmux$1230_Y [26] $flatten\imem.\bmem.$procmux$1230_Y [23] $flatten\imem.\bmem.$procmux$1230_Y [21:19] $flatten\imem.\bmem.$procmux$1230_Y [17] $flatten\imem.\bmem.$procmux$1230_Y [15:14] $flatten\imem.\bmem.$procmux$1230_Y [12] $flatten\imem.\bmem.$procmux$1230_Y [6] $flatten\imem.\bmem.$procmux$1230_Y [3] $flatten\imem.\bmem.$procmux$1230_Y [1:0] } = { $flatten\imem.\bmem.$procmux$1230_Y [18] $flatten\imem.\bmem.$procmux$1230_Y [13] 3'000 $flatten\imem.\bmem.$procmux$1230_Y [11] $flatten\imem.\bmem.$procmux$1230_Y [5] $flatten\imem.\bmem.$procmux$1230_Y [11] $flatten\imem.\bmem.$procmux$1230_Y [11] $flatten\imem.\bmem.$procmux$1230_Y [5] 3'011 }
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1242:
      Old ports: A=$flatten\imem.\bmem.$procmux$1239_Y, B=32'11010010010111111111000011101111, Y=$flatten\imem.\bmem.$procmux$1242_Y
      New ports: A={ $flatten\imem.\bmem.$procmux$1239_Y [26] $flatten\imem.\bmem.$procmux$1239_Y [26:0] }, B=28'1010010111111111000011101111, Y={ $flatten\imem.\bmem.$procmux$1242_Y [28] $flatten\imem.\bmem.$procmux$1242_Y [26:0] }
      New connections: { $flatten\imem.\bmem.$procmux$1242_Y [31:29] $flatten\imem.\bmem.$procmux$1242_Y [27] } = { $flatten\imem.\bmem.$procmux$1242_Y [28] $flatten\imem.\bmem.$procmux$1242_Y [28] $flatten\imem.\bmem.$procmux$1242_Y [26] $flatten\imem.\bmem.$procmux$1242_Y [26] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1233:
      Old ports: A=$flatten\imem.\bmem.$procmux$1230_Y [26:0], B=27'110111101000010011000100011, Y=$flatten\imem.\bmem.$procmux$1233_Y [26:0]
      New ports: A={ $flatten\imem.\bmem.$procmux$1230_Y [25:24] $flatten\imem.\bmem.$procmux$1230_Y [22] 1'0 $flatten\imem.\bmem.$procmux$1230_Y [18] $flatten\imem.\bmem.$procmux$1230_Y [16] $flatten\imem.\bmem.$procmux$1230_Y [13] $flatten\imem.\bmem.$procmux$1230_Y [11:7] $flatten\imem.\bmem.$procmux$1230_Y [5] $flatten\imem.\bmem.$procmux$1230_Y [5:4] $flatten\imem.\bmem.$procmux$1230_Y [2] }, B=16'1011101011000100, Y={ $flatten\imem.\bmem.$procmux$1233_Y [25:24] $flatten\imem.\bmem.$procmux$1233_Y [22] $flatten\imem.\bmem.$procmux$1233_Y [20] $flatten\imem.\bmem.$procmux$1233_Y [18] $flatten\imem.\bmem.$procmux$1233_Y [16] $flatten\imem.\bmem.$procmux$1233_Y [13] $flatten\imem.\bmem.$procmux$1233_Y [11:4] $flatten\imem.\bmem.$procmux$1233_Y [2] }
      New connections: { $flatten\imem.\bmem.$procmux$1233_Y [26] $flatten\imem.\bmem.$procmux$1233_Y [23] $flatten\imem.\bmem.$procmux$1233_Y [21] $flatten\imem.\bmem.$procmux$1233_Y [19] $flatten\imem.\bmem.$procmux$1233_Y [17] $flatten\imem.\bmem.$procmux$1233_Y [15:14] $flatten\imem.\bmem.$procmux$1233_Y [12] $flatten\imem.\bmem.$procmux$1233_Y [3] $flatten\imem.\bmem.$procmux$1233_Y [1:0] } = { $flatten\imem.\bmem.$procmux$1233_Y [18] $flatten\imem.\bmem.$procmux$1233_Y [13] $flatten\imem.\bmem.$procmux$1233_Y [20] 1'0 $flatten\imem.\bmem.$procmux$1233_Y [11] $flatten\imem.\bmem.$procmux$1233_Y [6] $flatten\imem.\bmem.$procmux$1233_Y [11] $flatten\imem.\bmem.$procmux$1233_Y [11] 3'011 }
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1245:
      Old ports: A=$flatten\imem.\bmem.$procmux$1242_Y, B=492819, Y=$flatten\imem.\bmem.$procmux$1245_Y
      New ports: A={ $flatten\imem.\bmem.$procmux$1242_Y [28] $flatten\imem.\bmem.$procmux$1242_Y [26:0] }, B=28'0000000001111000010100010011, Y={ $flatten\imem.\bmem.$procmux$1245_Y [28] $flatten\imem.\bmem.$procmux$1245_Y [26:0] }
      New connections: { $flatten\imem.\bmem.$procmux$1245_Y [31:29] $flatten\imem.\bmem.$procmux$1245_Y [27] } = { $flatten\imem.\bmem.$procmux$1245_Y [28] $flatten\imem.\bmem.$procmux$1245_Y [28] $flatten\imem.\bmem.$procmux$1245_Y [26] $flatten\imem.\bmem.$procmux$1245_Y [26] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1236:
      Old ports: A=$flatten\imem.\bmem.$procmux$1233_Y [26:0], B=27'111111101111000011110010011, Y=$flatten\imem.\bmem.$procmux$1236_Y [26:0]
      New ports: A={ $flatten\imem.\bmem.$procmux$1233_Y [25:24] $flatten\imem.\bmem.$procmux$1233_Y [13] $flatten\imem.\bmem.$procmux$1233_Y [22] $flatten\imem.\bmem.$procmux$1233_Y [20] $flatten\imem.\bmem.$procmux$1233_Y [18] $flatten\imem.\bmem.$procmux$1233_Y [11] $flatten\imem.\bmem.$procmux$1233_Y [16] $flatten\imem.\bmem.$procmux$1233_Y [6] $flatten\imem.\bmem.$procmux$1233_Y [13] $flatten\imem.\bmem.$procmux$1233_Y [11:4] $flatten\imem.\bmem.$procmux$1233_Y [2] }, B=19'1111111110011110010, Y={ $flatten\imem.\bmem.$procmux$1236_Y [25:22] $flatten\imem.\bmem.$procmux$1236_Y [20] $flatten\imem.\bmem.$procmux$1236_Y [18:15] $flatten\imem.\bmem.$procmux$1236_Y [13] $flatten\imem.\bmem.$procmux$1236_Y [11:4] $flatten\imem.\bmem.$procmux$1236_Y [2] }
      New connections: { $flatten\imem.\bmem.$procmux$1236_Y [26] $flatten\imem.\bmem.$procmux$1236_Y [21] $flatten\imem.\bmem.$procmux$1236_Y [19] $flatten\imem.\bmem.$procmux$1236_Y [14] $flatten\imem.\bmem.$procmux$1236_Y [12] $flatten\imem.\bmem.$procmux$1236_Y [3] $flatten\imem.\bmem.$procmux$1236_Y [1:0] } = { $flatten\imem.\bmem.$procmux$1236_Y [18] $flatten\imem.\bmem.$procmux$1236_Y [20] 1'0 $flatten\imem.\bmem.$procmux$1236_Y [11] $flatten\imem.\bmem.$procmux$1236_Y [11] 3'011 }
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1248:
      Old ports: A=$flatten\imem.\bmem.$procmux$1245_Y, B=32'11111111100001111100011110000011, Y=$flatten\imem.\bmem.$procmux$1248_Y
      New ports: A={ $flatten\imem.\bmem.$procmux$1245_Y [28] $flatten\imem.\bmem.$procmux$1245_Y [26:0] }, B=28'1111100001111100011110000011, Y={ $flatten\imem.\bmem.$procmux$1248_Y [28] $flatten\imem.\bmem.$procmux$1248_Y [26:0] }
      New connections: { $flatten\imem.\bmem.$procmux$1248_Y [31:29] $flatten\imem.\bmem.$procmux$1248_Y [27] } = { $flatten\imem.\bmem.$procmux$1248_Y [28] $flatten\imem.\bmem.$procmux$1248_Y [28] $flatten\imem.\bmem.$procmux$1248_Y [26] $flatten\imem.\bmem.$procmux$1248_Y [26] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1239:
      Old ports: A=$flatten\imem.\bmem.$procmux$1236_Y [26:0], B=27'110110001000010011110000011, Y=$flatten\imem.\bmem.$procmux$1239_Y [26:0]
      New ports: A={ $flatten\imem.\bmem.$procmux$1236_Y [25:22] $flatten\imem.\bmem.$procmux$1236_Y [20] $flatten\imem.\bmem.$procmux$1236_Y [18:15] $flatten\imem.\bmem.$procmux$1236_Y [13] $flatten\imem.\bmem.$procmux$1236_Y [11:4] $flatten\imem.\bmem.$procmux$1236_Y [2] }, B=19'1011010001011110000, Y={ $flatten\imem.\bmem.$procmux$1239_Y [25:22] $flatten\imem.\bmem.$procmux$1239_Y [20] $flatten\imem.\bmem.$procmux$1239_Y [18:15] $flatten\imem.\bmem.$procmux$1239_Y [13] $flatten\imem.\bmem.$procmux$1239_Y [11:4] $flatten\imem.\bmem.$procmux$1239_Y [2] }
      New connections: { $flatten\imem.\bmem.$procmux$1239_Y [26] $flatten\imem.\bmem.$procmux$1239_Y [21] $flatten\imem.\bmem.$procmux$1239_Y [19] $flatten\imem.\bmem.$procmux$1239_Y [14] $flatten\imem.\bmem.$procmux$1239_Y [12] $flatten\imem.\bmem.$procmux$1239_Y [3] $flatten\imem.\bmem.$procmux$1239_Y [1:0] } = { $flatten\imem.\bmem.$procmux$1239_Y [18] $flatten\imem.\bmem.$procmux$1239_Y [20] 1'0 $flatten\imem.\bmem.$procmux$1239_Y [11] $flatten\imem.\bmem.$procmux$1239_Y [11] 3'011 }
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1251:
      Old ports: A=$flatten\imem.\bmem.$procmux$1248_Y, B=16189363, Y=$flatten\imem.\bmem.$procmux$1251_Y
      New ports: A={ $flatten\imem.\bmem.$procmux$1248_Y [28] $flatten\imem.\bmem.$procmux$1248_Y [26:0] }, B=28'0000111101110000011110110011, Y={ $flatten\imem.\bmem.$procmux$1251_Y [28] $flatten\imem.\bmem.$procmux$1251_Y [26:0] }
      New connections: { $flatten\imem.\bmem.$procmux$1251_Y [31:29] $flatten\imem.\bmem.$procmux$1251_Y [27] } = { $flatten\imem.\bmem.$procmux$1251_Y [28] $flatten\imem.\bmem.$procmux$1251_Y [28] $flatten\imem.\bmem.$procmux$1251_Y [26] $flatten\imem.\bmem.$procmux$1251_Y [26] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1242:
      Old ports: A={ $flatten\imem.\bmem.$procmux$1239_Y [26] $flatten\imem.\bmem.$procmux$1239_Y [26:0] }, B=28'1010010111111111000011101111, Y={ $flatten\imem.\bmem.$procmux$1242_Y [28] $flatten\imem.\bmem.$procmux$1242_Y [26:0] }
      New ports: A={ $flatten\imem.\bmem.$procmux$1239_Y [18] $flatten\imem.\bmem.$procmux$1239_Y [25:22] $flatten\imem.\bmem.$procmux$1239_Y [20] $flatten\imem.\bmem.$procmux$1239_Y [20] $flatten\imem.\bmem.$procmux$1239_Y [18:15] $flatten\imem.\bmem.$procmux$1239_Y [13] $flatten\imem.\bmem.$procmux$1239_Y [11] $flatten\imem.\bmem.$procmux$1239_Y [11:4] 1'0 $flatten\imem.\bmem.$procmux$1239_Y [2] }, B=23'01001011111110000111011, Y={ $flatten\imem.\bmem.$procmux$1242_Y [26:20] $flatten\imem.\bmem.$procmux$1242_Y [18:15] $flatten\imem.\bmem.$procmux$1242_Y [13:2] }
      New connections: { $flatten\imem.\bmem.$procmux$1242_Y [28] $flatten\imem.\bmem.$procmux$1242_Y [19] $flatten\imem.\bmem.$procmux$1242_Y [14] $flatten\imem.\bmem.$procmux$1242_Y [1:0] } = { $flatten\imem.\bmem.$procmux$1242_Y [18] $flatten\imem.\bmem.$procmux$1242_Y [3] $flatten\imem.\bmem.$procmux$1242_Y [12] 2'11 }
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1254:
      Old ports: A=$flatten\imem.\bmem.$procmux$1251_Y, B=32'11111111000001000000011100010011, Y=$flatten\imem.\bmem.$procmux$1254_Y
      New ports: A={ $flatten\imem.\bmem.$procmux$1251_Y [28] $flatten\imem.\bmem.$procmux$1251_Y [26:0] }, B=28'1111000001000000011100010011, Y={ $flatten\imem.\bmem.$procmux$1254_Y [28] $flatten\imem.\bmem.$procmux$1254_Y [26:0] }
      New connections: { $flatten\imem.\bmem.$procmux$1254_Y [31:29] $flatten\imem.\bmem.$procmux$1254_Y [27] } = { $flatten\imem.\bmem.$procmux$1254_Y [28] $flatten\imem.\bmem.$procmux$1254_Y [28] $flatten\imem.\bmem.$procmux$1254_Y [26] $flatten\imem.\bmem.$procmux$1254_Y [26] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1245:
      Old ports: A={ $flatten\imem.\bmem.$procmux$1242_Y [28] $flatten\imem.\bmem.$procmux$1242_Y [26:0] }, B=28'0000000001111000010100010011, Y={ $flatten\imem.\bmem.$procmux$1245_Y [28] $flatten\imem.\bmem.$procmux$1245_Y [26:0] }
      New ports: A={ $flatten\imem.\bmem.$procmux$1242_Y [18] $flatten\imem.\bmem.$procmux$1242_Y [26:20] $flatten\imem.\bmem.$procmux$1242_Y [18:15] $flatten\imem.\bmem.$procmux$1242_Y [13:2] }, B=24'000000001111000101000100, Y={ $flatten\imem.\bmem.$procmux$1245_Y [28] $flatten\imem.\bmem.$procmux$1245_Y [26:20] $flatten\imem.\bmem.$procmux$1245_Y [18:15] $flatten\imem.\bmem.$procmux$1245_Y [13:2] }
      New connections: { $flatten\imem.\bmem.$procmux$1245_Y [19] $flatten\imem.\bmem.$procmux$1245_Y [14] $flatten\imem.\bmem.$procmux$1245_Y [1:0] } = { $flatten\imem.\bmem.$procmux$1245_Y [3] $flatten\imem.\bmem.$procmux$1245_Y [12] 2'11 }
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1257:
      Old ports: A=$flatten\imem.\bmem.$procmux$1254_Y, B=32'11111110110001000010011110000011, Y=$flatten\imem.\bmem.$procmux$1257_Y
      New ports: A={ $flatten\imem.\bmem.$procmux$1254_Y [28] $flatten\imem.\bmem.$procmux$1254_Y [26:0] }, B=28'1110110001000010011110000011, Y={ $flatten\imem.\bmem.$procmux$1257_Y [28] $flatten\imem.\bmem.$procmux$1257_Y [26:0] }
      New connections: { $flatten\imem.\bmem.$procmux$1257_Y [31:29] $flatten\imem.\bmem.$procmux$1257_Y [27] } = { $flatten\imem.\bmem.$procmux$1257_Y [28] $flatten\imem.\bmem.$procmux$1257_Y [28] $flatten\imem.\bmem.$procmux$1257_Y [26] $flatten\imem.\bmem.$procmux$1257_Y [26] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1248:
      Old ports: A={ $flatten\imem.\bmem.$procmux$1245_Y [28] $flatten\imem.\bmem.$procmux$1245_Y [26:0] }, B=28'1111100001111100011110000011, Y={ $flatten\imem.\bmem.$procmux$1248_Y [28] $flatten\imem.\bmem.$procmux$1248_Y [26:0] }
      New ports: A={ $flatten\imem.\bmem.$procmux$1245_Y [28] $flatten\imem.\bmem.$procmux$1245_Y [26:20] $flatten\imem.\bmem.$procmux$1245_Y [18:15] $flatten\imem.\bmem.$procmux$1245_Y [12] $flatten\imem.\bmem.$procmux$1245_Y [13:2] }, B=25'1111100011111000111100000, Y={ $flatten\imem.\bmem.$procmux$1248_Y [28] $flatten\imem.\bmem.$procmux$1248_Y [26:20] $flatten\imem.\bmem.$procmux$1248_Y [18:2] }
      New connections: { $flatten\imem.\bmem.$procmux$1248_Y [19] $flatten\imem.\bmem.$procmux$1248_Y [1:0] } = { $flatten\imem.\bmem.$procmux$1248_Y [3] 2'11 }
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1260:
      Old ports: A=$flatten\imem.\bmem.$procmux$1257_Y, B=41943151, Y=$flatten\imem.\bmem.$procmux$1260_Y
      New ports: A={ $flatten\imem.\bmem.$procmux$1257_Y [28] $flatten\imem.\bmem.$procmux$1257_Y [26:0] }, B=28'0010100000000000000001101111, Y={ $flatten\imem.\bmem.$procmux$1260_Y [28] $flatten\imem.\bmem.$procmux$1260_Y [26:0] }
      New connections: { $flatten\imem.\bmem.$procmux$1260_Y [31:29] $flatten\imem.\bmem.$procmux$1260_Y [27] } = { $flatten\imem.\bmem.$procmux$1260_Y [28] $flatten\imem.\bmem.$procmux$1260_Y [28] $flatten\imem.\bmem.$procmux$1260_Y [26] $flatten\imem.\bmem.$procmux$1260_Y [26] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1251:
      Old ports: A={ $flatten\imem.\bmem.$procmux$1248_Y [28] $flatten\imem.\bmem.$procmux$1248_Y [26:0] }, B=28'0000111101110000011110110011, Y={ $flatten\imem.\bmem.$procmux$1251_Y [28] $flatten\imem.\bmem.$procmux$1251_Y [26:0] }
      New ports: A={ $flatten\imem.\bmem.$procmux$1248_Y [28] $flatten\imem.\bmem.$procmux$1248_Y [26:20] $flatten\imem.\bmem.$procmux$1248_Y [18:2] }, B=25'0000111111100000111101100, Y={ $flatten\imem.\bmem.$procmux$1251_Y [28] $flatten\imem.\bmem.$procmux$1251_Y [26:20] $flatten\imem.\bmem.$procmux$1251_Y [18:2] }
      New connections: { $flatten\imem.\bmem.$procmux$1251_Y [19] $flatten\imem.\bmem.$procmux$1251_Y [1:0] } = { $flatten\imem.\bmem.$procmux$1251_Y [3] 2'11 }
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1263:
      Old ports: A=$flatten\imem.\bmem.$procmux$1260_Y, B=32'11111110111101000010011000100011, Y=$flatten\imem.\bmem.$procmux$1263_Y
      New ports: A={ $flatten\imem.\bmem.$procmux$1260_Y [28] $flatten\imem.\bmem.$procmux$1260_Y [26:0] }, B=28'1110111101000010011000100011, Y={ $flatten\imem.\bmem.$procmux$1263_Y [28] $flatten\imem.\bmem.$procmux$1263_Y [26:0] }
      New connections: { $flatten\imem.\bmem.$procmux$1263_Y [31:29] $flatten\imem.\bmem.$procmux$1263_Y [27] } = { $flatten\imem.\bmem.$procmux$1263_Y [28] $flatten\imem.\bmem.$procmux$1263_Y [28] $flatten\imem.\bmem.$procmux$1263_Y [26] $flatten\imem.\bmem.$procmux$1263_Y [26] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1254:
      Old ports: A={ $flatten\imem.\bmem.$procmux$1251_Y [28] $flatten\imem.\bmem.$procmux$1251_Y [26:0] }, B=28'1111000001000000011100010011, Y={ $flatten\imem.\bmem.$procmux$1254_Y [28] $flatten\imem.\bmem.$procmux$1254_Y [26:0] }
      New ports: A={ $flatten\imem.\bmem.$procmux$1251_Y [28] $flatten\imem.\bmem.$procmux$1251_Y [26:20] $flatten\imem.\bmem.$procmux$1251_Y [18:2] }, B=25'1111000010000000111000100, Y={ $flatten\imem.\bmem.$procmux$1254_Y [28] $flatten\imem.\bmem.$procmux$1254_Y [26:20] $flatten\imem.\bmem.$procmux$1254_Y [18:2] }
      New connections: { $flatten\imem.\bmem.$procmux$1254_Y [19] $flatten\imem.\bmem.$procmux$1254_Y [1:0] } = { $flatten\imem.\bmem.$procmux$1254_Y [3] 2'11 }
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1266:
      Old ports: A=$flatten\imem.\bmem.$procmux$1263_Y, B=2099091, Y=$flatten\imem.\bmem.$procmux$1266_Y
      New ports: A={ $flatten\imem.\bmem.$procmux$1263_Y [28] $flatten\imem.\bmem.$procmux$1263_Y [26:0] }, B=28'0000001000000000011110010011, Y={ $flatten\imem.\bmem.$procmux$1266_Y [28] $flatten\imem.\bmem.$procmux$1266_Y [26:0] }
      New connections: { $flatten\imem.\bmem.$procmux$1266_Y [31:29] $flatten\imem.\bmem.$procmux$1266_Y [27] } = { $flatten\imem.\bmem.$procmux$1266_Y [28] $flatten\imem.\bmem.$procmux$1266_Y [28] $flatten\imem.\bmem.$procmux$1266_Y [26] $flatten\imem.\bmem.$procmux$1266_Y [26] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1257:
      Old ports: A={ $flatten\imem.\bmem.$procmux$1254_Y [28] $flatten\imem.\bmem.$procmux$1254_Y [26:0] }, B=28'1110110001000010011110000011, Y={ $flatten\imem.\bmem.$procmux$1257_Y [28] $flatten\imem.\bmem.$procmux$1257_Y [26:0] }
      New ports: A={ $flatten\imem.\bmem.$procmux$1254_Y [28] $flatten\imem.\bmem.$procmux$1254_Y [26:20] $flatten\imem.\bmem.$procmux$1254_Y [18:2] }, B=25'1110110010000100111100000, Y={ $flatten\imem.\bmem.$procmux$1257_Y [28] $flatten\imem.\bmem.$procmux$1257_Y [26:20] $flatten\imem.\bmem.$procmux$1257_Y [18:2] }
      New connections: { $flatten\imem.\bmem.$procmux$1257_Y [19] $flatten\imem.\bmem.$procmux$1257_Y [1:0] } = { $flatten\imem.\bmem.$procmux$1257_Y [3] 2'11 }
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1269:
      Old ports: A=$flatten\imem.\bmem.$procmux$1266_Y, B=32'11111110111101000010010000100011, Y=$flatten\imem.\bmem.$procmux$1269_Y
      New ports: A={ $flatten\imem.\bmem.$procmux$1266_Y [28] $flatten\imem.\bmem.$procmux$1266_Y [26:0] }, B=28'1110111101000010010000100011, Y={ $flatten\imem.\bmem.$procmux$1269_Y [28] $flatten\imem.\bmem.$procmux$1269_Y [26:0] }
      New connections: { $flatten\imem.\bmem.$procmux$1269_Y [31:29] $flatten\imem.\bmem.$procmux$1269_Y [27] } = { $flatten\imem.\bmem.$procmux$1269_Y [28] $flatten\imem.\bmem.$procmux$1269_Y [28] $flatten\imem.\bmem.$procmux$1269_Y [26] $flatten\imem.\bmem.$procmux$1269_Y [26] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1260:
      Old ports: A={ $flatten\imem.\bmem.$procmux$1257_Y [28] $flatten\imem.\bmem.$procmux$1257_Y [26:0] }, B=28'0010100000000000000001101111, Y={ $flatten\imem.\bmem.$procmux$1260_Y [28] $flatten\imem.\bmem.$procmux$1260_Y [26:0] }
      New ports: A={ $flatten\imem.\bmem.$procmux$1257_Y [28] $flatten\imem.\bmem.$procmux$1257_Y [26:20] $flatten\imem.\bmem.$procmux$1257_Y [3] $flatten\imem.\bmem.$procmux$1257_Y [18:2] }, B=26'00101000000000000000011011, Y={ $flatten\imem.\bmem.$procmux$1260_Y [28] $flatten\imem.\bmem.$procmux$1260_Y [26:2] }
      New connections: $flatten\imem.\bmem.$procmux$1260_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1272:
      Old ports: A=$flatten\imem.\bmem.$procmux$1269_Y, B=32'11111101110001000010011110000011, Y=$flatten\imem.\bmem.$procmux$1272_Y
      New ports: A={ $flatten\imem.\bmem.$procmux$1269_Y [28] $flatten\imem.\bmem.$procmux$1269_Y [26:0] }, B=28'1101110001000010011110000011, Y={ $flatten\imem.\bmem.$procmux$1272_Y [28] $flatten\imem.\bmem.$procmux$1272_Y [26:0] }
      New connections: { $flatten\imem.\bmem.$procmux$1272_Y [31:29] $flatten\imem.\bmem.$procmux$1272_Y [27] } = { $flatten\imem.\bmem.$procmux$1272_Y [28] $flatten\imem.\bmem.$procmux$1272_Y [28] $flatten\imem.\bmem.$procmux$1272_Y [26] $flatten\imem.\bmem.$procmux$1272_Y [26] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1263:
      Old ports: A={ $flatten\imem.\bmem.$procmux$1260_Y [28] $flatten\imem.\bmem.$procmux$1260_Y [26:0] }, B=28'1110111101000010011000100011, Y={ $flatten\imem.\bmem.$procmux$1263_Y [28] $flatten\imem.\bmem.$procmux$1263_Y [26:0] }
      New ports: A={ $flatten\imem.\bmem.$procmux$1260_Y [28] $flatten\imem.\bmem.$procmux$1260_Y [26:2] }, B=26'11101111010000100110001000, Y={ $flatten\imem.\bmem.$procmux$1263_Y [28] $flatten\imem.\bmem.$procmux$1263_Y [26:2] }
      New connections: $flatten\imem.\bmem.$procmux$1263_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1275:
      Old ports: A=$flatten\imem.\bmem.$procmux$1272_Y, B=32'11111100101001000010111000100011, Y=$flatten\imem.\bmem.$procmux$1275_Y
      New ports: A={ $flatten\imem.\bmem.$procmux$1272_Y [28] $flatten\imem.\bmem.$procmux$1272_Y [26:0] }, B=28'1100101001000010111000100011, Y={ $flatten\imem.\bmem.$procmux$1275_Y [28] $flatten\imem.\bmem.$procmux$1275_Y [26:0] }
      New connections: { $flatten\imem.\bmem.$procmux$1275_Y [31:29] $flatten\imem.\bmem.$procmux$1275_Y [27] } = { $flatten\imem.\bmem.$procmux$1275_Y [28] $flatten\imem.\bmem.$procmux$1275_Y [28] $flatten\imem.\bmem.$procmux$1275_Y [26] $flatten\imem.\bmem.$procmux$1275_Y [26] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1266:
      Old ports: A={ $flatten\imem.\bmem.$procmux$1263_Y [28] $flatten\imem.\bmem.$procmux$1263_Y [26:0] }, B=28'0000001000000000011110010011, Y={ $flatten\imem.\bmem.$procmux$1266_Y [28] $flatten\imem.\bmem.$procmux$1266_Y [26:0] }
      New ports: A={ $flatten\imem.\bmem.$procmux$1263_Y [28] $flatten\imem.\bmem.$procmux$1263_Y [26:2] }, B=26'00000010000000000111100100, Y={ $flatten\imem.\bmem.$procmux$1266_Y [28] $flatten\imem.\bmem.$procmux$1266_Y [26:2] }
      New connections: $flatten\imem.\bmem.$procmux$1266_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1278:
      Old ports: A=$flatten\imem.\bmem.$procmux$1275_Y, B=50398227, Y=$flatten\imem.\bmem.$procmux$1278_Y
      New ports: A={ $flatten\imem.\bmem.$procmux$1275_Y [28] $flatten\imem.\bmem.$procmux$1275_Y [26:0] }, B=28'0011000000010000010000010011, Y={ $flatten\imem.\bmem.$procmux$1278_Y [28] $flatten\imem.\bmem.$procmux$1278_Y [26:0] }
      New connections: { $flatten\imem.\bmem.$procmux$1278_Y [31:29] $flatten\imem.\bmem.$procmux$1278_Y [27] } = { $flatten\imem.\bmem.$procmux$1278_Y [28] $flatten\imem.\bmem.$procmux$1278_Y [28] $flatten\imem.\bmem.$procmux$1278_Y [26] $flatten\imem.\bmem.$procmux$1278_Y [26] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1269:
      Old ports: A={ $flatten\imem.\bmem.$procmux$1266_Y [28] $flatten\imem.\bmem.$procmux$1266_Y [26:0] }, B=28'1110111101000010010000100011, Y={ $flatten\imem.\bmem.$procmux$1269_Y [28] $flatten\imem.\bmem.$procmux$1269_Y [26:0] }
      New ports: A={ $flatten\imem.\bmem.$procmux$1266_Y [28] $flatten\imem.\bmem.$procmux$1266_Y [26:2] }, B=26'11101111010000100100001000, Y={ $flatten\imem.\bmem.$procmux$1269_Y [28] $flatten\imem.\bmem.$procmux$1269_Y [26:2] }
      New connections: $flatten\imem.\bmem.$procmux$1269_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1281:
      Old ports: A=$flatten\imem.\bmem.$procmux$1278_Y, B=42017827, Y=$flatten\imem.\bmem.$procmux$1281_Y
      New ports: A={ $flatten\imem.\bmem.$procmux$1278_Y [28] $flatten\imem.\bmem.$procmux$1278_Y [26:0] }, B=28'0010100000010010010000100011, Y={ $flatten\imem.\bmem.$procmux$1281_Y [28] $flatten\imem.\bmem.$procmux$1281_Y [26:0] }
      New connections: { $flatten\imem.\bmem.$procmux$1281_Y [31:29] $flatten\imem.\bmem.$procmux$1281_Y [27] } = { $flatten\imem.\bmem.$procmux$1281_Y [28] $flatten\imem.\bmem.$procmux$1281_Y [28] $flatten\imem.\bmem.$procmux$1281_Y [26] $flatten\imem.\bmem.$procmux$1281_Y [26] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1272:
      Old ports: A={ $flatten\imem.\bmem.$procmux$1269_Y [28] $flatten\imem.\bmem.$procmux$1269_Y [26:0] }, B=28'1101110001000010011110000011, Y={ $flatten\imem.\bmem.$procmux$1272_Y [28] $flatten\imem.\bmem.$procmux$1272_Y [26:0] }
      New ports: A={ $flatten\imem.\bmem.$procmux$1269_Y [28] $flatten\imem.\bmem.$procmux$1269_Y [26:2] }, B=26'11011100010000100111100000, Y={ $flatten\imem.\bmem.$procmux$1272_Y [28] $flatten\imem.\bmem.$procmux$1272_Y [26:2] }
      New connections: $flatten\imem.\bmem.$procmux$1272_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1284:
      Old ports: A=$flatten\imem.\bmem.$procmux$1281_Y, B=34678307, Y=$flatten\imem.\bmem.$procmux$1284_Y
      New ports: A={ $flatten\imem.\bmem.$procmux$1281_Y [28] $flatten\imem.\bmem.$procmux$1281_Y [26:0] }, B=28'0010000100010010011000100011, Y={ $flatten\imem.\bmem.$procmux$1284_Y [28] $flatten\imem.\bmem.$procmux$1284_Y [26:0] }
      New connections: { $flatten\imem.\bmem.$procmux$1284_Y [31:29] $flatten\imem.\bmem.$procmux$1284_Y [27] } = { $flatten\imem.\bmem.$procmux$1284_Y [28] $flatten\imem.\bmem.$procmux$1284_Y [28] $flatten\imem.\bmem.$procmux$1284_Y [26] $flatten\imem.\bmem.$procmux$1284_Y [26] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1275:
      Old ports: A={ $flatten\imem.\bmem.$procmux$1272_Y [28] $flatten\imem.\bmem.$procmux$1272_Y [26:0] }, B=28'1100101001000010111000100011, Y={ $flatten\imem.\bmem.$procmux$1275_Y [28] $flatten\imem.\bmem.$procmux$1275_Y [26:0] }
      New ports: A={ $flatten\imem.\bmem.$procmux$1272_Y [28] $flatten\imem.\bmem.$procmux$1272_Y [26:2] }, B=26'11001010010000101110001000, Y={ $flatten\imem.\bmem.$procmux$1275_Y [28] $flatten\imem.\bmem.$procmux$1275_Y [26:2] }
      New connections: $flatten\imem.\bmem.$procmux$1275_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1287:
      Old ports: A=$flatten\imem.\bmem.$procmux$1284_Y, B=32'11111101000000010000000100010011, Y=$flatten\imem.\bmem.$procmux$1287_Y
      New ports: A={ $flatten\imem.\bmem.$procmux$1284_Y [28] $flatten\imem.\bmem.$procmux$1284_Y [26:0] }, B=28'1101000000010000000100010011, Y={ $flatten\imem.\bmem.$procmux$1287_Y [28] $flatten\imem.\bmem.$procmux$1287_Y [26:0] }
      New connections: { $flatten\imem.\bmem.$procmux$1287_Y [31:29] $flatten\imem.\bmem.$procmux$1287_Y [27] } = { $flatten\imem.\bmem.$procmux$1287_Y [28] $flatten\imem.\bmem.$procmux$1287_Y [28] $flatten\imem.\bmem.$procmux$1287_Y [26] $flatten\imem.\bmem.$procmux$1287_Y [26] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1278:
      Old ports: A={ $flatten\imem.\bmem.$procmux$1275_Y [28] $flatten\imem.\bmem.$procmux$1275_Y [26:0] }, B=28'0011000000010000010000010011, Y={ $flatten\imem.\bmem.$procmux$1278_Y [28] $flatten\imem.\bmem.$procmux$1278_Y [26:0] }
      New ports: A={ $flatten\imem.\bmem.$procmux$1275_Y [28] $flatten\imem.\bmem.$procmux$1275_Y [26:2] }, B=26'00110000000100000100000100, Y={ $flatten\imem.\bmem.$procmux$1278_Y [28] $flatten\imem.\bmem.$procmux$1278_Y [26:2] }
      New connections: $flatten\imem.\bmem.$procmux$1278_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1290:
      Old ports: A=$flatten\imem.\bmem.$procmux$1287_Y, B=32871, Y=$flatten\imem.\bmem.$procmux$1290_Y
      New ports: A={ $flatten\imem.\bmem.$procmux$1287_Y [28] $flatten\imem.\bmem.$procmux$1287_Y [26:0] }, B=28'0000000000001000000001100111, Y={ $flatten\imem.\bmem.$procmux$1290_Y [28] $flatten\imem.\bmem.$procmux$1290_Y [26:0] }
      New connections: { $flatten\imem.\bmem.$procmux$1290_Y [31:29] $flatten\imem.\bmem.$procmux$1290_Y [27] } = { $flatten\imem.\bmem.$procmux$1290_Y [28] $flatten\imem.\bmem.$procmux$1290_Y [28] $flatten\imem.\bmem.$procmux$1290_Y [26] $flatten\imem.\bmem.$procmux$1290_Y [26] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1281:
      Old ports: A={ $flatten\imem.\bmem.$procmux$1278_Y [28] $flatten\imem.\bmem.$procmux$1278_Y [26:0] }, B=28'0010100000010010010000100011, Y={ $flatten\imem.\bmem.$procmux$1281_Y [28] $flatten\imem.\bmem.$procmux$1281_Y [26:0] }
      New ports: A={ $flatten\imem.\bmem.$procmux$1278_Y [28] $flatten\imem.\bmem.$procmux$1278_Y [26:2] }, B=26'00101000000100100100001000, Y={ $flatten\imem.\bmem.$procmux$1281_Y [28] $flatten\imem.\bmem.$procmux$1281_Y [26:2] }
      New connections: $flatten\imem.\bmem.$procmux$1281_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1293:
      Old ports: A=$flatten\imem.\bmem.$procmux$1290_Y, B=50397459, Y=$flatten\imem.\bmem.$procmux$1293_Y
      New ports: A={ $flatten\imem.\bmem.$procmux$1290_Y [28] $flatten\imem.\bmem.$procmux$1290_Y [26:0] }, B=28'0011000000010000000100010011, Y={ $flatten\imem.\bmem.$procmux$1293_Y [28] $flatten\imem.\bmem.$procmux$1293_Y [26:0] }
      New connections: { $flatten\imem.\bmem.$procmux$1293_Y [31:29] $flatten\imem.\bmem.$procmux$1293_Y [27] } = { $flatten\imem.\bmem.$procmux$1293_Y [28] $flatten\imem.\bmem.$procmux$1293_Y [28] $flatten\imem.\bmem.$procmux$1293_Y [26] $flatten\imem.\bmem.$procmux$1293_Y [26] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1284:
      Old ports: A={ $flatten\imem.\bmem.$procmux$1281_Y [28] $flatten\imem.\bmem.$procmux$1281_Y [26:0] }, B=28'0010000100010010011000100011, Y={ $flatten\imem.\bmem.$procmux$1284_Y [28] $flatten\imem.\bmem.$procmux$1284_Y [26:0] }
      New ports: A={ $flatten\imem.\bmem.$procmux$1281_Y [28] $flatten\imem.\bmem.$procmux$1281_Y [26:2] }, B=26'00100001000100100110001000, Y={ $flatten\imem.\bmem.$procmux$1284_Y [28] $flatten\imem.\bmem.$procmux$1284_Y [26:2] }
      New connections: $flatten\imem.\bmem.$procmux$1284_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1296:
      Old ports: A=$flatten\imem.\bmem.$procmux$1293_Y, B=42017795, Y=$flatten\imem.\bmem.$procmux$1296_Y
      New ports: A={ $flatten\imem.\bmem.$procmux$1293_Y [28] $flatten\imem.\bmem.$procmux$1293_Y [26:0] }, B=28'0010100000010010010000000011, Y={ $flatten\imem.\bmem.$procmux$1296_Y [28] $flatten\imem.\bmem.$procmux$1296_Y [26:0] }
      New connections: { $flatten\imem.\bmem.$procmux$1296_Y [31:29] $flatten\imem.\bmem.$procmux$1296_Y [27] } = { $flatten\imem.\bmem.$procmux$1296_Y [28] $flatten\imem.\bmem.$procmux$1296_Y [28] $flatten\imem.\bmem.$procmux$1296_Y [26] $flatten\imem.\bmem.$procmux$1296_Y [26] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1287:
      Old ports: A={ $flatten\imem.\bmem.$procmux$1284_Y [28] $flatten\imem.\bmem.$procmux$1284_Y [26:0] }, B=28'1101000000010000000100010011, Y={ $flatten\imem.\bmem.$procmux$1287_Y [28] $flatten\imem.\bmem.$procmux$1287_Y [26:0] }
      New ports: A={ $flatten\imem.\bmem.$procmux$1284_Y [28] $flatten\imem.\bmem.$procmux$1284_Y [26:2] }, B=26'11010000000100000001000100, Y={ $flatten\imem.\bmem.$procmux$1287_Y [28] $flatten\imem.\bmem.$procmux$1287_Y [26:2] }
      New connections: $flatten\imem.\bmem.$procmux$1287_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1299:
      Old ports: A=$flatten\imem.\bmem.$procmux$1296_Y, B=46211203, Y=$flatten\imem.\bmem.$procmux$1299_Y
      New ports: A={ $flatten\imem.\bmem.$procmux$1296_Y [28] $flatten\imem.\bmem.$procmux$1296_Y [26:0] }, B=28'0010110000010010000010000011, Y={ $flatten\imem.\bmem.$procmux$1299_Y [28] $flatten\imem.\bmem.$procmux$1299_Y [26:0] }
      New connections: { $flatten\imem.\bmem.$procmux$1299_Y [31:29] $flatten\imem.\bmem.$procmux$1299_Y [27] } = { $flatten\imem.\bmem.$procmux$1299_Y [28] $flatten\imem.\bmem.$procmux$1299_Y [28] $flatten\imem.\bmem.$procmux$1299_Y [26] $flatten\imem.\bmem.$procmux$1299_Y [26] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1290:
      Old ports: A={ $flatten\imem.\bmem.$procmux$1287_Y [28] $flatten\imem.\bmem.$procmux$1287_Y [26:0] }, B=28'0000000000001000000001100111, Y={ $flatten\imem.\bmem.$procmux$1290_Y [28] $flatten\imem.\bmem.$procmux$1290_Y [26:0] }
      New ports: A={ $flatten\imem.\bmem.$procmux$1287_Y [28] $flatten\imem.\bmem.$procmux$1287_Y [26:2] }, B=26'00000000000010000000011001, Y={ $flatten\imem.\bmem.$procmux$1290_Y [28] $flatten\imem.\bmem.$procmux$1290_Y [26:2] }
      New connections: $flatten\imem.\bmem.$procmux$1290_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1302:
      Old ports: A=$flatten\imem.\bmem.$procmux$1299_Y, B=492819, Y=$flatten\imem.\bmem.$procmux$1302_Y
      New ports: A={ $flatten\imem.\bmem.$procmux$1299_Y [28] $flatten\imem.\bmem.$procmux$1299_Y [26:0] }, B=28'0000000001111000010100010011, Y={ $flatten\imem.\bmem.$procmux$1302_Y [28] $flatten\imem.\bmem.$procmux$1302_Y [26:0] }
      New connections: { $flatten\imem.\bmem.$procmux$1302_Y [31:29] $flatten\imem.\bmem.$procmux$1302_Y [27] } = { $flatten\imem.\bmem.$procmux$1302_Y [28] $flatten\imem.\bmem.$procmux$1302_Y [28] $flatten\imem.\bmem.$procmux$1302_Y [26] $flatten\imem.\bmem.$procmux$1302_Y [26] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1293:
      Old ports: A={ $flatten\imem.\bmem.$procmux$1290_Y [28] $flatten\imem.\bmem.$procmux$1290_Y [26:0] }, B=28'0011000000010000000100010011, Y={ $flatten\imem.\bmem.$procmux$1293_Y [28] $flatten\imem.\bmem.$procmux$1293_Y [26:0] }
      New ports: A={ $flatten\imem.\bmem.$procmux$1290_Y [28] $flatten\imem.\bmem.$procmux$1290_Y [26:2] }, B=26'00110000000100000001000100, Y={ $flatten\imem.\bmem.$procmux$1293_Y [28] $flatten\imem.\bmem.$procmux$1293_Y [26:2] }
      New connections: $flatten\imem.\bmem.$procmux$1293_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1305:
      Old ports: A=$flatten\imem.\bmem.$procmux$1302_Y, B=32'11111110100001000010011110000011, Y=$flatten\imem.\bmem.$procmux$1305_Y
      New ports: A={ $flatten\imem.\bmem.$procmux$1302_Y [28] $flatten\imem.\bmem.$procmux$1302_Y [26:0] }, B=28'1110100001000010011110000011, Y={ $flatten\imem.\bmem.$procmux$1305_Y [28] $flatten\imem.\bmem.$procmux$1305_Y [26:0] }
      New connections: { $flatten\imem.\bmem.$procmux$1305_Y [31:29] $flatten\imem.\bmem.$procmux$1305_Y [27] } = { $flatten\imem.\bmem.$procmux$1305_Y [28] $flatten\imem.\bmem.$procmux$1305_Y [28] $flatten\imem.\bmem.$procmux$1305_Y [26] $flatten\imem.\bmem.$procmux$1305_Y [26] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1296:
      Old ports: A={ $flatten\imem.\bmem.$procmux$1293_Y [28] $flatten\imem.\bmem.$procmux$1293_Y [26:0] }, B=28'0010100000010010010000000011, Y={ $flatten\imem.\bmem.$procmux$1296_Y [28] $flatten\imem.\bmem.$procmux$1296_Y [26:0] }
      New ports: A={ $flatten\imem.\bmem.$procmux$1293_Y [28] $flatten\imem.\bmem.$procmux$1293_Y [26:2] }, B=26'00101000000100100100000000, Y={ $flatten\imem.\bmem.$procmux$1296_Y [28] $flatten\imem.\bmem.$procmux$1296_Y [26:2] }
      New connections: $flatten\imem.\bmem.$procmux$1296_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1308:
      Old ports: A=$flatten\imem.\bmem.$procmux$1305_Y, B=15172259, Y=$flatten\imem.\bmem.$procmux$1308_Y
      New ports: A={ $flatten\imem.\bmem.$procmux$1305_Y [28] $flatten\imem.\bmem.$procmux$1305_Y [26:0] }, B=28'0000111001111000001010100011, Y={ $flatten\imem.\bmem.$procmux$1308_Y [28] $flatten\imem.\bmem.$procmux$1308_Y [26:0] }
      New connections: { $flatten\imem.\bmem.$procmux$1308_Y [31:29] $flatten\imem.\bmem.$procmux$1308_Y [27] } = { $flatten\imem.\bmem.$procmux$1308_Y [28] $flatten\imem.\bmem.$procmux$1308_Y [28] $flatten\imem.\bmem.$procmux$1308_Y [26] $flatten\imem.\bmem.$procmux$1308_Y [26] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1299:
      Old ports: A={ $flatten\imem.\bmem.$procmux$1296_Y [28] $flatten\imem.\bmem.$procmux$1296_Y [26:0] }, B=28'0010110000010010000010000011, Y={ $flatten\imem.\bmem.$procmux$1299_Y [28] $flatten\imem.\bmem.$procmux$1299_Y [26:0] }
      New ports: A={ $flatten\imem.\bmem.$procmux$1296_Y [28] $flatten\imem.\bmem.$procmux$1296_Y [26:2] }, B=26'00101100000100100000100000, Y={ $flatten\imem.\bmem.$procmux$1299_Y [28] $flatten\imem.\bmem.$procmux$1299_Y [26:2] }
      New connections: $flatten\imem.\bmem.$procmux$1299_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1311:
      Old ports: A=$flatten\imem.\bmem.$procmux$1308_Y, B=267876115, Y=$flatten\imem.\bmem.$procmux$1311_Y
      New ports: A={ $flatten\imem.\bmem.$procmux$1308_Y [26] $flatten\imem.\bmem.$procmux$1308_Y [28] $flatten\imem.\bmem.$procmux$1308_Y [26:0] }, B=29'00111111101110111011100010011, Y={ $flatten\imem.\bmem.$procmux$1311_Y [29:28] $flatten\imem.\bmem.$procmux$1311_Y [26:0] }
      New connections: { $flatten\imem.\bmem.$procmux$1311_Y [31:30] $flatten\imem.\bmem.$procmux$1311_Y [27] } = { $flatten\imem.\bmem.$procmux$1311_Y [28] $flatten\imem.\bmem.$procmux$1311_Y [28] $flatten\imem.\bmem.$procmux$1311_Y [26] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1302:
      Old ports: A={ $flatten\imem.\bmem.$procmux$1299_Y [28] $flatten\imem.\bmem.$procmux$1299_Y [26:0] }, B=28'0000000001111000010100010011, Y={ $flatten\imem.\bmem.$procmux$1302_Y [28] $flatten\imem.\bmem.$procmux$1302_Y [26:0] }
      New ports: A={ $flatten\imem.\bmem.$procmux$1299_Y [28] $flatten\imem.\bmem.$procmux$1299_Y [26:2] }, B=26'00000000011110000101000100, Y={ $flatten\imem.\bmem.$procmux$1302_Y [28] $flatten\imem.\bmem.$procmux$1302_Y [26:2] }
      New connections: $flatten\imem.\bmem.$procmux$1302_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1314:
      Old ports: A=$flatten\imem.\bmem.$procmux$1311_Y, B=32'11111111111001110111011100010011, Y=$flatten\imem.\bmem.$procmux$1314_Y
      New ports: A={ $flatten\imem.\bmem.$procmux$1311_Y [29:28] $flatten\imem.\bmem.$procmux$1311_Y [26:0] }, B=29'11111111001110111011100010011, Y={ $flatten\imem.\bmem.$procmux$1314_Y [29:28] $flatten\imem.\bmem.$procmux$1314_Y [26:0] }
      New connections: { $flatten\imem.\bmem.$procmux$1314_Y [31:30] $flatten\imem.\bmem.$procmux$1314_Y [27] } = { $flatten\imem.\bmem.$procmux$1314_Y [28] $flatten\imem.\bmem.$procmux$1314_Y [28] $flatten\imem.\bmem.$procmux$1314_Y [26] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1305:
      Old ports: A={ $flatten\imem.\bmem.$procmux$1302_Y [28] $flatten\imem.\bmem.$procmux$1302_Y [26:0] }, B=28'1110100001000010011110000011, Y={ $flatten\imem.\bmem.$procmux$1305_Y [28] $flatten\imem.\bmem.$procmux$1305_Y [26:0] }
      New ports: A={ $flatten\imem.\bmem.$procmux$1302_Y [28] $flatten\imem.\bmem.$procmux$1302_Y [26:2] }, B=26'11101000010000100111100000, Y={ $flatten\imem.\bmem.$procmux$1305_Y [28] $flatten\imem.\bmem.$procmux$1305_Y [26:2] }
      New connections: $flatten\imem.\bmem.$procmux$1305_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1317:
      Old ports: A=$flatten\imem.\bmem.$procmux$1314_Y, B=14263, Y=$flatten\imem.\bmem.$procmux$1317_Y
      New ports: A={ $flatten\imem.\bmem.$procmux$1314_Y [29:28] $flatten\imem.\bmem.$procmux$1314_Y [26:0] }, B=29'00000000000000011011110110111, Y={ $flatten\imem.\bmem.$procmux$1317_Y [29:28] $flatten\imem.\bmem.$procmux$1317_Y [26:0] }
      New connections: { $flatten\imem.\bmem.$procmux$1317_Y [31:30] $flatten\imem.\bmem.$procmux$1317_Y [27] } = { $flatten\imem.\bmem.$procmux$1317_Y [28] $flatten\imem.\bmem.$procmux$1317_Y [28] $flatten\imem.\bmem.$procmux$1317_Y [26] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1308:
      Old ports: A={ $flatten\imem.\bmem.$procmux$1305_Y [28] $flatten\imem.\bmem.$procmux$1305_Y [26:0] }, B=28'0000111001111000001010100011, Y={ $flatten\imem.\bmem.$procmux$1308_Y [28] $flatten\imem.\bmem.$procmux$1308_Y [26:0] }
      New ports: A={ $flatten\imem.\bmem.$procmux$1305_Y [28] $flatten\imem.\bmem.$procmux$1305_Y [26:2] }, B=26'00001110011110000010101000, Y={ $flatten\imem.\bmem.$procmux$1308_Y [28] $flatten\imem.\bmem.$procmux$1308_Y [26:2] }
      New connections: $flatten\imem.\bmem.$procmux$1308_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1320:
      Old ports: A=$flatten\imem.\bmem.$procmux$1317_Y, B=267908883, Y=$flatten\imem.\bmem.$procmux$1320_Y
      New ports: A={ $flatten\imem.\bmem.$procmux$1317_Y [29:28] $flatten\imem.\bmem.$procmux$1317_Y [26:0] }, B=29'00111111101111111011100010011, Y={ $flatten\imem.\bmem.$procmux$1320_Y [29:28] $flatten\imem.\bmem.$procmux$1320_Y [26:0] }
      New connections: { $flatten\imem.\bmem.$procmux$1320_Y [31:30] $flatten\imem.\bmem.$procmux$1320_Y [27] } = { $flatten\imem.\bmem.$procmux$1320_Y [28] $flatten\imem.\bmem.$procmux$1320_Y [28] $flatten\imem.\bmem.$procmux$1320_Y [26] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1311:
      Old ports: A={ $flatten\imem.\bmem.$procmux$1308_Y [26] $flatten\imem.\bmem.$procmux$1308_Y [28] $flatten\imem.\bmem.$procmux$1308_Y [26:0] }, B=29'00111111101110111011100010011, Y={ $flatten\imem.\bmem.$procmux$1311_Y [29:28] $flatten\imem.\bmem.$procmux$1311_Y [26:0] }
      New ports: A={ $flatten\imem.\bmem.$procmux$1308_Y [26] $flatten\imem.\bmem.$procmux$1308_Y [28] $flatten\imem.\bmem.$procmux$1308_Y [26:2] }, B=27'001111111011101110111000100, Y={ $flatten\imem.\bmem.$procmux$1311_Y [29:28] $flatten\imem.\bmem.$procmux$1311_Y [26:2] }
      New connections: $flatten\imem.\bmem.$procmux$1311_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1323:
      Old ports: A=$flatten\imem.\bmem.$procmux$1320_Y, B=5752707, Y=$flatten\imem.\bmem.$procmux$1323_Y
      New ports: A={ $flatten\imem.\bmem.$procmux$1320_Y [29:28] $flatten\imem.\bmem.$procmux$1320_Y [26:0] }, B=29'00000010101111100011110000011, Y={ $flatten\imem.\bmem.$procmux$1323_Y [29:28] $flatten\imem.\bmem.$procmux$1323_Y [26:0] }
      New connections: { $flatten\imem.\bmem.$procmux$1323_Y [31:30] $flatten\imem.\bmem.$procmux$1323_Y [27] } = { $flatten\imem.\bmem.$procmux$1323_Y [28] $flatten\imem.\bmem.$procmux$1323_Y [28] $flatten\imem.\bmem.$procmux$1323_Y [26] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1314:
      Old ports: A={ $flatten\imem.\bmem.$procmux$1311_Y [29:28] $flatten\imem.\bmem.$procmux$1311_Y [26:0] }, B=29'11111111001110111011100010011, Y={ $flatten\imem.\bmem.$procmux$1314_Y [29:28] $flatten\imem.\bmem.$procmux$1314_Y [26:0] }
      New ports: A={ $flatten\imem.\bmem.$procmux$1311_Y [29:28] $flatten\imem.\bmem.$procmux$1311_Y [26:2] }, B=27'111111110011101110111000100, Y={ $flatten\imem.\bmem.$procmux$1314_Y [29:28] $flatten\imem.\bmem.$procmux$1314_Y [26:2] }
      New connections: $flatten\imem.\bmem.$procmux$1314_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1326:
      Old ports: A=$flatten\imem.\bmem.$procmux$1323_Y, B=14263, Y=$flatten\imem.\bmem.$procmux$1326_Y
      New ports: A={ $flatten\imem.\bmem.$procmux$1323_Y [29:28] $flatten\imem.\bmem.$procmux$1323_Y [26:0] }, B=29'00000000000000011011110110111, Y={ $flatten\imem.\bmem.$procmux$1326_Y [29:28] $flatten\imem.\bmem.$procmux$1326_Y [26:0] }
      New connections: { $flatten\imem.\bmem.$procmux$1326_Y [31:30] $flatten\imem.\bmem.$procmux$1326_Y [27] } = { $flatten\imem.\bmem.$procmux$1326_Y [28] $flatten\imem.\bmem.$procmux$1326_Y [28] $flatten\imem.\bmem.$procmux$1326_Y [26] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1317:
      Old ports: A={ $flatten\imem.\bmem.$procmux$1314_Y [29:28] $flatten\imem.\bmem.$procmux$1314_Y [26:0] }, B=29'00000000000000011011110110111, Y={ $flatten\imem.\bmem.$procmux$1317_Y [29:28] $flatten\imem.\bmem.$procmux$1317_Y [26:0] }
      New ports: A={ $flatten\imem.\bmem.$procmux$1314_Y [29:28] $flatten\imem.\bmem.$procmux$1314_Y [26:2] }, B=27'000000000000000110111101101, Y={ $flatten\imem.\bmem.$procmux$1317_Y [29:28] $flatten\imem.\bmem.$procmux$1317_Y [26:2] }
      New connections: $flatten\imem.\bmem.$procmux$1317_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1329:
      Old ports: A=$flatten\imem.\bmem.$procmux$1326_Y, B=32'11111100111001111111011011100011, Y=$flatten\imem.\bmem.$procmux$1329_Y
      New ports: A={ $flatten\imem.\bmem.$procmux$1326_Y [29:28] $flatten\imem.\bmem.$procmux$1326_Y [26:0] }, B=29'11100111001111111011011100011, Y={ $flatten\imem.\bmem.$procmux$1329_Y [29:28] $flatten\imem.\bmem.$procmux$1329_Y [26:0] }
      New connections: { $flatten\imem.\bmem.$procmux$1329_Y [31:30] $flatten\imem.\bmem.$procmux$1329_Y [27] } = { $flatten\imem.\bmem.$procmux$1329_Y [28] $flatten\imem.\bmem.$procmux$1329_Y [28] $flatten\imem.\bmem.$procmux$1329_Y [26] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1320:
      Old ports: A={ $flatten\imem.\bmem.$procmux$1317_Y [29:28] $flatten\imem.\bmem.$procmux$1317_Y [26:0] }, B=29'00111111101111111011100010011, Y={ $flatten\imem.\bmem.$procmux$1320_Y [29:28] $flatten\imem.\bmem.$procmux$1320_Y [26:0] }
      New ports: A={ $flatten\imem.\bmem.$procmux$1317_Y [29:28] $flatten\imem.\bmem.$procmux$1317_Y [26:2] }, B=27'001111111011111110111000100, Y={ $flatten\imem.\bmem.$procmux$1320_Y [29:28] $flatten\imem.\bmem.$procmux$1320_Y [26:2] }
      New connections: $flatten\imem.\bmem.$procmux$1320_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1332:
      Old ports: A=$flatten\imem.\bmem.$procmux$1329_Y, B=3147667, Y=$flatten\imem.\bmem.$procmux$1332_Y
      New ports: A={ $flatten\imem.\bmem.$procmux$1329_Y [29:28] $flatten\imem.\bmem.$procmux$1329_Y [26:0] }, B=29'00000001100000000011110010011, Y={ $flatten\imem.\bmem.$procmux$1332_Y [29:28] $flatten\imem.\bmem.$procmux$1332_Y [26:0] }
      New connections: { $flatten\imem.\bmem.$procmux$1332_Y [31:30] $flatten\imem.\bmem.$procmux$1332_Y [27] } = { $flatten\imem.\bmem.$procmux$1332_Y [28] $flatten\imem.\bmem.$procmux$1332_Y [28] $flatten\imem.\bmem.$procmux$1332_Y [26] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1323:
      Old ports: A={ $flatten\imem.\bmem.$procmux$1320_Y [29:28] $flatten\imem.\bmem.$procmux$1320_Y [26:0] }, B=29'00000010101111100011110000011, Y={ $flatten\imem.\bmem.$procmux$1323_Y [29:28] $flatten\imem.\bmem.$procmux$1323_Y [26:0] }
      New ports: A={ $flatten\imem.\bmem.$procmux$1320_Y [29:28] $flatten\imem.\bmem.$procmux$1320_Y [26:2] }, B=27'000000101011111000111100000, Y={ $flatten\imem.\bmem.$procmux$1323_Y [29:28] $flatten\imem.\bmem.$procmux$1323_Y [26:2] }
      New connections: $flatten\imem.\bmem.$procmux$1323_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1335:
      Old ports: A=$flatten\imem.\bmem.$procmux$1332_Y, B=32'11111110110001000010011100000011, Y=$flatten\imem.\bmem.$procmux$1335_Y
      New ports: A={ $flatten\imem.\bmem.$procmux$1332_Y [29:28] $flatten\imem.\bmem.$procmux$1332_Y [26:0] }, B=29'11110110001000010011100000011, Y={ $flatten\imem.\bmem.$procmux$1335_Y [29:28] $flatten\imem.\bmem.$procmux$1335_Y [26:0] }
      New connections: { $flatten\imem.\bmem.$procmux$1335_Y [31:30] $flatten\imem.\bmem.$procmux$1335_Y [27] } = { $flatten\imem.\bmem.$procmux$1335_Y [28] $flatten\imem.\bmem.$procmux$1335_Y [28] $flatten\imem.\bmem.$procmux$1335_Y [26] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1326:
      Old ports: A={ $flatten\imem.\bmem.$procmux$1323_Y [29:28] $flatten\imem.\bmem.$procmux$1323_Y [26:0] }, B=29'00000000000000011011110110111, Y={ $flatten\imem.\bmem.$procmux$1326_Y [29:28] $flatten\imem.\bmem.$procmux$1326_Y [26:0] }
      New ports: A={ $flatten\imem.\bmem.$procmux$1323_Y [29:28] $flatten\imem.\bmem.$procmux$1323_Y [26:2] }, B=27'000000000000000110111101101, Y={ $flatten\imem.\bmem.$procmux$1326_Y [29:28] $flatten\imem.\bmem.$procmux$1326_Y [26:2] }
      New connections: $flatten\imem.\bmem.$procmux$1326_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1338:
      Old ports: A=$flatten\imem.\bmem.$procmux$1335_Y, B=32'11111110111101000010011000100011, Y=$flatten\imem.\bmem.$procmux$1338_Y
      New ports: A={ $flatten\imem.\bmem.$procmux$1335_Y [29:28] $flatten\imem.\bmem.$procmux$1335_Y [26:0] }, B=29'11110111101000010011000100011, Y={ $flatten\imem.\bmem.$procmux$1338_Y [29:28] $flatten\imem.\bmem.$procmux$1338_Y [26:0] }
      New connections: { $flatten\imem.\bmem.$procmux$1338_Y [31:30] $flatten\imem.\bmem.$procmux$1338_Y [27] } = { $flatten\imem.\bmem.$procmux$1338_Y [28] $flatten\imem.\bmem.$procmux$1338_Y [28] $flatten\imem.\bmem.$procmux$1338_Y [26] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1329:
      Old ports: A={ $flatten\imem.\bmem.$procmux$1326_Y [29:28] $flatten\imem.\bmem.$procmux$1326_Y [26:0] }, B=29'11100111001111111011011100011, Y={ $flatten\imem.\bmem.$procmux$1329_Y [29:28] $flatten\imem.\bmem.$procmux$1329_Y [26:0] }
      New ports: A={ $flatten\imem.\bmem.$procmux$1326_Y [29:28] $flatten\imem.\bmem.$procmux$1326_Y [26:2] }, B=27'111001110011111110110111000, Y={ $flatten\imem.\bmem.$procmux$1329_Y [29:28] $flatten\imem.\bmem.$procmux$1329_Y [26:2] }
      New connections: $flatten\imem.\bmem.$procmux$1329_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1341:
      Old ports: A=$flatten\imem.\bmem.$procmux$1338_Y, B=1542035, Y=$flatten\imem.\bmem.$procmux$1341_Y
      New ports: A={ $flatten\imem.\bmem.$procmux$1338_Y [29:28] $flatten\imem.\bmem.$procmux$1338_Y [26:0] }, B=29'00000000101111000011110010011, Y={ $flatten\imem.\bmem.$procmux$1341_Y [29:28] $flatten\imem.\bmem.$procmux$1341_Y [26:0] }
      New connections: { $flatten\imem.\bmem.$procmux$1341_Y [31:30] $flatten\imem.\bmem.$procmux$1341_Y [27] } = { $flatten\imem.\bmem.$procmux$1341_Y [28] $flatten\imem.\bmem.$procmux$1341_Y [28] $flatten\imem.\bmem.$procmux$1341_Y [26] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1332:
      Old ports: A={ $flatten\imem.\bmem.$procmux$1329_Y [29:28] $flatten\imem.\bmem.$procmux$1329_Y [26:0] }, B=29'00000001100000000011110010011, Y={ $flatten\imem.\bmem.$procmux$1332_Y [29:28] $flatten\imem.\bmem.$procmux$1332_Y [26:0] }
      New ports: A={ $flatten\imem.\bmem.$procmux$1329_Y [29:28] $flatten\imem.\bmem.$procmux$1329_Y [26:2] }, B=27'000000011000000000111100100, Y={ $flatten\imem.\bmem.$procmux$1332_Y [29:28] $flatten\imem.\bmem.$procmux$1332_Y [26:2] }
      New connections: $flatten\imem.\bmem.$procmux$1332_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1344:
      Old ports: A=$flatten\imem.\bmem.$procmux$1341_Y, B=32'11111110110001000010011110000011, Y=$flatten\imem.\bmem.$procmux$1344_Y
      New ports: A={ $flatten\imem.\bmem.$procmux$1341_Y [29:28] $flatten\imem.\bmem.$procmux$1341_Y [26:0] }, B=29'11110110001000010011110000011, Y={ $flatten\imem.\bmem.$procmux$1344_Y [29:28] $flatten\imem.\bmem.$procmux$1344_Y [26:0] }
      New connections: { $flatten\imem.\bmem.$procmux$1344_Y [31:30] $flatten\imem.\bmem.$procmux$1344_Y [27] } = { $flatten\imem.\bmem.$procmux$1344_Y [28] $flatten\imem.\bmem.$procmux$1344_Y [28] $flatten\imem.\bmem.$procmux$1344_Y [26] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1335:
      Old ports: A={ $flatten\imem.\bmem.$procmux$1332_Y [29:28] $flatten\imem.\bmem.$procmux$1332_Y [26:0] }, B=29'11110110001000010011100000011, Y={ $flatten\imem.\bmem.$procmux$1335_Y [29:28] $flatten\imem.\bmem.$procmux$1335_Y [26:0] }
      New ports: A={ $flatten\imem.\bmem.$procmux$1332_Y [29:28] $flatten\imem.\bmem.$procmux$1332_Y [26:2] }, B=27'111101100010000100111000000, Y={ $flatten\imem.\bmem.$procmux$1335_Y [29:28] $flatten\imem.\bmem.$procmux$1335_Y [26:2] }
      New connections: $flatten\imem.\bmem.$procmux$1335_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1347:
      Old ports: A=$flatten\imem.\bmem.$procmux$1344_Y, B=32'11111110111001111000110000100011, Y=$flatten\imem.\bmem.$procmux$1347_Y
      New ports: A={ $flatten\imem.\bmem.$procmux$1344_Y [29:28] $flatten\imem.\bmem.$procmux$1344_Y [26:0] }, B=29'11110111001111000110000100011, Y={ $flatten\imem.\bmem.$procmux$1347_Y [29:28] $flatten\imem.\bmem.$procmux$1347_Y [26:0] }
      New connections: { $flatten\imem.\bmem.$procmux$1347_Y [31:30] $flatten\imem.\bmem.$procmux$1347_Y [27] } = { $flatten\imem.\bmem.$procmux$1347_Y [28] $flatten\imem.\bmem.$procmux$1347_Y [28] $flatten\imem.\bmem.$procmux$1347_Y [26] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1338:
      Old ports: A={ $flatten\imem.\bmem.$procmux$1335_Y [29:28] $flatten\imem.\bmem.$procmux$1335_Y [26:0] }, B=29'11110111101000010011000100011, Y={ $flatten\imem.\bmem.$procmux$1338_Y [29:28] $flatten\imem.\bmem.$procmux$1338_Y [26:0] }
      New ports: A={ $flatten\imem.\bmem.$procmux$1335_Y [29:28] $flatten\imem.\bmem.$procmux$1335_Y [26:2] }, B=27'111101111010000100110001000, Y={ $flatten\imem.\bmem.$procmux$1338_Y [29:28] $flatten\imem.\bmem.$procmux$1338_Y [26:2] }
      New connections: $flatten\imem.\bmem.$procmux$1338_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1350:
      Old ports: A=$flatten\imem.\bmem.$procmux$1347_Y, B=16156595, Y=$flatten\imem.\bmem.$procmux$1350_Y
      New ports: A={ $flatten\imem.\bmem.$procmux$1347_Y [29:28] $flatten\imem.\bmem.$procmux$1347_Y [26:0] }, B=29'00000111101101000011110110011, Y={ $flatten\imem.\bmem.$procmux$1350_Y [29:28] $flatten\imem.\bmem.$procmux$1350_Y [26:0] }
      New connections: { $flatten\imem.\bmem.$procmux$1350_Y [31:30] $flatten\imem.\bmem.$procmux$1350_Y [27] } = { $flatten\imem.\bmem.$procmux$1350_Y [28] $flatten\imem.\bmem.$procmux$1350_Y [28] $flatten\imem.\bmem.$procmux$1350_Y [26] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1341:
      Old ports: A={ $flatten\imem.\bmem.$procmux$1338_Y [29:28] $flatten\imem.\bmem.$procmux$1338_Y [26:0] }, B=29'00000000101111000011110010011, Y={ $flatten\imem.\bmem.$procmux$1341_Y [29:28] $flatten\imem.\bmem.$procmux$1341_Y [26:0] }
      New ports: A={ $flatten\imem.\bmem.$procmux$1338_Y [29:28] $flatten\imem.\bmem.$procmux$1338_Y [26:2] }, B=27'000000001011110000111100100, Y={ $flatten\imem.\bmem.$procmux$1341_Y [29:28] $flatten\imem.\bmem.$procmux$1341_Y [26:2] }
      New connections: $flatten\imem.\bmem.$procmux$1341_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1353:
      Old ports: A=$flatten\imem.\bmem.$procmux$1350_Y, B=32'11111111000001000000011010010011, Y=$flatten\imem.\bmem.$procmux$1353_Y
      New ports: A={ $flatten\imem.\bmem.$procmux$1350_Y [29:28] $flatten\imem.\bmem.$procmux$1350_Y [26:0] }, B=29'11111000001000000011010010011, Y={ $flatten\imem.\bmem.$procmux$1353_Y [29:28] $flatten\imem.\bmem.$procmux$1353_Y [26:0] }
      New connections: { $flatten\imem.\bmem.$procmux$1353_Y [31:30] $flatten\imem.\bmem.$procmux$1353_Y [27] } = { $flatten\imem.\bmem.$procmux$1353_Y [28] $flatten\imem.\bmem.$procmux$1353_Y [28] $flatten\imem.\bmem.$procmux$1353_Y [26] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1344:
      Old ports: A={ $flatten\imem.\bmem.$procmux$1341_Y [29:28] $flatten\imem.\bmem.$procmux$1341_Y [26:0] }, B=29'11110110001000010011110000011, Y={ $flatten\imem.\bmem.$procmux$1344_Y [29:28] $flatten\imem.\bmem.$procmux$1344_Y [26:0] }
      New ports: A={ $flatten\imem.\bmem.$procmux$1341_Y [29:28] $flatten\imem.\bmem.$procmux$1341_Y [26:2] }, B=27'111101100010000100111100000, Y={ $flatten\imem.\bmem.$procmux$1344_Y [29:28] $flatten\imem.\bmem.$procmux$1344_Y [26:2] }
      New connections: $flatten\imem.\bmem.$procmux$1344_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1356:
      Old ports: A=$flatten\imem.\bmem.$procmux$1353_Y, B=32'11111110110001000010011110000011, Y=$flatten\imem.\bmem.$procmux$1356_Y
      New ports: A={ $flatten\imem.\bmem.$procmux$1353_Y [29:28] $flatten\imem.\bmem.$procmux$1353_Y [26:0] }, B=29'11110110001000010011110000011, Y={ $flatten\imem.\bmem.$procmux$1356_Y [29:28] $flatten\imem.\bmem.$procmux$1356_Y [26:0] }
      New connections: { $flatten\imem.\bmem.$procmux$1356_Y [31:30] $flatten\imem.\bmem.$procmux$1356_Y [27] } = { $flatten\imem.\bmem.$procmux$1356_Y [28] $flatten\imem.\bmem.$procmux$1356_Y [28] $flatten\imem.\bmem.$procmux$1356_Y [26] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1347:
      Old ports: A={ $flatten\imem.\bmem.$procmux$1344_Y [29:28] $flatten\imem.\bmem.$procmux$1344_Y [26:0] }, B=29'11110111001111000110000100011, Y={ $flatten\imem.\bmem.$procmux$1347_Y [29:28] $flatten\imem.\bmem.$procmux$1347_Y [26:0] }
      New ports: A={ $flatten\imem.\bmem.$procmux$1344_Y [29:28] $flatten\imem.\bmem.$procmux$1344_Y [26:2] }, B=27'111101110011110001100001000, Y={ $flatten\imem.\bmem.$procmux$1347_Y [29:28] $flatten\imem.\bmem.$procmux$1347_Y [26:2] }
      New connections: $flatten\imem.\bmem.$procmux$1347_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1359:
      Old ports: A=$flatten\imem.\bmem.$procmux$1356_Y, B=493331, Y=$flatten\imem.\bmem.$procmux$1359_Y
      New ports: A={ $flatten\imem.\bmem.$procmux$1356_Y [29:28] $flatten\imem.\bmem.$procmux$1356_Y [26:0] }, B=29'00000000001111000011100010011, Y={ $flatten\imem.\bmem.$procmux$1359_Y [29:28] $flatten\imem.\bmem.$procmux$1359_Y [26:0] }
      New connections: { $flatten\imem.\bmem.$procmux$1359_Y [31:30] $flatten\imem.\bmem.$procmux$1359_Y [27] } = { $flatten\imem.\bmem.$procmux$1359_Y [28] $flatten\imem.\bmem.$procmux$1359_Y [28] $flatten\imem.\bmem.$procmux$1359_Y [26] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1350:
      Old ports: A={ $flatten\imem.\bmem.$procmux$1347_Y [29:28] $flatten\imem.\bmem.$procmux$1347_Y [26:0] }, B=29'00000111101101000011110110011, Y={ $flatten\imem.\bmem.$procmux$1350_Y [29:28] $flatten\imem.\bmem.$procmux$1350_Y [26:0] }
      New ports: A={ $flatten\imem.\bmem.$procmux$1347_Y [29:28] $flatten\imem.\bmem.$procmux$1347_Y [26:2] }, B=27'000001111011010000111101100, Y={ $flatten\imem.\bmem.$procmux$1350_Y [29:28] $flatten\imem.\bmem.$procmux$1350_Y [26:2] }
      New connections: $flatten\imem.\bmem.$procmux$1350_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1362:
      Old ports: A=$flatten\imem.\bmem.$procmux$1359_Y, B=329619, Y=$flatten\imem.\bmem.$procmux$1362_Y
      New ports: A={ $flatten\imem.\bmem.$procmux$1359_Y [29:28] $flatten\imem.\bmem.$procmux$1359_Y [26:0] }, B=29'00000000001010000011110010011, Y={ $flatten\imem.\bmem.$procmux$1362_Y [29:28] $flatten\imem.\bmem.$procmux$1362_Y [26:0] }
      New connections: { $flatten\imem.\bmem.$procmux$1362_Y [31:30] $flatten\imem.\bmem.$procmux$1362_Y [27] } = { $flatten\imem.\bmem.$procmux$1362_Y [28] $flatten\imem.\bmem.$procmux$1362_Y [28] $flatten\imem.\bmem.$procmux$1362_Y [26] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1353:
      Old ports: A={ $flatten\imem.\bmem.$procmux$1350_Y [29:28] $flatten\imem.\bmem.$procmux$1350_Y [26:0] }, B=29'11111000001000000011010010011, Y={ $flatten\imem.\bmem.$procmux$1353_Y [29:28] $flatten\imem.\bmem.$procmux$1353_Y [26:0] }
      New ports: A={ $flatten\imem.\bmem.$procmux$1350_Y [29:28] $flatten\imem.\bmem.$procmux$1350_Y [26:2] }, B=27'111110000010000000110100100, Y={ $flatten\imem.\bmem.$procmux$1353_Y [29:28] $flatten\imem.\bmem.$procmux$1353_Y [26:2] }
      New connections: $flatten\imem.\bmem.$procmux$1353_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1365:
      Old ports: A=$flatten\imem.\bmem.$procmux$1362_Y, B=32'11011100100111111111000011101111, Y=$flatten\imem.\bmem.$procmux$1365_Y
      New ports: A={ $flatten\imem.\bmem.$procmux$1362_Y [29:28] $flatten\imem.\bmem.$procmux$1362_Y [26:0] }, B=29'01100100111111111000011101111, Y={ $flatten\imem.\bmem.$procmux$1365_Y [29:28] $flatten\imem.\bmem.$procmux$1365_Y [26:0] }
      New connections: { $flatten\imem.\bmem.$procmux$1365_Y [31:30] $flatten\imem.\bmem.$procmux$1365_Y [27] } = { $flatten\imem.\bmem.$procmux$1365_Y [28] $flatten\imem.\bmem.$procmux$1365_Y [28] $flatten\imem.\bmem.$procmux$1365_Y [26] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1356:
      Old ports: A={ $flatten\imem.\bmem.$procmux$1353_Y [29:28] $flatten\imem.\bmem.$procmux$1353_Y [26:0] }, B=29'11110110001000010011110000011, Y={ $flatten\imem.\bmem.$procmux$1356_Y [29:28] $flatten\imem.\bmem.$procmux$1356_Y [26:0] }
      New ports: A={ $flatten\imem.\bmem.$procmux$1353_Y [29:28] $flatten\imem.\bmem.$procmux$1353_Y [26:2] }, B=27'111101100010000100111100000, Y={ $flatten\imem.\bmem.$procmux$1356_Y [29:28] $flatten\imem.\bmem.$procmux$1356_Y [26:2] }
      New connections: $flatten\imem.\bmem.$procmux$1356_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1368:
      Old ports: A=$flatten\imem.\bmem.$procmux$1365_Y, B=1299, Y=$flatten\imem.\bmem.$procmux$1368_Y
      New ports: A={ $flatten\imem.\bmem.$procmux$1365_Y [29:28] $flatten\imem.\bmem.$procmux$1365_Y [26:0] }, B=29'00000000000000000010100010011, Y={ $flatten\imem.\bmem.$procmux$1368_Y [29:28] $flatten\imem.\bmem.$procmux$1368_Y [26:0] }
      New connections: { $flatten\imem.\bmem.$procmux$1368_Y [31:30] $flatten\imem.\bmem.$procmux$1368_Y [27] } = { $flatten\imem.\bmem.$procmux$1368_Y [28] $flatten\imem.\bmem.$procmux$1368_Y [28] $flatten\imem.\bmem.$procmux$1368_Y [26] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1359:
      Old ports: A={ $flatten\imem.\bmem.$procmux$1356_Y [29:28] $flatten\imem.\bmem.$procmux$1356_Y [26:0] }, B=29'00000000001111000011100010011, Y={ $flatten\imem.\bmem.$procmux$1359_Y [29:28] $flatten\imem.\bmem.$procmux$1359_Y [26:0] }
      New ports: A={ $flatten\imem.\bmem.$procmux$1356_Y [29:28] $flatten\imem.\bmem.$procmux$1356_Y [26:2] }, B=27'000000000011110000111000100, Y={ $flatten\imem.\bmem.$procmux$1359_Y [29:28] $flatten\imem.\bmem.$procmux$1359_Y [26:2] }
      New connections: $flatten\imem.\bmem.$procmux$1359_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1371:
      Old ports: A=$flatten\imem.\bmem.$procmux$1368_Y, B=50331759, Y=$flatten\imem.\bmem.$procmux$1371_Y
      New ports: A={ $flatten\imem.\bmem.$procmux$1368_Y [29:28] $flatten\imem.\bmem.$procmux$1368_Y [26:0] }, B=29'00011000000000000000001101111, Y={ $flatten\imem.\bmem.$procmux$1371_Y [29:28] $flatten\imem.\bmem.$procmux$1371_Y [26:0] }
      New connections: { $flatten\imem.\bmem.$procmux$1371_Y [31:30] $flatten\imem.\bmem.$procmux$1371_Y [27] } = { $flatten\imem.\bmem.$procmux$1371_Y [28] $flatten\imem.\bmem.$procmux$1371_Y [28] $flatten\imem.\bmem.$procmux$1371_Y [26] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1362:
      Old ports: A={ $flatten\imem.\bmem.$procmux$1359_Y [29:28] $flatten\imem.\bmem.$procmux$1359_Y [26:0] }, B=29'00000000001010000011110010011, Y={ $flatten\imem.\bmem.$procmux$1362_Y [29:28] $flatten\imem.\bmem.$procmux$1362_Y [26:0] }
      New ports: A={ $flatten\imem.\bmem.$procmux$1359_Y [29:28] $flatten\imem.\bmem.$procmux$1359_Y [26:2] }, B=27'000000000010100000111100100, Y={ $flatten\imem.\bmem.$procmux$1362_Y [29:28] $flatten\imem.\bmem.$procmux$1362_Y [26:2] }
      New connections: $flatten\imem.\bmem.$procmux$1362_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1374:
      Old ports: A=$flatten\imem.\bmem.$procmux$1371_Y, B=32'11111110000001000010011000100011, Y=$flatten\imem.\bmem.$procmux$1374_Y
      New ports: A={ $flatten\imem.\bmem.$procmux$1371_Y [29:28] $flatten\imem.\bmem.$procmux$1371_Y [26:0] }, B=29'11110000001000010011000100011, Y={ $flatten\imem.\bmem.$procmux$1374_Y [29:28] $flatten\imem.\bmem.$procmux$1374_Y [26:0] }
      New connections: { $flatten\imem.\bmem.$procmux$1374_Y [31:30] $flatten\imem.\bmem.$procmux$1374_Y [27] } = { $flatten\imem.\bmem.$procmux$1374_Y [28] $flatten\imem.\bmem.$procmux$1374_Y [28] $flatten\imem.\bmem.$procmux$1374_Y [26] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1365:
      Old ports: A={ $flatten\imem.\bmem.$procmux$1362_Y [29:28] $flatten\imem.\bmem.$procmux$1362_Y [26:0] }, B=29'01100100111111111000011101111, Y={ $flatten\imem.\bmem.$procmux$1365_Y [29:28] $flatten\imem.\bmem.$procmux$1365_Y [26:0] }
      New ports: A={ $flatten\imem.\bmem.$procmux$1362_Y [29:28] $flatten\imem.\bmem.$procmux$1362_Y [26:2] }, B=27'011001001111111110000111011, Y={ $flatten\imem.\bmem.$procmux$1365_Y [29:28] $flatten\imem.\bmem.$procmux$1365_Y [26:2] }
      New connections: $flatten\imem.\bmem.$procmux$1365_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1377:
      Old ports: A=$flatten\imem.\bmem.$procmux$1374_Y, B=125829359, Y=$flatten\imem.\bmem.$procmux$1377_Y
      New ports: A={ $flatten\imem.\bmem.$procmux$1374_Y [29:28] $flatten\imem.\bmem.$procmux$1374_Y [26] $flatten\imem.\bmem.$procmux$1374_Y [26:0] }, B=30'000111100000000000000011101111, Y=$flatten\imem.\bmem.$procmux$1377_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1377_Y [31:30] = { $flatten\imem.\bmem.$procmux$1377_Y [28] $flatten\imem.\bmem.$procmux$1377_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1368:
      Old ports: A={ $flatten\imem.\bmem.$procmux$1365_Y [29:28] $flatten\imem.\bmem.$procmux$1365_Y [26:0] }, B=29'00000000000000000010100010011, Y={ $flatten\imem.\bmem.$procmux$1368_Y [29:28] $flatten\imem.\bmem.$procmux$1368_Y [26:0] }
      New ports: A={ $flatten\imem.\bmem.$procmux$1365_Y [29:28] $flatten\imem.\bmem.$procmux$1365_Y [26:2] }, B=27'000000000000000000101000100, Y={ $flatten\imem.\bmem.$procmux$1368_Y [29:28] $flatten\imem.\bmem.$procmux$1368_Y [26:2] }
      New connections: $flatten\imem.\bmem.$procmux$1368_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1380:
      Old ports: A=$flatten\imem.\bmem.$procmux$1377_Y, B=32'11111101110001000010010100000011, Y=$flatten\imem.\bmem.$procmux$1380_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1377_Y [29:0], B=30'111101110001000010010100000011, Y=$flatten\imem.\bmem.$procmux$1380_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1380_Y [31:30] = { $flatten\imem.\bmem.$procmux$1380_Y [28] $flatten\imem.\bmem.$procmux$1380_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1371:
      Old ports: A={ $flatten\imem.\bmem.$procmux$1368_Y [29:28] $flatten\imem.\bmem.$procmux$1368_Y [26:0] }, B=29'00011000000000000000001101111, Y={ $flatten\imem.\bmem.$procmux$1371_Y [29:28] $flatten\imem.\bmem.$procmux$1371_Y [26:0] }
      New ports: A={ $flatten\imem.\bmem.$procmux$1368_Y [29:28] $flatten\imem.\bmem.$procmux$1368_Y [26:2] }, B=27'000110000000000000000011011, Y={ $flatten\imem.\bmem.$procmux$1371_Y [29:28] $flatten\imem.\bmem.$procmux$1371_Y [26:2] }
      New connections: $flatten\imem.\bmem.$procmux$1371_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1383:
      Old ports: A=$flatten\imem.\bmem.$procmux$1380_Y, B=32'11011110000111111111000011101111, Y=$flatten\imem.\bmem.$procmux$1383_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1380_Y [29:0], B=30'011110000111111111000011101111, Y=$flatten\imem.\bmem.$procmux$1383_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1383_Y [31:30] = { $flatten\imem.\bmem.$procmux$1383_Y [28] $flatten\imem.\bmem.$procmux$1383_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1374:
      Old ports: A={ $flatten\imem.\bmem.$procmux$1371_Y [29:28] $flatten\imem.\bmem.$procmux$1371_Y [26:0] }, B=29'11110000001000010011000100011, Y={ $flatten\imem.\bmem.$procmux$1374_Y [29:28] $flatten\imem.\bmem.$procmux$1374_Y [26:0] }
      New ports: A={ $flatten\imem.\bmem.$procmux$1371_Y [29:28] $flatten\imem.\bmem.$procmux$1371_Y [26:2] }, B=27'111100000010000100110001000, Y={ $flatten\imem.\bmem.$procmux$1374_Y [29:28] $flatten\imem.\bmem.$procmux$1374_Y [26:2] }
      New connections: $flatten\imem.\bmem.$procmux$1374_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1386:
      Old ports: A=$flatten\imem.\bmem.$procmux$1383_Y, B=3147027, Y=$flatten\imem.\bmem.$procmux$1386_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1383_Y [29:0], B=30'000000001100000000010100010011, Y=$flatten\imem.\bmem.$procmux$1386_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1386_Y [31:30] = { $flatten\imem.\bmem.$procmux$1386_Y [28] $flatten\imem.\bmem.$procmux$1386_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1377:
      Old ports: A={ $flatten\imem.\bmem.$procmux$1374_Y [29:28] $flatten\imem.\bmem.$procmux$1374_Y [26] $flatten\imem.\bmem.$procmux$1374_Y [26:0] }, B=30'000111100000000000000011101111, Y=$flatten\imem.\bmem.$procmux$1377_Y [29:0]
      New ports: A={ $flatten\imem.\bmem.$procmux$1374_Y [29:28] $flatten\imem.\bmem.$procmux$1374_Y [26] $flatten\imem.\bmem.$procmux$1374_Y [26:2] }, B=28'0001111000000000000000111011, Y=$flatten\imem.\bmem.$procmux$1377_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1377_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1389:
      Old ports: A=$flatten\imem.\bmem.$procmux$1386_Y, B=15172259, Y=$flatten\imem.\bmem.$procmux$1389_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1386_Y [29:0], B=30'000000111001111000001010100011, Y=$flatten\imem.\bmem.$procmux$1389_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1389_Y [31:30] = { $flatten\imem.\bmem.$procmux$1389_Y [28] $flatten\imem.\bmem.$procmux$1389_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1380:
      Old ports: A=$flatten\imem.\bmem.$procmux$1377_Y [29:0], B=30'111101110001000010010100000011, Y=$flatten\imem.\bmem.$procmux$1380_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1377_Y [29:2], B=28'1111011100010000100101000000, Y=$flatten\imem.\bmem.$procmux$1380_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1380_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1392:
      Old ports: A=$flatten\imem.\bmem.$procmux$1389_Y, B=267876115, Y=$flatten\imem.\bmem.$procmux$1392_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1389_Y [29:0], B=30'001111111101110111011100010011, Y=$flatten\imem.\bmem.$procmux$1392_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1392_Y [31:30] = { $flatten\imem.\bmem.$procmux$1392_Y [28] $flatten\imem.\bmem.$procmux$1392_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1383:
      Old ports: A=$flatten\imem.\bmem.$procmux$1380_Y [29:0], B=30'011110000111111111000011101111, Y=$flatten\imem.\bmem.$procmux$1383_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1380_Y [29:2], B=28'0111100001111111110000111011, Y=$flatten\imem.\bmem.$procmux$1383_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1383_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1395:
      Old ports: A=$flatten\imem.\bmem.$procmux$1392_Y, B=1533715, Y=$flatten\imem.\bmem.$procmux$1395_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1392_Y [29:0], B=30'000000000101110110011100010011, Y=$flatten\imem.\bmem.$procmux$1395_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1395_Y [31:30] = { $flatten\imem.\bmem.$procmux$1395_Y [28] $flatten\imem.\bmem.$procmux$1395_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1386:
      Old ports: A=$flatten\imem.\bmem.$procmux$1383_Y [29:0], B=30'000000001100000000010100010011, Y=$flatten\imem.\bmem.$procmux$1386_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1383_Y [29:2], B=28'0000000011000000000101000100, Y=$flatten\imem.\bmem.$procmux$1386_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1386_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1398:
      Old ports: A=$flatten\imem.\bmem.$procmux$1395_Y, B=14263, Y=$flatten\imem.\bmem.$procmux$1398_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1395_Y [29:0], B=30'000000000000000011011110110111, Y=$flatten\imem.\bmem.$procmux$1398_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1398_Y [31:30] = { $flatten\imem.\bmem.$procmux$1398_Y [28] $flatten\imem.\bmem.$procmux$1398_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1389:
      Old ports: A=$flatten\imem.\bmem.$procmux$1386_Y [29:0], B=30'000000111001111000001010100011, Y=$flatten\imem.\bmem.$procmux$1389_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1386_Y [29:2], B=28'0000001110011110000010101000, Y=$flatten\imem.\bmem.$procmux$1389_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1389_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1401:
      Old ports: A=$flatten\imem.\bmem.$procmux$1398_Y, B=267908883, Y=$flatten\imem.\bmem.$procmux$1401_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1398_Y [29:0], B=30'001111111101111111011100010011, Y=$flatten\imem.\bmem.$procmux$1401_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1401_Y [31:30] = { $flatten\imem.\bmem.$procmux$1401_Y [28] $flatten\imem.\bmem.$procmux$1401_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1392:
      Old ports: A=$flatten\imem.\bmem.$procmux$1389_Y [29:0], B=30'001111111101110111011100010011, Y=$flatten\imem.\bmem.$procmux$1392_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1389_Y [29:2], B=28'0011111111011101110111000100, Y=$flatten\imem.\bmem.$procmux$1392_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1392_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1404:
      Old ports: A=$flatten\imem.\bmem.$procmux$1401_Y, B=5752707, Y=$flatten\imem.\bmem.$procmux$1404_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1401_Y [29:0], B=30'000000010101111100011110000011, Y=$flatten\imem.\bmem.$procmux$1404_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1404_Y [31:30] = { $flatten\imem.\bmem.$procmux$1404_Y [28] $flatten\imem.\bmem.$procmux$1404_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1395:
      Old ports: A=$flatten\imem.\bmem.$procmux$1392_Y [29:0], B=30'000000000101110110011100010011, Y=$flatten\imem.\bmem.$procmux$1395_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1392_Y [29:2], B=28'0000000001011101100111000100, Y=$flatten\imem.\bmem.$procmux$1395_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1395_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1407:
      Old ports: A=$flatten\imem.\bmem.$procmux$1404_Y, B=14263, Y=$flatten\imem.\bmem.$procmux$1407_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1404_Y [29:0], B=30'000000000000000011011110110111, Y=$flatten\imem.\bmem.$procmux$1407_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1407_Y [31:30] = { $flatten\imem.\bmem.$procmux$1407_Y [28] $flatten\imem.\bmem.$procmux$1407_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1398:
      Old ports: A=$flatten\imem.\bmem.$procmux$1395_Y [29:0], B=30'000000000000000011011110110111, Y=$flatten\imem.\bmem.$procmux$1398_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1395_Y [29:2], B=28'0000000000000000110111101101, Y=$flatten\imem.\bmem.$procmux$1398_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1398_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1410:
      Old ports: A=$flatten\imem.\bmem.$procmux$1407_Y, B=32'11111100101001000010111000100011, Y=$flatten\imem.\bmem.$procmux$1410_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1407_Y [29:0], B=30'111100101001000010111000100011, Y=$flatten\imem.\bmem.$procmux$1410_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1410_Y [31:30] = { $flatten\imem.\bmem.$procmux$1410_Y [28] $flatten\imem.\bmem.$procmux$1410_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1401:
      Old ports: A=$flatten\imem.\bmem.$procmux$1398_Y [29:0], B=30'001111111101111111011100010011, Y=$flatten\imem.\bmem.$procmux$1401_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1398_Y [29:2], B=28'0011111111011111110111000100, Y=$flatten\imem.\bmem.$procmux$1401_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1401_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1413:
      Old ports: A=$flatten\imem.\bmem.$procmux$1410_Y, B=50398227, Y=$flatten\imem.\bmem.$procmux$1413_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1410_Y [29:0], B=30'000011000000010000010000010011, Y=$flatten\imem.\bmem.$procmux$1413_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1413_Y [31:30] = { $flatten\imem.\bmem.$procmux$1413_Y [28] $flatten\imem.\bmem.$procmux$1413_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1404:
      Old ports: A=$flatten\imem.\bmem.$procmux$1401_Y [29:0], B=30'000000010101111100011110000011, Y=$flatten\imem.\bmem.$procmux$1404_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1401_Y [29:2], B=28'0000000101011111000111100000, Y=$flatten\imem.\bmem.$procmux$1404_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1404_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1416:
      Old ports: A=$flatten\imem.\bmem.$procmux$1413_Y, B=42017827, Y=$flatten\imem.\bmem.$procmux$1416_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1413_Y [29:0], B=30'000010100000010010010000100011, Y=$flatten\imem.\bmem.$procmux$1416_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1416_Y [31:30] = { $flatten\imem.\bmem.$procmux$1416_Y [28] $flatten\imem.\bmem.$procmux$1416_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1407:
      Old ports: A=$flatten\imem.\bmem.$procmux$1404_Y [29:0], B=30'000000000000000011011110110111, Y=$flatten\imem.\bmem.$procmux$1407_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1404_Y [29:2], B=28'0000000000000000110111101101, Y=$flatten\imem.\bmem.$procmux$1407_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1407_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1419:
      Old ports: A=$flatten\imem.\bmem.$procmux$1416_Y, B=34678307, Y=$flatten\imem.\bmem.$procmux$1419_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1416_Y [29:0], B=30'000010000100010010011000100011, Y=$flatten\imem.\bmem.$procmux$1419_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1419_Y [31:30] = { $flatten\imem.\bmem.$procmux$1419_Y [28] $flatten\imem.\bmem.$procmux$1419_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1410:
      Old ports: A=$flatten\imem.\bmem.$procmux$1407_Y [29:0], B=30'111100101001000010111000100011, Y=$flatten\imem.\bmem.$procmux$1410_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1407_Y [29:2], B=28'1111001010010000101110001000, Y=$flatten\imem.\bmem.$procmux$1410_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1410_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1422:
      Old ports: A=$flatten\imem.\bmem.$procmux$1419_Y, B=32'11111101000000010000000100010011, Y=$flatten\imem.\bmem.$procmux$1422_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1419_Y [29:0], B=30'111101000000010000000100010011, Y=$flatten\imem.\bmem.$procmux$1422_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1422_Y [31:30] = { $flatten\imem.\bmem.$procmux$1422_Y [28] $flatten\imem.\bmem.$procmux$1422_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1413:
      Old ports: A=$flatten\imem.\bmem.$procmux$1410_Y [29:0], B=30'000011000000010000010000010011, Y=$flatten\imem.\bmem.$procmux$1413_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1410_Y [29:2], B=28'0000110000000100000100000100, Y=$flatten\imem.\bmem.$procmux$1413_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1413_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1425:
      Old ports: A=$flatten\imem.\bmem.$procmux$1422_Y, B=32871, Y=$flatten\imem.\bmem.$procmux$1425_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1422_Y [29:0], B=30'000000000000001000000001100111, Y=$flatten\imem.\bmem.$procmux$1425_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1425_Y [31:30] = { $flatten\imem.\bmem.$procmux$1425_Y [28] $flatten\imem.\bmem.$procmux$1425_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1416:
      Old ports: A=$flatten\imem.\bmem.$procmux$1413_Y [29:0], B=30'000010100000010010010000100011, Y=$flatten\imem.\bmem.$procmux$1416_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1413_Y [29:2], B=28'0000101000000100100100001000, Y=$flatten\imem.\bmem.$procmux$1416_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1416_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1428:
      Old ports: A=$flatten\imem.\bmem.$procmux$1425_Y, B=50397459, Y=$flatten\imem.\bmem.$procmux$1428_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1425_Y [29:0], B=30'000011000000010000000100010011, Y=$flatten\imem.\bmem.$procmux$1428_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1428_Y [31:30] = { $flatten\imem.\bmem.$procmux$1428_Y [28] $flatten\imem.\bmem.$procmux$1428_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1419:
      Old ports: A=$flatten\imem.\bmem.$procmux$1416_Y [29:0], B=30'000010000100010010011000100011, Y=$flatten\imem.\bmem.$procmux$1419_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1416_Y [29:2], B=28'0000100001000100100110001000, Y=$flatten\imem.\bmem.$procmux$1419_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1419_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1431:
      Old ports: A=$flatten\imem.\bmem.$procmux$1428_Y, B=42017795, Y=$flatten\imem.\bmem.$procmux$1431_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1428_Y [29:0], B=30'000010100000010010010000000011, Y=$flatten\imem.\bmem.$procmux$1431_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1431_Y [31:30] = { $flatten\imem.\bmem.$procmux$1431_Y [28] $flatten\imem.\bmem.$procmux$1431_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1422:
      Old ports: A=$flatten\imem.\bmem.$procmux$1419_Y [29:0], B=30'111101000000010000000100010011, Y=$flatten\imem.\bmem.$procmux$1422_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1419_Y [29:2], B=28'1111010000000100000001000100, Y=$flatten\imem.\bmem.$procmux$1422_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1422_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1434:
      Old ports: A=$flatten\imem.\bmem.$procmux$1431_Y, B=46211203, Y=$flatten\imem.\bmem.$procmux$1434_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1431_Y [29:0], B=30'000010110000010010000010000011, Y=$flatten\imem.\bmem.$procmux$1434_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1434_Y [31:30] = { $flatten\imem.\bmem.$procmux$1434_Y [28] $flatten\imem.\bmem.$procmux$1434_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1425:
      Old ports: A=$flatten\imem.\bmem.$procmux$1422_Y [29:0], B=30'000000000000001000000001100111, Y=$flatten\imem.\bmem.$procmux$1425_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1422_Y [29:2], B=28'0000000000000010000000011001, Y=$flatten\imem.\bmem.$procmux$1425_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1425_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1437:
      Old ports: A=$flatten\imem.\bmem.$procmux$1434_Y, B=19, Y=$flatten\imem.\bmem.$procmux$1437_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1434_Y [29:0], B=30'000000000000000000000000010011, Y=$flatten\imem.\bmem.$procmux$1437_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1437_Y [31:30] = { $flatten\imem.\bmem.$procmux$1437_Y [28] $flatten\imem.\bmem.$procmux$1437_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1428:
      Old ports: A=$flatten\imem.\bmem.$procmux$1425_Y [29:0], B=30'000011000000010000000100010011, Y=$flatten\imem.\bmem.$procmux$1428_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1425_Y [29:2], B=28'0000110000000100000001000100, Y=$flatten\imem.\bmem.$procmux$1428_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1428_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1440:
      Old ports: A=$flatten\imem.\bmem.$procmux$1437_Y, B=32'11111010111101110110111011100011, Y=$flatten\imem.\bmem.$procmux$1440_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1437_Y [29:0], B=30'111010111101110110111011100011, Y=$flatten\imem.\bmem.$procmux$1440_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1440_Y [31:30] = { $flatten\imem.\bmem.$procmux$1440_Y [28] $flatten\imem.\bmem.$procmux$1440_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1431:
      Old ports: A=$flatten\imem.\bmem.$procmux$1428_Y [29:0], B=30'000010100000010010010000000011, Y=$flatten\imem.\bmem.$procmux$1431_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1428_Y [29:2], B=28'0000101000000100100100000000, Y=$flatten\imem.\bmem.$procmux$1431_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1431_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1443:
      Old ports: A=$flatten\imem.\bmem.$procmux$1440_Y, B=32'11111110100001000010011100000011, Y=$flatten\imem.\bmem.$procmux$1443_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1440_Y [29:0], B=30'111110100001000010011100000011, Y=$flatten\imem.\bmem.$procmux$1443_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1443_Y [31:30] = { $flatten\imem.\bmem.$procmux$1443_Y [28] $flatten\imem.\bmem.$procmux$1443_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1434:
      Old ports: A=$flatten\imem.\bmem.$procmux$1431_Y [29:0], B=30'000010110000010010000010000011, Y=$flatten\imem.\bmem.$procmux$1434_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1431_Y [29:2], B=28'0000101100000100100000100000, Y=$flatten\imem.\bmem.$procmux$1434_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1434_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1446:
      Old ports: A=$flatten\imem.\bmem.$procmux$1443_Y, B=2611091, Y=$flatten\imem.\bmem.$procmux$1446_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1443_Y [29:0], B=30'000000001001111101011110010011, Y=$flatten\imem.\bmem.$procmux$1446_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1446_Y [31:30] = { $flatten\imem.\bmem.$procmux$1446_Y [28] $flatten\imem.\bmem.$procmux$1446_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1437:
      Old ports: A=$flatten\imem.\bmem.$procmux$1434_Y [29:0], B=30'000000000000000000000000010011, Y=$flatten\imem.\bmem.$procmux$1437_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1434_Y [29:2], B=28'0000000000000000000000000100, Y=$flatten\imem.\bmem.$procmux$1437_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1437_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1449:
      Old ports: A=$flatten\imem.\bmem.$procmux$1446_Y, B=32'11111110000001000010011110000011, Y=$flatten\imem.\bmem.$procmux$1449_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1446_Y [29:0], B=30'111110000001000010011110000011, Y=$flatten\imem.\bmem.$procmux$1449_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1449_Y [31:30] = { $flatten\imem.\bmem.$procmux$1449_Y [28] $flatten\imem.\bmem.$procmux$1449_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1440:
      Old ports: A=$flatten\imem.\bmem.$procmux$1437_Y [29:0], B=30'111010111101110110111011100011, Y=$flatten\imem.\bmem.$procmux$1440_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1437_Y [29:2], B=28'1110101111011101101110111000, Y=$flatten\imem.\bmem.$procmux$1440_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1440_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1452:
      Old ports: A=$flatten\imem.\bmem.$procmux$1449_Y, B=32'11111110111101000010011000100011, Y=$flatten\imem.\bmem.$procmux$1452_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1449_Y [29:0], B=30'111110111101000010011000100011, Y=$flatten\imem.\bmem.$procmux$1452_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1452_Y [31:30] = { $flatten\imem.\bmem.$procmux$1452_Y [28] $flatten\imem.\bmem.$procmux$1452_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1443:
      Old ports: A=$flatten\imem.\bmem.$procmux$1440_Y [29:0], B=30'111110100001000010011100000011, Y=$flatten\imem.\bmem.$procmux$1443_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1440_Y [29:2], B=28'1111101000010000100111000000, Y=$flatten\imem.\bmem.$procmux$1443_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1443_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1455:
      Old ports: A=$flatten\imem.\bmem.$procmux$1452_Y, B=4687763, Y=$flatten\imem.\bmem.$procmux$1455_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1452_Y [29:0], B=30'000000010001111000011110010011, Y=$flatten\imem.\bmem.$procmux$1455_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1455_Y [31:30] = { $flatten\imem.\bmem.$procmux$1455_Y [28] $flatten\imem.\bmem.$procmux$1455_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1446:
      Old ports: A=$flatten\imem.\bmem.$procmux$1443_Y [29:0], B=30'000000001001111101011110010011, Y=$flatten\imem.\bmem.$procmux$1446_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1443_Y [29:2], B=28'0000000010011111010111100100, Y=$flatten\imem.\bmem.$procmux$1446_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1446_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1458:
      Old ports: A=$flatten\imem.\bmem.$procmux$1455_Y, B=32'11111110110001000010011110000011, Y=$flatten\imem.\bmem.$procmux$1458_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1455_Y [29:0], B=30'111110110001000010011110000011, Y=$flatten\imem.\bmem.$procmux$1458_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1458_Y [31:30] = { $flatten\imem.\bmem.$procmux$1458_Y [28] $flatten\imem.\bmem.$procmux$1458_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1449:
      Old ports: A=$flatten\imem.\bmem.$procmux$1446_Y [29:0], B=30'111110000001000010011110000011, Y=$flatten\imem.\bmem.$procmux$1449_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1446_Y [29:2], B=28'1111100000010000100111100000, Y=$flatten\imem.\bmem.$procmux$1449_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1449_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1461:
      Old ports: A=$flatten\imem.\bmem.$procmux$1458_Y, B=15179811, Y=$flatten\imem.\bmem.$procmux$1461_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1458_Y [29:0], B=30'000000111001111010000000100011, Y=$flatten\imem.\bmem.$procmux$1461_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1461_Y [31:30] = { $flatten\imem.\bmem.$procmux$1461_Y [28] $flatten\imem.\bmem.$procmux$1461_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1452:
      Old ports: A=$flatten\imem.\bmem.$procmux$1449_Y [29:0], B=30'111110111101000010011000100011, Y=$flatten\imem.\bmem.$procmux$1452_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1449_Y [29:2], B=28'1111101111010000100110001000, Y=$flatten\imem.\bmem.$procmux$1452_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1452_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1464:
      Old ports: A=$flatten\imem.\bmem.$procmux$1461_Y, B=32'11111101100001000010011100000011, Y=$flatten\imem.\bmem.$procmux$1464_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1461_Y [29:0], B=30'111101100001000010011100000011, Y=$flatten\imem.\bmem.$procmux$1464_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1464_Y [31:30] = { $flatten\imem.\bmem.$procmux$1464_Y [28] $flatten\imem.\bmem.$procmux$1464_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1455:
      Old ports: A=$flatten\imem.\bmem.$procmux$1452_Y [29:0], B=30'000000010001111000011110010011, Y=$flatten\imem.\bmem.$procmux$1455_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1452_Y [29:2], B=28'0000000100011110000111100100, Y=$flatten\imem.\bmem.$procmux$1455_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1455_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1467:
      Old ports: A=$flatten\imem.\bmem.$procmux$1464_Y, B=16189363, Y=$flatten\imem.\bmem.$procmux$1467_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1464_Y [29:0], B=30'000000111101110000011110110011, Y=$flatten\imem.\bmem.$procmux$1467_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1467_Y [31:30] = { $flatten\imem.\bmem.$procmux$1467_Y [28] $flatten\imem.\bmem.$procmux$1467_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1458:
      Old ports: A=$flatten\imem.\bmem.$procmux$1455_Y [29:0], B=30'111110110001000010011110000011, Y=$flatten\imem.\bmem.$procmux$1458_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1455_Y [29:2], B=28'1111101100010000100111100000, Y=$flatten\imem.\bmem.$procmux$1458_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1458_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1470:
      Old ports: A=$flatten\imem.\bmem.$procmux$1467_Y, B=32'11111101110001000010011100000011, Y=$flatten\imem.\bmem.$procmux$1470_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1467_Y [29:0], B=30'111101110001000010011100000011, Y=$flatten\imem.\bmem.$procmux$1470_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1470_Y [31:30] = { $flatten\imem.\bmem.$procmux$1470_Y [28] $flatten\imem.\bmem.$procmux$1470_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1461:
      Old ports: A=$flatten\imem.\bmem.$procmux$1458_Y [29:0], B=30'000000111001111010000000100011, Y=$flatten\imem.\bmem.$procmux$1461_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1458_Y [29:2], B=28'0000001110011110100000001000, Y=$flatten\imem.\bmem.$procmux$1461_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1461_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1473:
      Old ports: A=$flatten\imem.\bmem.$procmux$1470_Y, B=2594707, Y=$flatten\imem.\bmem.$procmux$1473_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1470_Y [29:0], B=30'000000001001111001011110010011, Y=$flatten\imem.\bmem.$procmux$1473_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1473_Y [31:30] = { $flatten\imem.\bmem.$procmux$1473_Y [28] $flatten\imem.\bmem.$procmux$1473_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1464:
      Old ports: A=$flatten\imem.\bmem.$procmux$1461_Y [29:0], B=30'111101100001000010011100000011, Y=$flatten\imem.\bmem.$procmux$1464_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1461_Y [29:2], B=28'1111011000010000100111000000, Y=$flatten\imem.\bmem.$procmux$1464_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1464_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1476:
      Old ports: A=$flatten\imem.\bmem.$procmux$1473_Y, B=32'11111110111001000010010000100011, Y=$flatten\imem.\bmem.$procmux$1476_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1473_Y [29:0], B=30'111110111001000010010000100011, Y=$flatten\imem.\bmem.$procmux$1476_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1476_Y [31:30] = { $flatten\imem.\bmem.$procmux$1476_Y [28] $flatten\imem.\bmem.$procmux$1476_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1467:
      Old ports: A=$flatten\imem.\bmem.$procmux$1464_Y [29:0], B=30'000000111101110000011110110011, Y=$flatten\imem.\bmem.$procmux$1467_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1464_Y [29:2], B=28'0000001111011100000111101100, Y=$flatten\imem.\bmem.$procmux$1467_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1467_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1479:
      Old ports: A=$flatten\imem.\bmem.$procmux$1476_Y, B=1541907, Y=$flatten\imem.\bmem.$procmux$1479_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1476_Y [29:0], B=30'000000000101111000011100010011, Y=$flatten\imem.\bmem.$procmux$1479_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1479_Y [31:30] = { $flatten\imem.\bmem.$procmux$1479_Y [28] $flatten\imem.\bmem.$procmux$1479_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1470:
      Old ports: A=$flatten\imem.\bmem.$procmux$1467_Y [29:0], B=30'111101110001000010011100000011, Y=$flatten\imem.\bmem.$procmux$1470_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1467_Y [29:2], B=28'1111011100010000100111000000, Y=$flatten\imem.\bmem.$procmux$1470_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1470_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1482:
      Old ports: A=$flatten\imem.\bmem.$procmux$1479_Y, B=32'11111110100001000010011110000011, Y=$flatten\imem.\bmem.$procmux$1482_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1479_Y [29:0], B=30'111110100001000010011110000011, Y=$flatten\imem.\bmem.$procmux$1482_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1482_Y [31:30] = { $flatten\imem.\bmem.$procmux$1482_Y [28] $flatten\imem.\bmem.$procmux$1482_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1473:
      Old ports: A=$flatten\imem.\bmem.$procmux$1470_Y [29:0], B=30'000000001001111001011110010011, Y=$flatten\imem.\bmem.$procmux$1473_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1470_Y [29:2], B=28'0000000010011110010111100100, Y=$flatten\imem.\bmem.$procmux$1473_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1473_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1485:
      Old ports: A=$flatten\imem.\bmem.$procmux$1482_Y, B=32'11111100101001000010110000100011, Y=$flatten\imem.\bmem.$procmux$1485_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1482_Y [29:0], B=30'111100101001000010110000100011, Y=$flatten\imem.\bmem.$procmux$1485_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1485_Y [31:30] = { $flatten\imem.\bmem.$procmux$1485_Y [28] $flatten\imem.\bmem.$procmux$1485_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1476:
      Old ports: A=$flatten\imem.\bmem.$procmux$1473_Y [29:0], B=30'111110111001000010010000100011, Y=$flatten\imem.\bmem.$procmux$1476_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1473_Y [29:2], B=28'1111101110010000100100001000, Y=$flatten\imem.\bmem.$procmux$1476_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1476_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1488:
      Old ports: A=$flatten\imem.\bmem.$procmux$1485_Y, B=92274927, Y=$flatten\imem.\bmem.$procmux$1488_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1485_Y [29:0], B=30'000101100000000000000011101111, Y=$flatten\imem.\bmem.$procmux$1488_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1488_Y [31:30] = { $flatten\imem.\bmem.$procmux$1488_Y [28] $flatten\imem.\bmem.$procmux$1488_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1479:
      Old ports: A=$flatten\imem.\bmem.$procmux$1476_Y [29:0], B=30'000000000101111000011100010011, Y=$flatten\imem.\bmem.$procmux$1479_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1476_Y [29:2], B=28'0000000001011110000111000100, Y=$flatten\imem.\bmem.$procmux$1479_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1479_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1491:
      Old ports: A=$flatten\imem.\bmem.$procmux$1488_Y, B=32'11111110110001000010010100000011, Y=$flatten\imem.\bmem.$procmux$1491_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1488_Y [29:0], B=30'111110110001000010010100000011, Y=$flatten\imem.\bmem.$procmux$1491_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1491_Y [31:30] = { $flatten\imem.\bmem.$procmux$1491_Y [28] $flatten\imem.\bmem.$procmux$1491_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1482:
      Old ports: A=$flatten\imem.\bmem.$procmux$1479_Y [29:0], B=30'111110100001000010011110000011, Y=$flatten\imem.\bmem.$procmux$1482_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1479_Y [29:2], B=28'1111101000010000100111100000, Y=$flatten\imem.\bmem.$procmux$1482_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1482_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1494:
      Old ports: A=$flatten\imem.\bmem.$procmux$1491_Y, B=62914671, Y=$flatten\imem.\bmem.$procmux$1494_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1491_Y [29:0], B=30'000011110000000000000001101111, Y=$flatten\imem.\bmem.$procmux$1494_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1494_Y [31:30] = { $flatten\imem.\bmem.$procmux$1494_Y [28] $flatten\imem.\bmem.$procmux$1494_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1485:
      Old ports: A=$flatten\imem.\bmem.$procmux$1482_Y [29:0], B=30'111100101001000010110000100011, Y=$flatten\imem.\bmem.$procmux$1485_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1482_Y [29:2], B=28'1111001010010000101100001000, Y=$flatten\imem.\bmem.$procmux$1485_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1485_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1497:
      Old ports: A=$flatten\imem.\bmem.$procmux$1494_Y, B=32'11111110111101000010011000100011, Y=$flatten\imem.\bmem.$procmux$1497_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1494_Y [29:0], B=30'111110111101000010011000100011, Y=$flatten\imem.\bmem.$procmux$1497_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1497_Y [31:30] = { $flatten\imem.\bmem.$procmux$1497_Y [28] $flatten\imem.\bmem.$procmux$1497_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1488:
      Old ports: A=$flatten\imem.\bmem.$procmux$1485_Y [29:0], B=30'000101100000000000000011101111, Y=$flatten\imem.\bmem.$procmux$1488_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1485_Y [29:2], B=28'0001011000000000000000111011, Y=$flatten\imem.\bmem.$procmux$1488_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1488_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1500:
      Old ports: A=$flatten\imem.\bmem.$procmux$1497_Y, B=13076371, Y=$flatten\imem.\bmem.$procmux$1500_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1497_Y [29:0], B=30'000000110001111000011110010011, Y=$flatten\imem.\bmem.$procmux$1500_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1500_Y [31:30] = { $flatten\imem.\bmem.$procmux$1500_Y [28] $flatten\imem.\bmem.$procmux$1500_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1491:
      Old ports: A=$flatten\imem.\bmem.$procmux$1488_Y [29:0], B=30'111110110001000010010100000011, Y=$flatten\imem.\bmem.$procmux$1491_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1488_Y [29:2], B=28'1111101100010000100101000000, Y=$flatten\imem.\bmem.$procmux$1491_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1491_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1503:
      Old ports: A=$flatten\imem.\bmem.$procmux$1500_Y, B=32'11111110110001000010011110000011, Y=$flatten\imem.\bmem.$procmux$1503_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1500_Y [29:0], B=30'111110110001000010011110000011, Y=$flatten\imem.\bmem.$procmux$1503_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1503_Y [31:30] = { $flatten\imem.\bmem.$procmux$1503_Y [28] $flatten\imem.\bmem.$procmux$1503_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1494:
      Old ports: A=$flatten\imem.\bmem.$procmux$1491_Y [29:0], B=30'000011110000000000000001101111, Y=$flatten\imem.\bmem.$procmux$1494_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1491_Y [29:2], B=28'0000111100000000000000011011, Y=$flatten\imem.\bmem.$procmux$1494_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1494_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1506:
      Old ports: A=$flatten\imem.\bmem.$procmux$1503_Y, B=32'11111110000001000010010000100011, Y=$flatten\imem.\bmem.$procmux$1506_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1503_Y [29:0], B=30'111110000001000010010000100011, Y=$flatten\imem.\bmem.$procmux$1506_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1506_Y [31:30] = { $flatten\imem.\bmem.$procmux$1506_Y [28] $flatten\imem.\bmem.$procmux$1506_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1497:
      Old ports: A=$flatten\imem.\bmem.$procmux$1494_Y [29:0], B=30'111110111101000010011000100011, Y=$flatten\imem.\bmem.$procmux$1497_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1494_Y [29:2], B=28'1111101111010000100110001000, Y=$flatten\imem.\bmem.$procmux$1497_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1497_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1509:
      Old ports: A=$flatten\imem.\bmem.$procmux$1506_Y, B=32'11111100000001000010110000100011, Y=$flatten\imem.\bmem.$procmux$1509_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1506_Y [29:0], B=30'111100000001000010110000100011, Y=$flatten\imem.\bmem.$procmux$1509_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1509_Y [31:30] = { $flatten\imem.\bmem.$procmux$1509_Y [28] $flatten\imem.\bmem.$procmux$1509_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1500:
      Old ports: A=$flatten\imem.\bmem.$procmux$1497_Y [29:0], B=30'000000110001111000011110010011, Y=$flatten\imem.\bmem.$procmux$1500_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1497_Y [29:2], B=28'0000001100011110000111100100, Y=$flatten\imem.\bmem.$procmux$1500_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1500_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1512:
      Old ports: A=$flatten\imem.\bmem.$procmux$1509_Y, B=32'11111100000001000010111000100011, Y=$flatten\imem.\bmem.$procmux$1512_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1509_Y [29:0], B=30'111100000001000010111000100011, Y=$flatten\imem.\bmem.$procmux$1512_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1512_Y [31:30] = { $flatten\imem.\bmem.$procmux$1512_Y [28] $flatten\imem.\bmem.$procmux$1512_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1503:
      Old ports: A=$flatten\imem.\bmem.$procmux$1500_Y [29:0], B=30'111110110001000010011110000011, Y=$flatten\imem.\bmem.$procmux$1503_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1500_Y [29:2], B=28'1111101100010000100111100000, Y=$flatten\imem.\bmem.$procmux$1503_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1503_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1515:
      Old ports: A=$flatten\imem.\bmem.$procmux$1512_Y, B=32'11111110101001000010000000100011, Y=$flatten\imem.\bmem.$procmux$1515_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1512_Y [29:0], B=30'111110101001000010000000100011, Y=$flatten\imem.\bmem.$procmux$1515_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1515_Y [31:30] = { $flatten\imem.\bmem.$procmux$1515_Y [28] $flatten\imem.\bmem.$procmux$1515_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1506:
      Old ports: A=$flatten\imem.\bmem.$procmux$1503_Y [29:0], B=30'111110000001000010010000100011, Y=$flatten\imem.\bmem.$procmux$1506_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1503_Y [29:2], B=28'1111100000010000100100001000, Y=$flatten\imem.\bmem.$procmux$1506_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1506_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1518:
      Old ports: A=$flatten\imem.\bmem.$procmux$1515_Y, B=134217967, Y=$flatten\imem.\bmem.$procmux$1518_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1515_Y [29:0], B=30'001000000000000000000011101111, Y=$flatten\imem.\bmem.$procmux$1518_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1518_Y [31:30] = { $flatten\imem.\bmem.$procmux$1518_Y [28] $flatten\imem.\bmem.$procmux$1518_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1509:
      Old ports: A=$flatten\imem.\bmem.$procmux$1506_Y [29:0], B=30'111100000001000010110000100011, Y=$flatten\imem.\bmem.$procmux$1509_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1506_Y [29:2], B=28'1111000000010000101100001000, Y=$flatten\imem.\bmem.$procmux$1509_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1509_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1521:
      Old ports: A=$flatten\imem.\bmem.$procmux$1518_Y, B=492819, Y=$flatten\imem.\bmem.$procmux$1521_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1518_Y [29:0], B=30'000000000001111000010100010011, Y=$flatten\imem.\bmem.$procmux$1521_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1521_Y [31:30] = { $flatten\imem.\bmem.$procmux$1521_Y [28] $flatten\imem.\bmem.$procmux$1521_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1512:
      Old ports: A=$flatten\imem.\bmem.$procmux$1509_Y [29:0], B=30'111100000001000010111000100011, Y=$flatten\imem.\bmem.$procmux$1512_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1509_Y [29:2], B=28'1111000000010000101110001000, Y=$flatten\imem.\bmem.$procmux$1512_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1512_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1524:
      Old ports: A=$flatten\imem.\bmem.$procmux$1521_Y, B=4687763, Y=$flatten\imem.\bmem.$procmux$1524_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1521_Y [29:0], B=30'000000010001111000011110010011, Y=$flatten\imem.\bmem.$procmux$1524_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1524_Y [31:30] = { $flatten\imem.\bmem.$procmux$1524_Y [28] $flatten\imem.\bmem.$procmux$1524_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1515:
      Old ports: A=$flatten\imem.\bmem.$procmux$1512_Y [29:0], B=30'111110101001000010000000100011, Y=$flatten\imem.\bmem.$procmux$1515_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1512_Y [29:2], B=28'1111101010010000100000001000, Y=$flatten\imem.\bmem.$procmux$1515_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1515_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1527:
      Old ports: A=$flatten\imem.\bmem.$procmux$1524_Y, B=32'11111110110001000010011110000011, Y=$flatten\imem.\bmem.$procmux$1527_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1524_Y [29:0], B=30'111110110001000010011110000011, Y=$flatten\imem.\bmem.$procmux$1527_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1527_Y [31:30] = { $flatten\imem.\bmem.$procmux$1527_Y [28] $flatten\imem.\bmem.$procmux$1527_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1518:
      Old ports: A=$flatten\imem.\bmem.$procmux$1515_Y [29:0], B=30'001000000000000000000011101111, Y=$flatten\imem.\bmem.$procmux$1518_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1515_Y [29:2], B=28'0010000000000000000000111011, Y=$flatten\imem.\bmem.$procmux$1518_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1518_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1530:
      Old ports: A=$flatten\imem.\bmem.$procmux$1527_Y, B=32'11111110101001000010001000100011, Y=$flatten\imem.\bmem.$procmux$1530_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1527_Y [29:0], B=30'111110101001000010001000100011, Y=$flatten\imem.\bmem.$procmux$1530_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1530_Y [31:30] = { $flatten\imem.\bmem.$procmux$1530_Y [28] $flatten\imem.\bmem.$procmux$1530_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1521:
      Old ports: A=$flatten\imem.\bmem.$procmux$1518_Y [29:0], B=30'000000000001111000010100010011, Y=$flatten\imem.\bmem.$procmux$1521_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1518_Y [29:2], B=28'0000000000011110000101000100, Y=$flatten\imem.\bmem.$procmux$1521_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1521_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1533:
      Old ports: A=$flatten\imem.\bmem.$procmux$1530_Y, B=155189487, Y=$flatten\imem.\bmem.$procmux$1533_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1530_Y [29:0], B=30'001001010000000000000011101111, Y=$flatten\imem.\bmem.$procmux$1533_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1533_Y [31:30] = { $flatten\imem.\bmem.$procmux$1533_Y [28] $flatten\imem.\bmem.$procmux$1533_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1524:
      Old ports: A=$flatten\imem.\bmem.$procmux$1521_Y [29:0], B=30'000000010001111000011110010011, Y=$flatten\imem.\bmem.$procmux$1524_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1521_Y [29:2], B=28'0000000100011110000111100100, Y=$flatten\imem.\bmem.$procmux$1524_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1524_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1536:
      Old ports: A=$flatten\imem.\bmem.$procmux$1533_Y, B=32'11111110110001000010010100000011, Y=$flatten\imem.\bmem.$procmux$1536_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1533_Y [29:0], B=30'111110110001000010010100000011, Y=$flatten\imem.\bmem.$procmux$1536_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1536_Y [31:30] = { $flatten\imem.\bmem.$procmux$1536_Y [28] $flatten\imem.\bmem.$procmux$1536_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1527:
      Old ports: A=$flatten\imem.\bmem.$procmux$1524_Y [29:0], B=30'111110110001000010011110000011, Y=$flatten\imem.\bmem.$procmux$1527_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1524_Y [29:2], B=28'1111101100010000100111100000, Y=$flatten\imem.\bmem.$procmux$1527_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1527_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1539:
      Old ports: A=$flatten\imem.\bmem.$procmux$1536_Y, B=32'11111110000001000010011000100011, Y=$flatten\imem.\bmem.$procmux$1539_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1536_Y [29:0], B=30'111110000001000010011000100011, Y=$flatten\imem.\bmem.$procmux$1539_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1539_Y [31:30] = { $flatten\imem.\bmem.$procmux$1539_Y [28] $flatten\imem.\bmem.$procmux$1539_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1530:
      Old ports: A=$flatten\imem.\bmem.$procmux$1527_Y [29:0], B=30'111110101001000010001000100011, Y=$flatten\imem.\bmem.$procmux$1530_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1527_Y [29:2], B=28'1111101010010000100010001000, Y=$flatten\imem.\bmem.$procmux$1530_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1530_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1542:
      Old ports: A=$flatten\imem.\bmem.$procmux$1539_Y, B=50398227, Y=$flatten\imem.\bmem.$procmux$1542_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1539_Y [29:0], B=30'000011000000010000010000010011, Y=$flatten\imem.\bmem.$procmux$1542_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1542_Y [31:30] = { $flatten\imem.\bmem.$procmux$1542_Y [28] $flatten\imem.\bmem.$procmux$1542_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1533:
      Old ports: A=$flatten\imem.\bmem.$procmux$1530_Y [29:0], B=30'001001010000000000000011101111, Y=$flatten\imem.\bmem.$procmux$1533_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1530_Y [29:2], B=28'0010010100000000000000111011, Y=$flatten\imem.\bmem.$procmux$1533_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1533_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1545:
      Old ports: A=$flatten\imem.\bmem.$procmux$1542_Y, B=42017827, Y=$flatten\imem.\bmem.$procmux$1545_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1542_Y [29:0], B=30'000010100000010010010000100011, Y=$flatten\imem.\bmem.$procmux$1545_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1545_Y [31:30] = { $flatten\imem.\bmem.$procmux$1545_Y [28] $flatten\imem.\bmem.$procmux$1545_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1536:
      Old ports: A=$flatten\imem.\bmem.$procmux$1533_Y [29:0], B=30'111110110001000010010100000011, Y=$flatten\imem.\bmem.$procmux$1536_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1533_Y [29:2], B=28'1111101100010000100101000000, Y=$flatten\imem.\bmem.$procmux$1536_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1536_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1548:
      Old ports: A=$flatten\imem.\bmem.$procmux$1545_Y, B=34678307, Y=$flatten\imem.\bmem.$procmux$1548_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1545_Y [29:0], B=30'000010000100010010011000100011, Y=$flatten\imem.\bmem.$procmux$1548_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1548_Y [31:30] = { $flatten\imem.\bmem.$procmux$1548_Y [28] $flatten\imem.\bmem.$procmux$1548_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1539:
      Old ports: A=$flatten\imem.\bmem.$procmux$1536_Y [29:0], B=30'111110000001000010011000100011, Y=$flatten\imem.\bmem.$procmux$1539_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1536_Y [29:2], B=28'1111100000010000100110001000, Y=$flatten\imem.\bmem.$procmux$1539_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1539_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1551:
      Old ports: A=$flatten\imem.\bmem.$procmux$1548_Y, B=32'11111101000000010000000100010011, Y=$flatten\imem.\bmem.$procmux$1551_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1548_Y [29:0], B=30'111101000000010000000100010011, Y=$flatten\imem.\bmem.$procmux$1551_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1551_Y [31:30] = { $flatten\imem.\bmem.$procmux$1551_Y [28] $flatten\imem.\bmem.$procmux$1551_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1542:
      Old ports: A=$flatten\imem.\bmem.$procmux$1539_Y [29:0], B=30'000011000000010000010000010011, Y=$flatten\imem.\bmem.$procmux$1542_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1539_Y [29:2], B=28'0000110000000100000100000100, Y=$flatten\imem.\bmem.$procmux$1542_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1542_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1554:
      Old ports: A=$flatten\imem.\bmem.$procmux$1551_Y, B=32871, Y=$flatten\imem.\bmem.$procmux$1554_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1551_Y [29:0], B=30'000000000000001000000001100111, Y=$flatten\imem.\bmem.$procmux$1554_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1554_Y [31:30] = { $flatten\imem.\bmem.$procmux$1554_Y [28] $flatten\imem.\bmem.$procmux$1554_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1545:
      Old ports: A=$flatten\imem.\bmem.$procmux$1542_Y [29:0], B=30'000010100000010010010000100011, Y=$flatten\imem.\bmem.$procmux$1545_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1542_Y [29:2], B=28'0000101000000100100100001000, Y=$flatten\imem.\bmem.$procmux$1545_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1545_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1557:
      Old ports: A=$flatten\imem.\bmem.$procmux$1554_Y, B=16843027, Y=$flatten\imem.\bmem.$procmux$1557_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1554_Y [29:0], B=30'000001000000010000000100010011, Y=$flatten\imem.\bmem.$procmux$1557_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1557_Y [31:30] = { $flatten\imem.\bmem.$procmux$1557_Y [28] $flatten\imem.\bmem.$procmux$1557_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1548:
      Old ports: A=$flatten\imem.\bmem.$procmux$1545_Y [29:0], B=30'000010000100010010011000100011, Y=$flatten\imem.\bmem.$procmux$1548_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1545_Y [29:2], B=28'0000100001000100100110001000, Y=$flatten\imem.\bmem.$procmux$1548_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1548_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1560:
      Old ports: A=$flatten\imem.\bmem.$procmux$1557_Y, B=12657667, Y=$flatten\imem.\bmem.$procmux$1560_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1557_Y [29:0], B=30'000000110000010010010000000011, Y=$flatten\imem.\bmem.$procmux$1560_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1560_Y [31:30] = { $flatten\imem.\bmem.$procmux$1560_Y [28] $flatten\imem.\bmem.$procmux$1560_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1551:
      Old ports: A=$flatten\imem.\bmem.$procmux$1548_Y [29:0], B=30'111101000000010000000100010011, Y=$flatten\imem.\bmem.$procmux$1551_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1548_Y [29:2], B=28'1111010000000100000001000100, Y=$flatten\imem.\bmem.$procmux$1551_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1551_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1563:
      Old ports: A=$flatten\imem.\bmem.$procmux$1560_Y, B=19, Y=$flatten\imem.\bmem.$procmux$1563_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1560_Y [29:0], B=30'000000000000000000000000010011, Y=$flatten\imem.\bmem.$procmux$1563_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1563_Y [31:30] = { $flatten\imem.\bmem.$procmux$1563_Y [28] $flatten\imem.\bmem.$procmux$1563_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1554:
      Old ports: A=$flatten\imem.\bmem.$procmux$1551_Y [29:0], B=30'000000000000001000000001100111, Y=$flatten\imem.\bmem.$procmux$1554_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1551_Y [29:2], B=28'0000000000000010000000011001, Y=$flatten\imem.\bmem.$procmux$1554_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1554_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1566:
      Old ports: A=$flatten\imem.\bmem.$procmux$1563_Y, B=163943, Y=$flatten\imem.\bmem.$procmux$1566_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1563_Y [29:0], B=30'000000000000101000000001100111, Y=$flatten\imem.\bmem.$procmux$1566_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1566_Y [31:30] = { $flatten\imem.\bmem.$procmux$1566_Y [28] $flatten\imem.\bmem.$procmux$1566_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1557:
      Old ports: A=$flatten\imem.\bmem.$procmux$1554_Y [29:0], B=30'000001000000010000000100010011, Y=$flatten\imem.\bmem.$procmux$1557_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1554_Y [29:2], B=28'0000010000000100000001000100, Y=$flatten\imem.\bmem.$procmux$1557_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1557_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1569:
      Old ports: A=$flatten\imem.\bmem.$procmux$1566_Y, B=695, Y=$flatten\imem.\bmem.$procmux$1569_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1566_Y [29:0], B=30'000000000000000000001010110111, Y=$flatten\imem.\bmem.$procmux$1569_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1569_Y [31:30] = { $flatten\imem.\bmem.$procmux$1569_Y [28] $flatten\imem.\bmem.$procmux$1569_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1560:
      Old ports: A=$flatten\imem.\bmem.$procmux$1557_Y [29:0], B=30'000000110000010010010000000011, Y=$flatten\imem.\bmem.$procmux$1560_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1557_Y [29:2], B=28'0000001100000100100100000000, Y=$flatten\imem.\bmem.$procmux$1560_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1560_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1572:
      Old ports: A=$flatten\imem.\bmem.$procmux$1569_Y, B=16843795, Y=$flatten\imem.\bmem.$procmux$1572_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1569_Y [29:0], B=30'000001000000010000010000010011, Y=$flatten\imem.\bmem.$procmux$1572_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1572_Y [31:30] = { $flatten\imem.\bmem.$procmux$1572_Y [28] $flatten\imem.\bmem.$procmux$1572_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1563:
      Old ports: A=$flatten\imem.\bmem.$procmux$1560_Y [29:0], B=30'000000000000000000000000010011, Y=$flatten\imem.\bmem.$procmux$1563_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1560_Y [29:2], B=28'0000000000000000000000000100, Y=$flatten\imem.\bmem.$procmux$1563_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1563_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1575:
      Old ports: A=$flatten\imem.\bmem.$procmux$1572_Y, B=8463907, Y=$flatten\imem.\bmem.$procmux$1575_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1572_Y [29:0], B=30'000000100000010010011000100011, Y=$flatten\imem.\bmem.$procmux$1575_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1575_Y [31:30] = { $flatten\imem.\bmem.$procmux$1575_Y [28] $flatten\imem.\bmem.$procmux$1575_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1566:
      Old ports: A=$flatten\imem.\bmem.$procmux$1563_Y [29:0], B=30'000000000000101000000001100111, Y=$flatten\imem.\bmem.$procmux$1566_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1563_Y [29:2], B=28'0000000000001010000000011001, Y=$flatten\imem.\bmem.$procmux$1566_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1566_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1578:
      Old ports: A=$flatten\imem.\bmem.$procmux$1575_Y, B=32'11111111000000010000000100010011, Y=$flatten\imem.\bmem.$procmux$1578_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1575_Y [29:0], B=30'111111000000010000000100010011, Y=$flatten\imem.\bmem.$procmux$1578_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1578_Y [31:30] = { $flatten\imem.\bmem.$procmux$1578_Y [28] $flatten\imem.\bmem.$procmux$1578_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1569:
      Old ports: A=$flatten\imem.\bmem.$procmux$1566_Y [29:0], B=30'000000000000000000001010110111, Y=$flatten\imem.\bmem.$procmux$1569_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1566_Y [29:2], B=28'0000000000000000000010101101, Y=$flatten\imem.\bmem.$procmux$1569_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1569_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1581:
      Old ports: A=$flatten\imem.\bmem.$procmux$1578_Y, B=32871, Y=$flatten\imem.\bmem.$procmux$1581_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1578_Y [29:0], B=30'000000000000001000000001100111, Y=$flatten\imem.\bmem.$procmux$1581_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1581_Y [31:30] = { $flatten\imem.\bmem.$procmux$1581_Y [28] $flatten\imem.\bmem.$procmux$1581_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1572:
      Old ports: A=$flatten\imem.\bmem.$procmux$1569_Y [29:0], B=30'000001000000010000010000010011, Y=$flatten\imem.\bmem.$procmux$1572_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1569_Y [29:2], B=28'0000010000000100000100000100, Y=$flatten\imem.\bmem.$procmux$1572_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1572_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1584:
      Old ports: A=$flatten\imem.\bmem.$procmux$1581_Y, B=16843027, Y=$flatten\imem.\bmem.$procmux$1584_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1581_Y [29:0], B=30'000001000000010000000100010011, Y=$flatten\imem.\bmem.$procmux$1584_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1584_Y [31:30] = { $flatten\imem.\bmem.$procmux$1584_Y [28] $flatten\imem.\bmem.$procmux$1584_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1575:
      Old ports: A=$flatten\imem.\bmem.$procmux$1572_Y [29:0], B=30'000000100000010010011000100011, Y=$flatten\imem.\bmem.$procmux$1575_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1572_Y [29:2], B=28'0000001000000100100110001000, Y=$flatten\imem.\bmem.$procmux$1575_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1575_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1587:
      Old ports: A=$flatten\imem.\bmem.$procmux$1584_Y, B=8463363, Y=$flatten\imem.\bmem.$procmux$1587_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1584_Y [29:0], B=30'000000100000010010010000000011, Y=$flatten\imem.\bmem.$procmux$1587_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1587_Y [31:30] = { $flatten\imem.\bmem.$procmux$1587_Y [28] $flatten\imem.\bmem.$procmux$1587_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1578:
      Old ports: A=$flatten\imem.\bmem.$procmux$1575_Y [29:0], B=30'111111000000010000000100010011, Y=$flatten\imem.\bmem.$procmux$1578_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1575_Y [29:2], B=28'1111110000000100000001000100, Y=$flatten\imem.\bmem.$procmux$1578_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1578_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1590:
      Old ports: A=$flatten\imem.\bmem.$procmux$1587_Y, B=12656771, Y=$flatten\imem.\bmem.$procmux$1590_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1587_Y [29:0], B=30'000000110000010010000010000011, Y=$flatten\imem.\bmem.$procmux$1590_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1590_Y [31:30] = { $flatten\imem.\bmem.$procmux$1590_Y [28] $flatten\imem.\bmem.$procmux$1590_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1581:
      Old ports: A=$flatten\imem.\bmem.$procmux$1578_Y [29:0], B=30'000000000000001000000001100111, Y=$flatten\imem.\bmem.$procmux$1581_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1578_Y [29:2], B=28'0000000000000010000000011001, Y=$flatten\imem.\bmem.$procmux$1581_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1581_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1593:
      Old ports: A=$flatten\imem.\bmem.$procmux$1590_Y, B=492819, Y=$flatten\imem.\bmem.$procmux$1593_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1590_Y [29:0], B=30'000000000001111000010100010011, Y=$flatten\imem.\bmem.$procmux$1593_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1593_Y [31:30] = { $flatten\imem.\bmem.$procmux$1593_Y [28] $flatten\imem.\bmem.$procmux$1593_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1584:
      Old ports: A=$flatten\imem.\bmem.$procmux$1581_Y [29:0], B=30'000001000000010000000100010011, Y=$flatten\imem.\bmem.$procmux$1584_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1581_Y [29:2], B=28'0000010000000100000001000100, Y=$flatten\imem.\bmem.$procmux$1584_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1584_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1596:
      Old ports: A=$flatten\imem.\bmem.$procmux$1593_Y, B=1939, Y=$flatten\imem.\bmem.$procmux$1596_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1593_Y [29:0], B=30'000000000000000000011110010011, Y=$flatten\imem.\bmem.$procmux$1596_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1596_Y [31:30] = { $flatten\imem.\bmem.$procmux$1596_Y [28] $flatten\imem.\bmem.$procmux$1596_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1587:
      Old ports: A=$flatten\imem.\bmem.$procmux$1584_Y [29:0], B=30'000000100000010010010000000011, Y=$flatten\imem.\bmem.$procmux$1587_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1584_Y [29:2], B=28'0000001000000100100100000000, Y=$flatten\imem.\bmem.$procmux$1587_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1587_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1599:
      Old ports: A=$flatten\imem.\bmem.$procmux$1596_Y, B=29360367, Y=$flatten\imem.\bmem.$procmux$1599_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1596_Y [29:0], B=30'000001110000000000000011101111, Y=$flatten\imem.\bmem.$procmux$1599_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1599_Y [31:30] = { $flatten\imem.\bmem.$procmux$1599_Y [28] $flatten\imem.\bmem.$procmux$1599_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1590:
      Old ports: A=$flatten\imem.\bmem.$procmux$1587_Y [29:0], B=30'000000110000010010000010000011, Y=$flatten\imem.\bmem.$procmux$1590_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1587_Y [29:2], B=28'0000001100000100100000100000, Y=$flatten\imem.\bmem.$procmux$1590_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1590_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1602:
      Old ports: A=$flatten\imem.\bmem.$procmux$1599_Y, B=32'11111000100111111111000011101111, Y=$flatten\imem.\bmem.$procmux$1602_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1599_Y [29:0], B=30'111000100111111111000011101111, Y=$flatten\imem.\bmem.$procmux$1602_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1602_Y [31:30] = { $flatten\imem.\bmem.$procmux$1602_Y [28] $flatten\imem.\bmem.$procmux$1602_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1593:
      Old ports: A=$flatten\imem.\bmem.$procmux$1590_Y [29:0], B=30'000000000001111000010100010011, Y=$flatten\imem.\bmem.$procmux$1593_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1590_Y [29:2], B=28'0000000000011110000101000100, Y=$flatten\imem.\bmem.$procmux$1593_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1593_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1605:
      Old ports: A=$flatten\imem.\bmem.$procmux$1602_Y, B=112198931, Y=$flatten\imem.\bmem.$procmux$1605_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1602_Y [29:0], B=30'000110101100000000010100010011, Y=$flatten\imem.\bmem.$procmux$1605_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1605_Y [31:30] = { $flatten\imem.\bmem.$procmux$1605_Y [28] $flatten\imem.\bmem.$procmux$1605_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1596:
      Old ports: A=$flatten\imem.\bmem.$procmux$1593_Y [29:0], B=30'000000000000000000011110010011, Y=$flatten\imem.\bmem.$procmux$1596_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1593_Y [29:2], B=28'0000000000000000000111100100, Y=$flatten\imem.\bmem.$procmux$1596_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1596_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1608:
      Old ports: A=$flatten\imem.\bmem.$procmux$1605_Y, B=32'11111001000111111111000011101111, Y=$flatten\imem.\bmem.$procmux$1608_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1605_Y [29:0], B=30'111001000111111111000011101111, Y=$flatten\imem.\bmem.$procmux$1608_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1608_Y [31:30] = { $flatten\imem.\bmem.$procmux$1608_Y [28] $flatten\imem.\bmem.$procmux$1608_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1599:
      Old ports: A=$flatten\imem.\bmem.$procmux$1596_Y [29:0], B=30'000001110000000000000011101111, Y=$flatten\imem.\bmem.$procmux$1599_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1596_Y [29:2], B=28'0000011100000000000000111011, Y=$flatten\imem.\bmem.$procmux$1599_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1599_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1611:
      Old ports: A=$flatten\imem.\bmem.$procmux$1608_Y, B=82838803, Y=$flatten\imem.\bmem.$procmux$1611_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1608_Y [29:0], B=30'000100111100000000010100010011, Y=$flatten\imem.\bmem.$procmux$1611_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1611_Y [31:30] = { $flatten\imem.\bmem.$procmux$1611_Y [28] $flatten\imem.\bmem.$procmux$1611_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1602:
      Old ports: A=$flatten\imem.\bmem.$procmux$1599_Y [29:0], B=30'111000100111111111000011101111, Y=$flatten\imem.\bmem.$procmux$1602_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1599_Y [29:2], B=28'1110001001111111110000111011, Y=$flatten\imem.\bmem.$procmux$1602_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1602_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1614:
      Old ports: A=$flatten\imem.\bmem.$procmux$1611_Y, B=88080623, Y=$flatten\imem.\bmem.$procmux$1614_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1611_Y [29:0], B=30'000101010000000000000011101111, Y=$flatten\imem.\bmem.$procmux$1614_Y [29:0]
      New connections: $flatten\imem.\bmem.$procmux$1614_Y [31:30] = { $flatten\imem.\bmem.$procmux$1614_Y [28] $flatten\imem.\bmem.$procmux$1614_Y [28] }
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1605:
      Old ports: A=$flatten\imem.\bmem.$procmux$1602_Y [29:0], B=30'000110101100000000010100010011, Y=$flatten\imem.\bmem.$procmux$1605_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1602_Y [29:2], B=28'0001101011000000000101000100, Y=$flatten\imem.\bmem.$procmux$1605_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1605_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1617:
      Old ports: A=$flatten\imem.\bmem.$procmux$1614_Y, B=32'11101101010111111111000011101111, Y=$flatten\imem.\bmem.$procmux$1617_Y
      New ports: A={ $flatten\imem.\bmem.$procmux$1614_Y [28] $flatten\imem.\bmem.$procmux$1614_Y [29:0] }, B=31'1101101010111111111000011101111, Y=$flatten\imem.\bmem.$procmux$1617_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1617_Y [31] = $flatten\imem.\bmem.$procmux$1617_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1608:
      Old ports: A=$flatten\imem.\bmem.$procmux$1605_Y [29:0], B=30'111001000111111111000011101111, Y=$flatten\imem.\bmem.$procmux$1608_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1605_Y [29:2], B=28'1110010001111111110000111011, Y=$flatten\imem.\bmem.$procmux$1608_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1608_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1620:
      Old ports: A=$flatten\imem.\bmem.$procmux$1617_Y, B=8389907, Y=$flatten\imem.\bmem.$procmux$1620_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1617_Y [30:0], B=31'0000000100000000000010100010011, Y=$flatten\imem.\bmem.$procmux$1620_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1620_Y [31] = $flatten\imem.\bmem.$procmux$1620_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1611:
      Old ports: A=$flatten\imem.\bmem.$procmux$1608_Y [29:0], B=30'000100111100000000010100010011, Y=$flatten\imem.\bmem.$procmux$1611_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1608_Y [29:2], B=28'0001001111000000000101000100, Y=$flatten\imem.\bmem.$procmux$1611_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1611_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1623:
      Old ports: A=$flatten\imem.\bmem.$procmux$1620_Y, B=32'11110111010111111111000011101111, Y=$flatten\imem.\bmem.$procmux$1623_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1620_Y [30:0], B=31'1110111010111111111000011101111, Y=$flatten\imem.\bmem.$procmux$1623_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1623_Y [31] = $flatten\imem.\bmem.$procmux$1623_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1614:
      Old ports: A=$flatten\imem.\bmem.$procmux$1611_Y [29:0], B=30'000101010000000000000011101111, Y=$flatten\imem.\bmem.$procmux$1614_Y [29:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1611_Y [29:2], B=28'0001010100000000000000111011, Y=$flatten\imem.\bmem.$procmux$1614_Y [29:2]
      New connections: $flatten\imem.\bmem.$procmux$1614_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1626:
      Old ports: A=$flatten\imem.\bmem.$procmux$1623_Y, B=16778515, Y=$flatten\imem.\bmem.$procmux$1626_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1623_Y [30:0], B=31'0000001000000000000010100010011, Y=$flatten\imem.\bmem.$procmux$1626_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1626_Y [31] = $flatten\imem.\bmem.$procmux$1626_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1617:
      Old ports: A={ $flatten\imem.\bmem.$procmux$1614_Y [28] $flatten\imem.\bmem.$procmux$1614_Y [29:0] }, B=31'1101101010111111111000011101111, Y=$flatten\imem.\bmem.$procmux$1617_Y [30:0]
      New ports: A={ $flatten\imem.\bmem.$procmux$1614_Y [28] $flatten\imem.\bmem.$procmux$1614_Y [29:2] }, B=29'11011010101111111110000111011, Y=$flatten\imem.\bmem.$procmux$1617_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1617_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1629:
      Old ports: A=$flatten\imem.\bmem.$procmux$1626_Y, B=16843795, Y=$flatten\imem.\bmem.$procmux$1629_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1626_Y [30:0], B=31'0000001000000010000010000010011, Y=$flatten\imem.\bmem.$procmux$1629_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1629_Y [31] = $flatten\imem.\bmem.$procmux$1629_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1620:
      Old ports: A=$flatten\imem.\bmem.$procmux$1617_Y [30:0], B=31'0000000100000000000010100010011, Y=$flatten\imem.\bmem.$procmux$1620_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1617_Y [30:2], B=29'00000001000000000000101000100, Y=$flatten\imem.\bmem.$procmux$1620_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1620_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1632:
      Old ports: A=$flatten\imem.\bmem.$procmux$1629_Y, B=8463395, Y=$flatten\imem.\bmem.$procmux$1632_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1629_Y [30:0], B=31'0000000100000010010010000100011, Y=$flatten\imem.\bmem.$procmux$1632_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1632_Y [31] = $flatten\imem.\bmem.$procmux$1632_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1623:
      Old ports: A=$flatten\imem.\bmem.$procmux$1620_Y [30:0], B=31'1110111010111111111000011101111, Y=$flatten\imem.\bmem.$procmux$1623_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1620_Y [30:2], B=29'11101110101111111110000111011, Y=$flatten\imem.\bmem.$procmux$1623_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1623_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1635:
      Old ports: A=$flatten\imem.\bmem.$procmux$1632_Y, B=1123875, Y=$flatten\imem.\bmem.$procmux$1635_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1632_Y [30:0], B=31'0000000000100010010011000100011, Y=$flatten\imem.\bmem.$procmux$1635_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1635_Y [31] = $flatten\imem.\bmem.$procmux$1635_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1626:
      Old ports: A=$flatten\imem.\bmem.$procmux$1623_Y [30:0], B=31'0000001000000000000010100010011, Y=$flatten\imem.\bmem.$procmux$1626_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1623_Y [30:2], B=29'00000010000000000000101000100, Y=$flatten\imem.\bmem.$procmux$1626_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1626_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1638:
      Old ports: A=$flatten\imem.\bmem.$procmux$1635_Y, B=32'11111111000000010000000100010011, Y=$flatten\imem.\bmem.$procmux$1638_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1635_Y [30:0], B=31'1111111000000010000000100010011, Y=$flatten\imem.\bmem.$procmux$1638_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1638_Y [31] = $flatten\imem.\bmem.$procmux$1638_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1629:
      Old ports: A=$flatten\imem.\bmem.$procmux$1626_Y [30:0], B=31'0000001000000010000010000010011, Y=$flatten\imem.\bmem.$procmux$1629_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1626_Y [30:2], B=29'00000010000000100000100000100, Y=$flatten\imem.\bmem.$procmux$1629_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1629_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1641:
      Old ports: A=$flatten\imem.\bmem.$procmux$1638_Y, B=32871, Y=$flatten\imem.\bmem.$procmux$1641_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1638_Y [30:0], B=31'0000000000000001000000001100111, Y=$flatten\imem.\bmem.$procmux$1641_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1641_Y [31] = $flatten\imem.\bmem.$procmux$1641_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1632:
      Old ports: A=$flatten\imem.\bmem.$procmux$1629_Y [30:0], B=31'0000000100000010010010000100011, Y=$flatten\imem.\bmem.$procmux$1632_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1629_Y [30:2], B=29'00000001000000100100100001000, Y=$flatten\imem.\bmem.$procmux$1632_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1632_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1644:
      Old ports: A=$flatten\imem.\bmem.$procmux$1641_Y, B=33620243, Y=$flatten\imem.\bmem.$procmux$1644_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1641_Y [30:0], B=31'0000010000000010000000100010011, Y=$flatten\imem.\bmem.$procmux$1644_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1644_Y [31] = $flatten\imem.\bmem.$procmux$1644_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1635:
      Old ports: A=$flatten\imem.\bmem.$procmux$1632_Y [30:0], B=31'0000000000100010010011000100011, Y=$flatten\imem.\bmem.$procmux$1635_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1632_Y [30:2], B=29'00000000001000100100110001000, Y=$flatten\imem.\bmem.$procmux$1635_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1635_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1647:
      Old ports: A=$flatten\imem.\bmem.$procmux$1644_Y, B=29434883, Y=$flatten\imem.\bmem.$procmux$1647_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1644_Y [30:0], B=31'0000001110000010010010000000011, Y=$flatten\imem.\bmem.$procmux$1647_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1647_Y [31] = $flatten\imem.\bmem.$procmux$1647_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1638:
      Old ports: A=$flatten\imem.\bmem.$procmux$1635_Y [30:0], B=31'1111111000000010000000100010011, Y=$flatten\imem.\bmem.$procmux$1638_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1635_Y [30:2], B=29'11111110000000100000001000100, Y=$flatten\imem.\bmem.$procmux$1638_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1638_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1650:
      Old ports: A=$flatten\imem.\bmem.$procmux$1647_Y, B=19, Y=$flatten\imem.\bmem.$procmux$1650_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1647_Y [30:0], B=31'0000000000000000000000000010011, Y=$flatten\imem.\bmem.$procmux$1650_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1650_Y [31] = $flatten\imem.\bmem.$procmux$1650_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1641:
      Old ports: A=$flatten\imem.\bmem.$procmux$1638_Y [30:0], B=31'0000000000000001000000001100111, Y=$flatten\imem.\bmem.$procmux$1641_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1638_Y [30:2], B=29'00000000000000010000000011001, Y=$flatten\imem.\bmem.$procmux$1641_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1641_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1653:
      Old ports: A=$flatten\imem.\bmem.$procmux$1650_Y, B=15171747, Y=$flatten\imem.\bmem.$procmux$1653_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1650_Y [30:0], B=31'0000000111001111000000010100011, Y=$flatten\imem.\bmem.$procmux$1653_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1653_Y [31] = $flatten\imem.\bmem.$procmux$1653_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1644:
      Old ports: A=$flatten\imem.\bmem.$procmux$1641_Y [30:0], B=31'0000010000000010000000100010011, Y=$flatten\imem.\bmem.$procmux$1644_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1641_Y [30:2], B=29'00000100000000100000001000100, Y=$flatten\imem.\bmem.$procmux$1644_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1644_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1656:
      Old ports: A=$flatten\imem.\bmem.$procmux$1653_Y, B=32'11111110111101000100011100000011, Y=$flatten\imem.\bmem.$procmux$1656_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1653_Y [30:0], B=31'1111110111101000100011100000011, Y=$flatten\imem.\bmem.$procmux$1656_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1656_Y [31] = $flatten\imem.\bmem.$procmux$1656_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1647:
      Old ports: A=$flatten\imem.\bmem.$procmux$1644_Y [30:0], B=31'0000001110000010010010000000011, Y=$flatten\imem.\bmem.$procmux$1647_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1644_Y [30:2], B=29'00000011100000100100100000000, Y=$flatten\imem.\bmem.$procmux$1647_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1647_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1659:
      Old ports: A=$flatten\imem.\bmem.$procmux$1656_Y, B=10167, Y=$flatten\imem.\bmem.$procmux$1659_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1656_Y [30:0], B=31'0000000000000000010011110110111, Y=$flatten\imem.\bmem.$procmux$1659_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1659_Y [31] = $flatten\imem.\bmem.$procmux$1659_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1650:
      Old ports: A=$flatten\imem.\bmem.$procmux$1647_Y [30:0], B=31'0000000000000000000000000010011, Y=$flatten\imem.\bmem.$procmux$1650_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1647_Y [30:2], B=29'00000000000000000000000000100, Y=$flatten\imem.\bmem.$procmux$1650_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1650_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1662:
      Old ports: A=$flatten\imem.\bmem.$procmux$1659_Y, B=32'11111110000001111000100011100011, Y=$flatten\imem.\bmem.$procmux$1662_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1659_Y [30:0], B=31'1111110000001111000100011100011, Y=$flatten\imem.\bmem.$procmux$1662_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1662_Y [31] = $flatten\imem.\bmem.$procmux$1662_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1653:
      Old ports: A=$flatten\imem.\bmem.$procmux$1650_Y [30:0], B=31'0000000111001111000000010100011, Y=$flatten\imem.\bmem.$procmux$1653_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1650_Y [30:2], B=29'00000001110011110000000101000, Y=$flatten\imem.\bmem.$procmux$1653_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1653_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1665:
      Old ports: A=$flatten\imem.\bmem.$procmux$1662_Y, B=2619283, Y=$flatten\imem.\bmem.$procmux$1665_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1662_Y [30:0], B=31'0000000001001111111011110010011, Y=$flatten\imem.\bmem.$procmux$1665_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1665_Y [31] = $flatten\imem.\bmem.$procmux$1665_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1656:
      Old ports: A=$flatten\imem.\bmem.$procmux$1653_Y [30:0], B=31'1111110111101000100011100000011, Y=$flatten\imem.\bmem.$procmux$1656_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1653_Y [30:2], B=29'11111101111010001000111000000, Y=$flatten\imem.\bmem.$procmux$1656_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1656_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1668:
      Old ports: A=$flatten\imem.\bmem.$procmux$1665_Y, B=267909011, Y=$flatten\imem.\bmem.$procmux$1668_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1665_Y [30:0], B=31'0001111111101111111011110010011, Y=$flatten\imem.\bmem.$procmux$1668_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1668_Y [31] = $flatten\imem.\bmem.$procmux$1668_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1659:
      Old ports: A=$flatten\imem.\bmem.$procmux$1656_Y [30:0], B=31'0000000000000000010011110110111, Y=$flatten\imem.\bmem.$procmux$1659_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1656_Y [30:2], B=29'00000000000000000100111101101, Y=$flatten\imem.\bmem.$procmux$1659_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1659_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1671:
      Old ports: A=$flatten\imem.\bmem.$procmux$1668_Y, B=4704131, Y=$flatten\imem.\bmem.$procmux$1671_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1668_Y [30:0], B=31'0000000010001111100011110000011, Y=$flatten\imem.\bmem.$procmux$1671_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1671_Y [31] = $flatten\imem.\bmem.$procmux$1671_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1662:
      Old ports: A=$flatten\imem.\bmem.$procmux$1659_Y [30:0], B=31'1111110000001111000100011100011, Y=$flatten\imem.\bmem.$procmux$1662_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1659_Y [30:2], B=29'11111100000011110001000111000, Y=$flatten\imem.\bmem.$procmux$1662_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1662_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1674:
      Old ports: A=$flatten\imem.\bmem.$procmux$1671_Y, B=10167, Y=$flatten\imem.\bmem.$procmux$1674_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1671_Y [30:0], B=31'0000000000000000010011110110111, Y=$flatten\imem.\bmem.$procmux$1674_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1674_Y [31] = $flatten\imem.\bmem.$procmux$1674_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1665:
      Old ports: A=$flatten\imem.\bmem.$procmux$1662_Y [30:0], B=31'0000000001001111111011110010011, Y=$flatten\imem.\bmem.$procmux$1665_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1662_Y [30:2], B=29'00000000010011111110111100100, Y=$flatten\imem.\bmem.$procmux$1665_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1665_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1677:
      Old ports: A=$flatten\imem.\bmem.$procmux$1674_Y, B=19, Y=$flatten\imem.\bmem.$procmux$1677_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1674_Y [30:0], B=31'0000000000000000000000000010011, Y=$flatten\imem.\bmem.$procmux$1677_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1677_Y [31] = $flatten\imem.\bmem.$procmux$1677_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1668:
      Old ports: A=$flatten\imem.\bmem.$procmux$1665_Y [30:0], B=31'0001111111101111111011110010011, Y=$flatten\imem.\bmem.$procmux$1668_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1665_Y [30:2], B=29'00011111111011111110111100100, Y=$flatten\imem.\bmem.$procmux$1668_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1668_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1680:
      Old ports: A=$flatten\imem.\bmem.$procmux$1677_Y, B=32'11111110111101000000011110100011, Y=$flatten\imem.\bmem.$procmux$1680_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1677_Y [30:0], B=31'1111110111101000000011110100011, Y=$flatten\imem.\bmem.$procmux$1680_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1680_Y [31] = $flatten\imem.\bmem.$procmux$1680_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1671:
      Old ports: A=$flatten\imem.\bmem.$procmux$1668_Y [30:0], B=31'0000000010001111100011110000011, Y=$flatten\imem.\bmem.$procmux$1671_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1668_Y [30:2], B=29'00000000100011111000111100000, Y=$flatten\imem.\bmem.$procmux$1671_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1671_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1683:
      Old ports: A=$flatten\imem.\bmem.$procmux$1680_Y, B=329619, Y=$flatten\imem.\bmem.$procmux$1683_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1680_Y [30:0], B=31'0000000000001010000011110010011, Y=$flatten\imem.\bmem.$procmux$1683_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1683_Y [31] = $flatten\imem.\bmem.$procmux$1683_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1674:
      Old ports: A=$flatten\imem.\bmem.$procmux$1671_Y [30:0], B=31'0000000000000000010011110110111, Y=$flatten\imem.\bmem.$procmux$1674_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1671_Y [30:2], B=29'00000000000000000100111101101, Y=$flatten\imem.\bmem.$procmux$1674_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1674_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1686:
      Old ports: A=$flatten\imem.\bmem.$procmux$1683_Y, B=33621011, Y=$flatten\imem.\bmem.$procmux$1686_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1683_Y [30:0], B=31'0000010000000010000010000010011, Y=$flatten\imem.\bmem.$procmux$1686_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1686_Y [31] = $flatten\imem.\bmem.$procmux$1686_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1677:
      Old ports: A=$flatten\imem.\bmem.$procmux$1674_Y [30:0], B=31'0000000000000000000000000010011, Y=$flatten\imem.\bmem.$procmux$1677_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1674_Y [30:2], B=29'00000000000000000000000000100, Y=$flatten\imem.\bmem.$procmux$1677_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1677_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1689:
      Old ports: A=$flatten\imem.\bmem.$procmux$1686_Y, B=8465955, Y=$flatten\imem.\bmem.$procmux$1689_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1686_Y [30:0], B=31'0000000100000010010111000100011, Y=$flatten\imem.\bmem.$procmux$1689_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1689_Y [31] = $flatten\imem.\bmem.$procmux$1689_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1680:
      Old ports: A=$flatten\imem.\bmem.$procmux$1677_Y [30:0], B=31'1111110111101000000011110100011, Y=$flatten\imem.\bmem.$procmux$1680_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1677_Y [30:2], B=29'11111101111010000000111101000, Y=$flatten\imem.\bmem.$procmux$1680_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1680_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1692:
      Old ports: A=$flatten\imem.\bmem.$procmux$1689_Y, B=32'11111110000000010000000100010011, Y=$flatten\imem.\bmem.$procmux$1692_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1689_Y [30:0], B=31'1111110000000010000000100010011, Y=$flatten\imem.\bmem.$procmux$1692_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1692_Y [31] = $flatten\imem.\bmem.$procmux$1692_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1683:
      Old ports: A=$flatten\imem.\bmem.$procmux$1680_Y [30:0], B=31'0000000000001010000011110010011, Y=$flatten\imem.\bmem.$procmux$1683_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1680_Y [30:2], B=29'00000000000010100000111100100, Y=$flatten\imem.\bmem.$procmux$1683_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1683_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1695:
      Old ports: A=$flatten\imem.\bmem.$procmux$1692_Y, B=32871, Y=$flatten\imem.\bmem.$procmux$1695_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1692_Y [30:0], B=31'0000000000000001000000001100111, Y=$flatten\imem.\bmem.$procmux$1695_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1695_Y [31] = $flatten\imem.\bmem.$procmux$1695_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1686:
      Old ports: A=$flatten\imem.\bmem.$procmux$1683_Y [30:0], B=31'0000010000000010000010000010011, Y=$flatten\imem.\bmem.$procmux$1686_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1683_Y [30:2], B=29'00000100000000100000100000100, Y=$flatten\imem.\bmem.$procmux$1686_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1686_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1698:
      Old ports: A=$flatten\imem.\bmem.$procmux$1695_Y, B=33620243, Y=$flatten\imem.\bmem.$procmux$1698_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1695_Y [30:0], B=31'0000010000000010000000100010011, Y=$flatten\imem.\bmem.$procmux$1698_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1698_Y [31] = $flatten\imem.\bmem.$procmux$1698_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1689:
      Old ports: A=$flatten\imem.\bmem.$procmux$1686_Y [30:0], B=31'0000000100000010010111000100011, Y=$flatten\imem.\bmem.$procmux$1689_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1686_Y [30:2], B=29'00000001000000100101110001000, Y=$flatten\imem.\bmem.$procmux$1689_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1689_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1701:
      Old ports: A=$flatten\imem.\bmem.$procmux$1698_Y, B=29434883, Y=$flatten\imem.\bmem.$procmux$1701_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1698_Y [30:0], B=31'0000001110000010010010000000011, Y=$flatten\imem.\bmem.$procmux$1701_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1701_Y [31] = $flatten\imem.\bmem.$procmux$1701_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1692:
      Old ports: A=$flatten\imem.\bmem.$procmux$1689_Y [30:0], B=31'1111110000000010000000100010011, Y=$flatten\imem.\bmem.$procmux$1692_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1689_Y [30:2], B=29'11111100000000100000001000100, Y=$flatten\imem.\bmem.$procmux$1692_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1692_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1704:
      Old ports: A=$flatten\imem.\bmem.$procmux$1701_Y, B=19, Y=$flatten\imem.\bmem.$procmux$1704_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1701_Y [30:0], B=31'0000000000000000000000000010011, Y=$flatten\imem.\bmem.$procmux$1704_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1704_Y [31] = $flatten\imem.\bmem.$procmux$1704_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1695:
      Old ports: A=$flatten\imem.\bmem.$procmux$1692_Y [30:0], B=31'0000000000000001000000001100111, Y=$flatten\imem.\bmem.$procmux$1695_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1692_Y [30:2], B=29'00000000000000010000000011001, Y=$flatten\imem.\bmem.$procmux$1695_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1695_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1707:
      Old ports: A=$flatten\imem.\bmem.$procmux$1704_Y, B=15171875, Y=$flatten\imem.\bmem.$procmux$1707_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1704_Y [30:0], B=31'0000000111001111000000100100011, Y=$flatten\imem.\bmem.$procmux$1707_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1707_Y [31] = $flatten\imem.\bmem.$procmux$1707_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1698:
      Old ports: A=$flatten\imem.\bmem.$procmux$1695_Y [30:0], B=31'0000010000000010000000100010011, Y=$flatten\imem.\bmem.$procmux$1698_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1695_Y [30:2], B=29'00000100000000100000001000100, Y=$flatten\imem.\bmem.$procmux$1698_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1698_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1710:
      Old ports: A=$flatten\imem.\bmem.$procmux$1707_Y, B=32'11111110111101000100011100000011, Y=$flatten\imem.\bmem.$procmux$1710_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1707_Y [30:0], B=31'1111110111101000100011100000011, Y=$flatten\imem.\bmem.$procmux$1710_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1710_Y [31] = $flatten\imem.\bmem.$procmux$1710_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1701:
      Old ports: A=$flatten\imem.\bmem.$procmux$1698_Y [30:0], B=31'0000001110000010010010000000011, Y=$flatten\imem.\bmem.$procmux$1701_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1698_Y [30:2], B=29'00000011100000100100100000000, Y=$flatten\imem.\bmem.$procmux$1701_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1701_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1713:
      Old ports: A=$flatten\imem.\bmem.$procmux$1710_Y, B=10167, Y=$flatten\imem.\bmem.$procmux$1713_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1710_Y [30:0], B=31'0000000000000000010011110110111, Y=$flatten\imem.\bmem.$procmux$1713_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1713_Y [31] = $flatten\imem.\bmem.$procmux$1713_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1704:
      Old ports: A=$flatten\imem.\bmem.$procmux$1701_Y [30:0], B=31'0000000000000000000000000010011, Y=$flatten\imem.\bmem.$procmux$1704_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1701_Y [30:2], B=29'00000000000000000000000000100, Y=$flatten\imem.\bmem.$procmux$1704_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1704_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1716:
      Old ports: A=$flatten\imem.\bmem.$procmux$1713_Y, B=32'11111110111101000000011110100011, Y=$flatten\imem.\bmem.$procmux$1716_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1713_Y [30:0], B=31'1111110111101000000011110100011, Y=$flatten\imem.\bmem.$procmux$1716_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1716_Y [31] = $flatten\imem.\bmem.$procmux$1716_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1707:
      Old ports: A=$flatten\imem.\bmem.$procmux$1704_Y [30:0], B=31'0000000111001111000000100100011, Y=$flatten\imem.\bmem.$procmux$1707_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1704_Y [30:2], B=29'00000001110011110000001001000, Y=$flatten\imem.\bmem.$procmux$1707_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1707_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1719:
      Old ports: A=$flatten\imem.\bmem.$procmux$1716_Y, B=329619, Y=$flatten\imem.\bmem.$procmux$1719_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1716_Y [30:0], B=31'0000000000001010000011110010011, Y=$flatten\imem.\bmem.$procmux$1719_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1719_Y [31] = $flatten\imem.\bmem.$procmux$1719_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1710:
      Old ports: A=$flatten\imem.\bmem.$procmux$1707_Y [30:0], B=31'1111110111101000100011100000011, Y=$flatten\imem.\bmem.$procmux$1710_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1707_Y [30:2], B=29'11111101111010001000111000000, Y=$flatten\imem.\bmem.$procmux$1710_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1710_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1722:
      Old ports: A=$flatten\imem.\bmem.$procmux$1719_Y, B=33621011, Y=$flatten\imem.\bmem.$procmux$1722_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1719_Y [30:0], B=31'0000010000000010000010000010011, Y=$flatten\imem.\bmem.$procmux$1722_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1722_Y [31] = $flatten\imem.\bmem.$procmux$1722_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1713:
      Old ports: A=$flatten\imem.\bmem.$procmux$1710_Y [30:0], B=31'0000000000000000010011110110111, Y=$flatten\imem.\bmem.$procmux$1713_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1710_Y [30:2], B=29'00000000000000000100111101101, Y=$flatten\imem.\bmem.$procmux$1713_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1713_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1725:
      Old ports: A=$flatten\imem.\bmem.$procmux$1722_Y, B=8465955, Y=$flatten\imem.\bmem.$procmux$1725_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1722_Y [30:0], B=31'0000000100000010010111000100011, Y=$flatten\imem.\bmem.$procmux$1725_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1725_Y [31] = $flatten\imem.\bmem.$procmux$1725_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1716:
      Old ports: A=$flatten\imem.\bmem.$procmux$1713_Y [30:0], B=31'1111110111101000000011110100011, Y=$flatten\imem.\bmem.$procmux$1716_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1713_Y [30:2], B=29'11111101111010000000111101000, Y=$flatten\imem.\bmem.$procmux$1716_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1716_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1728:
      Old ports: A=$flatten\imem.\bmem.$procmux$1725_Y, B=32'11111110000000010000000100010011, Y=$flatten\imem.\bmem.$procmux$1728_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1725_Y [30:0], B=31'1111110000000010000000100010011, Y=$flatten\imem.\bmem.$procmux$1728_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1728_Y [31] = $flatten\imem.\bmem.$procmux$1728_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1719:
      Old ports: A=$flatten\imem.\bmem.$procmux$1716_Y [30:0], B=31'0000000000001010000011110010011, Y=$flatten\imem.\bmem.$procmux$1719_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1716_Y [30:2], B=29'00000000000010100000111100100, Y=$flatten\imem.\bmem.$procmux$1719_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1719_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1731:
      Old ports: A=$flatten\imem.\bmem.$procmux$1728_Y, B=32871, Y=$flatten\imem.\bmem.$procmux$1731_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1728_Y [30:0], B=31'0000000000000001000000001100111, Y=$flatten\imem.\bmem.$procmux$1731_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1731_Y [31] = $flatten\imem.\bmem.$procmux$1731_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1722:
      Old ports: A=$flatten\imem.\bmem.$procmux$1719_Y [30:0], B=31'0000010000000010000010000010011, Y=$flatten\imem.\bmem.$procmux$1722_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1719_Y [30:2], B=29'00000100000000100000100000100, Y=$flatten\imem.\bmem.$procmux$1722_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1722_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1734:
      Old ports: A=$flatten\imem.\bmem.$procmux$1731_Y, B=33620243, Y=$flatten\imem.\bmem.$procmux$1734_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1731_Y [30:0], B=31'0000010000000010000000100010011, Y=$flatten\imem.\bmem.$procmux$1734_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1734_Y [31] = $flatten\imem.\bmem.$procmux$1734_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1725:
      Old ports: A=$flatten\imem.\bmem.$procmux$1722_Y [30:0], B=31'0000000100000010010111000100011, Y=$flatten\imem.\bmem.$procmux$1725_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1722_Y [30:2], B=29'00000001000000100101110001000, Y=$flatten\imem.\bmem.$procmux$1725_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1725_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1737:
      Old ports: A=$flatten\imem.\bmem.$procmux$1734_Y, B=29434883, Y=$flatten\imem.\bmem.$procmux$1737_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1734_Y [30:0], B=31'0000001110000010010010000000011, Y=$flatten\imem.\bmem.$procmux$1737_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1737_Y [31] = $flatten\imem.\bmem.$procmux$1737_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1728:
      Old ports: A=$flatten\imem.\bmem.$procmux$1725_Y [30:0], B=31'1111110000000010000000100010011, Y=$flatten\imem.\bmem.$procmux$1728_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1725_Y [30:2], B=29'11111100000000100000001000100, Y=$flatten\imem.\bmem.$procmux$1728_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1728_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1740:
      Old ports: A=$flatten\imem.\bmem.$procmux$1737_Y, B=492819, Y=$flatten\imem.\bmem.$procmux$1740_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1737_Y [30:0], B=31'0000000000001111000010100010011, Y=$flatten\imem.\bmem.$procmux$1740_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1740_Y [31] = $flatten\imem.\bmem.$procmux$1740_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1731:
      Old ports: A=$flatten\imem.\bmem.$procmux$1728_Y [30:0], B=31'0000000000000001000000001100111, Y=$flatten\imem.\bmem.$procmux$1731_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1728_Y [30:2], B=29'00000000000000010000000011001, Y=$flatten\imem.\bmem.$procmux$1731_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1731_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1743:
      Old ports: A=$flatten\imem.\bmem.$procmux$1740_Y, B=267909011, Y=$flatten\imem.\bmem.$procmux$1743_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1740_Y [30:0], B=31'0001111111101111111011110010011, Y=$flatten\imem.\bmem.$procmux$1743_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1743_Y [31] = $flatten\imem.\bmem.$procmux$1743_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1734:
      Old ports: A=$flatten\imem.\bmem.$procmux$1731_Y [30:0], B=31'0000010000000010000000100010011, Y=$flatten\imem.\bmem.$procmux$1734_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1731_Y [30:2], B=29'00000100000000100000001000100, Y=$flatten\imem.\bmem.$procmux$1734_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1734_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1746:
      Old ports: A=$flatten\imem.\bmem.$procmux$1743_Y, B=509827, Y=$flatten\imem.\bmem.$procmux$1746_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1743_Y [30:0], B=31'0000000000001111100011110000011, Y=$flatten\imem.\bmem.$procmux$1746_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1746_Y [31] = $flatten\imem.\bmem.$procmux$1746_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1737:
      Old ports: A=$flatten\imem.\bmem.$procmux$1734_Y [30:0], B=31'0000001110000010010010000000011, Y=$flatten\imem.\bmem.$procmux$1737_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1734_Y [30:2], B=29'00000011100000100100100000000, Y=$flatten\imem.\bmem.$procmux$1737_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1737_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1749:
      Old ports: A=$flatten\imem.\bmem.$procmux$1746_Y, B=14263, Y=$flatten\imem.\bmem.$procmux$1749_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1746_Y [30:0], B=31'0000000000000000011011110110111, Y=$flatten\imem.\bmem.$procmux$1749_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1749_Y [31] = $flatten\imem.\bmem.$procmux$1749_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1740:
      Old ports: A=$flatten\imem.\bmem.$procmux$1737_Y [30:0], B=31'0000000000001111000010100010011, Y=$flatten\imem.\bmem.$procmux$1740_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1737_Y [30:2], B=29'00000000000011110000101000100, Y=$flatten\imem.\bmem.$procmux$1740_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1740_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1752:
      Old ports: A=$flatten\imem.\bmem.$procmux$1749_Y, B=32'11111110000001111000100011100011, Y=$flatten\imem.\bmem.$procmux$1752_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1749_Y [30:0], B=31'1111110000001111000100011100011, Y=$flatten\imem.\bmem.$procmux$1752_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1752_Y [31] = $flatten\imem.\bmem.$procmux$1752_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1743:
      Old ports: A=$flatten\imem.\bmem.$procmux$1740_Y [30:0], B=31'0001111111101111111011110010011, Y=$flatten\imem.\bmem.$procmux$1743_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1740_Y [30:2], B=29'00011111111011111110111100100, Y=$flatten\imem.\bmem.$procmux$1743_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1743_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1755:
      Old ports: A=$flatten\imem.\bmem.$procmux$1752_Y, B=17299347, Y=$flatten\imem.\bmem.$procmux$1755_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1752_Y [30:0], B=31'0000001000001111111011110010011, Y=$flatten\imem.\bmem.$procmux$1755_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1755_Y [31] = $flatten\imem.\bmem.$procmux$1755_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1746:
      Old ports: A=$flatten\imem.\bmem.$procmux$1743_Y [30:0], B=31'0000000000001111100011110000011, Y=$flatten\imem.\bmem.$procmux$1746_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1743_Y [30:2], B=29'00000000000011111000111100000, Y=$flatten\imem.\bmem.$procmux$1746_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1746_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1758:
      Old ports: A=$flatten\imem.\bmem.$procmux$1755_Y, B=267909011, Y=$flatten\imem.\bmem.$procmux$1758_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1755_Y [30:0], B=31'0001111111101111111011110010011, Y=$flatten\imem.\bmem.$procmux$1758_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1758_Y [31] = $flatten\imem.\bmem.$procmux$1758_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1749:
      Old ports: A=$flatten\imem.\bmem.$procmux$1746_Y [30:0], B=31'0000000000000000011011110110111, Y=$flatten\imem.\bmem.$procmux$1749_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1746_Y [30:2], B=29'00000000000000000110111101101, Y=$flatten\imem.\bmem.$procmux$1749_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1749_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1761:
      Old ports: A=$flatten\imem.\bmem.$procmux$1758_Y, B=4704131, Y=$flatten\imem.\bmem.$procmux$1761_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1758_Y [30:0], B=31'0000000010001111100011110000011, Y=$flatten\imem.\bmem.$procmux$1761_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1761_Y [31] = $flatten\imem.\bmem.$procmux$1761_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1752:
      Old ports: A=$flatten\imem.\bmem.$procmux$1749_Y [30:0], B=31'1111110000001111000100011100011, Y=$flatten\imem.\bmem.$procmux$1752_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1749_Y [30:2], B=29'11111100000011110001000111000, Y=$flatten\imem.\bmem.$procmux$1752_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1752_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1764:
      Old ports: A=$flatten\imem.\bmem.$procmux$1761_Y, B=14263, Y=$flatten\imem.\bmem.$procmux$1764_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1761_Y [30:0], B=31'0000000000000000011011110110111, Y=$flatten\imem.\bmem.$procmux$1764_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1764_Y [31] = $flatten\imem.\bmem.$procmux$1764_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1755:
      Old ports: A=$flatten\imem.\bmem.$procmux$1752_Y [30:0], B=31'0000001000001111111011110010011, Y=$flatten\imem.\bmem.$procmux$1755_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1752_Y [30:2], B=29'00000010000011111110111100100, Y=$flatten\imem.\bmem.$procmux$1755_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1755_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1767:
      Old ports: A=$flatten\imem.\bmem.$procmux$1764_Y, B=19, Y=$flatten\imem.\bmem.$procmux$1767_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1764_Y [30:0], B=31'0000000000000000000000000010011, Y=$flatten\imem.\bmem.$procmux$1767_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1767_Y [31] = $flatten\imem.\bmem.$procmux$1767_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1758:
      Old ports: A=$flatten\imem.\bmem.$procmux$1755_Y [30:0], B=31'0001111111101111111011110010011, Y=$flatten\imem.\bmem.$procmux$1758_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1755_Y [30:2], B=29'00011111111011111110111100100, Y=$flatten\imem.\bmem.$procmux$1758_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1758_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1770:
      Old ports: A=$flatten\imem.\bmem.$procmux$1767_Y, B=15171747, Y=$flatten\imem.\bmem.$procmux$1770_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1767_Y [30:0], B=31'0000000111001111000000010100011, Y=$flatten\imem.\bmem.$procmux$1770_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1770_Y [31] = $flatten\imem.\bmem.$procmux$1770_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1761:
      Old ports: A=$flatten\imem.\bmem.$procmux$1758_Y [30:0], B=31'0000000010001111100011110000011, Y=$flatten\imem.\bmem.$procmux$1761_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1758_Y [30:2], B=29'00000000100011111000111100000, Y=$flatten\imem.\bmem.$procmux$1761_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1761_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1773:
      Old ports: A=$flatten\imem.\bmem.$procmux$1770_Y, B=32'11111110111101000100011100000011, Y=$flatten\imem.\bmem.$procmux$1773_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1770_Y [30:0], B=31'1111110111101000100011100000011, Y=$flatten\imem.\bmem.$procmux$1773_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1773_Y [31] = $flatten\imem.\bmem.$procmux$1773_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1764:
      Old ports: A=$flatten\imem.\bmem.$procmux$1761_Y [30:0], B=31'0000000000000000011011110110111, Y=$flatten\imem.\bmem.$procmux$1764_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1761_Y [30:2], B=29'00000000000000000110111101101, Y=$flatten\imem.\bmem.$procmux$1764_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1764_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1776:
      Old ports: A=$flatten\imem.\bmem.$procmux$1773_Y, B=14263, Y=$flatten\imem.\bmem.$procmux$1776_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1773_Y [30:0], B=31'0000000000000000011011110110111, Y=$flatten\imem.\bmem.$procmux$1776_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1776_Y [31] = $flatten\imem.\bmem.$procmux$1776_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1767:
      Old ports: A=$flatten\imem.\bmem.$procmux$1764_Y [30:0], B=31'0000000000000000000000000010011, Y=$flatten\imem.\bmem.$procmux$1767_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1764_Y [30:2], B=29'00000000000000000000000000100, Y=$flatten\imem.\bmem.$procmux$1767_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1767_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1779:
      Old ports: A=$flatten\imem.\bmem.$procmux$1776_Y, B=32'11111110111101000000011110100011, Y=$flatten\imem.\bmem.$procmux$1779_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1776_Y [30:0], B=31'1111110111101000000011110100011, Y=$flatten\imem.\bmem.$procmux$1779_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1779_Y [31] = $flatten\imem.\bmem.$procmux$1779_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1770:
      Old ports: A=$flatten\imem.\bmem.$procmux$1767_Y [30:0], B=31'0000000111001111000000010100011, Y=$flatten\imem.\bmem.$procmux$1770_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1767_Y [30:2], B=29'00000001110011110000000101000, Y=$flatten\imem.\bmem.$procmux$1770_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1770_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1782:
      Old ports: A=$flatten\imem.\bmem.$procmux$1779_Y, B=329619, Y=$flatten\imem.\bmem.$procmux$1782_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1779_Y [30:0], B=31'0000000000001010000011110010011, Y=$flatten\imem.\bmem.$procmux$1782_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1782_Y [31] = $flatten\imem.\bmem.$procmux$1782_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1773:
      Old ports: A=$flatten\imem.\bmem.$procmux$1770_Y [30:0], B=31'1111110111101000100011100000011, Y=$flatten\imem.\bmem.$procmux$1773_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1770_Y [30:2], B=29'11111101111010001000111000000, Y=$flatten\imem.\bmem.$procmux$1773_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1773_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1785:
      Old ports: A=$flatten\imem.\bmem.$procmux$1782_Y, B=33621011, Y=$flatten\imem.\bmem.$procmux$1785_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1782_Y [30:0], B=31'0000010000000010000010000010011, Y=$flatten\imem.\bmem.$procmux$1785_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1785_Y [31] = $flatten\imem.\bmem.$procmux$1785_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1776:
      Old ports: A=$flatten\imem.\bmem.$procmux$1773_Y [30:0], B=31'0000000000000000011011110110111, Y=$flatten\imem.\bmem.$procmux$1776_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1773_Y [30:2], B=29'00000000000000000110111101101, Y=$flatten\imem.\bmem.$procmux$1776_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1776_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1788:
      Old ports: A=$flatten\imem.\bmem.$procmux$1785_Y, B=8465955, Y=$flatten\imem.\bmem.$procmux$1788_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1785_Y [30:0], B=31'0000000100000010010111000100011, Y=$flatten\imem.\bmem.$procmux$1788_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1788_Y [31] = $flatten\imem.\bmem.$procmux$1788_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1779:
      Old ports: A=$flatten\imem.\bmem.$procmux$1776_Y [30:0], B=31'1111110111101000000011110100011, Y=$flatten\imem.\bmem.$procmux$1779_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1776_Y [30:2], B=29'11111101111010000000111101000, Y=$flatten\imem.\bmem.$procmux$1779_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1779_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1791:
      Old ports: A=$flatten\imem.\bmem.$procmux$1788_Y, B=32'11111110000000010000000100010011, Y=$flatten\imem.\bmem.$procmux$1791_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1788_Y [30:0], B=31'1111110000000010000000100010011, Y=$flatten\imem.\bmem.$procmux$1791_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1791_Y [31] = $flatten\imem.\bmem.$procmux$1791_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1782:
      Old ports: A=$flatten\imem.\bmem.$procmux$1779_Y [30:0], B=31'0000000000001010000011110010011, Y=$flatten\imem.\bmem.$procmux$1782_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1779_Y [30:2], B=29'00000000000010100000111100100, Y=$flatten\imem.\bmem.$procmux$1782_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1782_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1794:
      Old ports: A=$flatten\imem.\bmem.$procmux$1791_Y, B=32871, Y=$flatten\imem.\bmem.$procmux$1794_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1791_Y [30:0], B=31'0000000000000001000000001100111, Y=$flatten\imem.\bmem.$procmux$1794_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1794_Y [31] = $flatten\imem.\bmem.$procmux$1794_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1785:
      Old ports: A=$flatten\imem.\bmem.$procmux$1782_Y [30:0], B=31'0000010000000010000010000010011, Y=$flatten\imem.\bmem.$procmux$1785_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1782_Y [30:2], B=29'00000100000000100000100000100, Y=$flatten\imem.\bmem.$procmux$1785_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1785_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1797:
      Old ports: A=$flatten\imem.\bmem.$procmux$1794_Y, B=33620243, Y=$flatten\imem.\bmem.$procmux$1797_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1794_Y [30:0], B=31'0000010000000010000000100010011, Y=$flatten\imem.\bmem.$procmux$1797_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1797_Y [31] = $flatten\imem.\bmem.$procmux$1797_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1788:
      Old ports: A=$flatten\imem.\bmem.$procmux$1785_Y [30:0], B=31'0000000100000010010111000100011, Y=$flatten\imem.\bmem.$procmux$1788_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1785_Y [30:2], B=29'00000001000000100101110001000, Y=$flatten\imem.\bmem.$procmux$1788_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1788_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1800:
      Old ports: A=$flatten\imem.\bmem.$procmux$1797_Y, B=29434883, Y=$flatten\imem.\bmem.$procmux$1800_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1797_Y [30:0], B=31'0000001110000010010010000000011, Y=$flatten\imem.\bmem.$procmux$1800_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1800_Y [31] = $flatten\imem.\bmem.$procmux$1800_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1791:
      Old ports: A=$flatten\imem.\bmem.$procmux$1788_Y [30:0], B=31'1111110000000010000000100010011, Y=$flatten\imem.\bmem.$procmux$1791_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1788_Y [30:2], B=29'11111100000000100000001000100, Y=$flatten\imem.\bmem.$procmux$1791_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1791_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1803:
      Old ports: A=$flatten\imem.\bmem.$procmux$1800_Y, B=19, Y=$flatten\imem.\bmem.$procmux$1803_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1800_Y [30:0], B=31'0000000000000000000000000010011, Y=$flatten\imem.\bmem.$procmux$1803_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1803_Y [31] = $flatten\imem.\bmem.$procmux$1803_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1794:
      Old ports: A=$flatten\imem.\bmem.$procmux$1791_Y [30:0], B=31'0000000000000001000000001100111, Y=$flatten\imem.\bmem.$procmux$1794_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1791_Y [30:2], B=29'00000000000000010000000011001, Y=$flatten\imem.\bmem.$procmux$1794_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1794_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1806:
      Old ports: A=$flatten\imem.\bmem.$procmux$1803_Y, B=15171875, Y=$flatten\imem.\bmem.$procmux$1806_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1803_Y [30:0], B=31'0000000111001111000000100100011, Y=$flatten\imem.\bmem.$procmux$1806_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1806_Y [31] = $flatten\imem.\bmem.$procmux$1806_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1797:
      Old ports: A=$flatten\imem.\bmem.$procmux$1794_Y [30:0], B=31'0000010000000010000000100010011, Y=$flatten\imem.\bmem.$procmux$1797_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1794_Y [30:2], B=29'00000100000000100000001000100, Y=$flatten\imem.\bmem.$procmux$1797_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1797_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1809:
      Old ports: A=$flatten\imem.\bmem.$procmux$1806_Y, B=267876115, Y=$flatten\imem.\bmem.$procmux$1809_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1806_Y [30:0], B=31'0001111111101110111011100010011, Y=$flatten\imem.\bmem.$procmux$1809_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1809_Y [31] = $flatten\imem.\bmem.$procmux$1809_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1800:
      Old ports: A=$flatten\imem.\bmem.$procmux$1797_Y [30:0], B=31'0000001110000010010010000000011, Y=$flatten\imem.\bmem.$procmux$1800_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1797_Y [30:2], B=29'00000011100000100100100000000, Y=$flatten\imem.\bmem.$procmux$1800_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1800_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1812:
      Old ports: A=$flatten\imem.\bmem.$procmux$1809_Y, B=15132467, Y=$flatten\imem.\bmem.$procmux$1812_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1809_Y [30:0], B=31'0000000111001101110011100110011, Y=$flatten\imem.\bmem.$procmux$1812_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1812_Y [31] = $flatten\imem.\bmem.$procmux$1812_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1803:
      Old ports: A=$flatten\imem.\bmem.$procmux$1800_Y [30:0], B=31'0000000000000000000000000010011, Y=$flatten\imem.\bmem.$procmux$1803_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1800_Y [30:2], B=29'00000000000000000000000000100, Y=$flatten\imem.\bmem.$procmux$1803_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1803_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1815:
      Old ports: A=$flatten\imem.\bmem.$procmux$1812_Y, B=32'11111110111101000100011100000011, Y=$flatten\imem.\bmem.$procmux$1815_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1812_Y [30:0], B=31'1111110111101000100011100000011, Y=$flatten\imem.\bmem.$procmux$1815_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1815_Y [31] = $flatten\imem.\bmem.$procmux$1815_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1806:
      Old ports: A=$flatten\imem.\bmem.$procmux$1803_Y [30:0], B=31'0000000111001111000000100100011, Y=$flatten\imem.\bmem.$procmux$1806_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1803_Y [30:2], B=29'00000001110011110000001001000, Y=$flatten\imem.\bmem.$procmux$1806_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1806_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1818:
      Old ports: A=$flatten\imem.\bmem.$procmux$1815_Y, B=14263, Y=$flatten\imem.\bmem.$procmux$1818_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1815_Y [30:0], B=31'0000000000000000011011110110111, Y=$flatten\imem.\bmem.$procmux$1818_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1818_Y [31] = $flatten\imem.\bmem.$procmux$1818_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1809:
      Old ports: A=$flatten\imem.\bmem.$procmux$1806_Y [30:0], B=31'0001111111101110111011100010011, Y=$flatten\imem.\bmem.$procmux$1809_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1806_Y [30:2], B=29'00011111111011101110111000100, Y=$flatten\imem.\bmem.$procmux$1809_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1809_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1821:
      Old ports: A=$flatten\imem.\bmem.$procmux$1818_Y, B=267908755, Y=$flatten\imem.\bmem.$procmux$1821_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1818_Y [30:0], B=31'0001111111101111111011010010011, Y=$flatten\imem.\bmem.$procmux$1821_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1821_Y [31] = $flatten\imem.\bmem.$procmux$1821_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1812:
      Old ports: A=$flatten\imem.\bmem.$procmux$1809_Y [30:0], B=31'0000000111001101110011100110011, Y=$flatten\imem.\bmem.$procmux$1812_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1809_Y [30:2], B=29'00000001110011011100111001100, Y=$flatten\imem.\bmem.$procmux$1812_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1812_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1824:
      Old ports: A=$flatten\imem.\bmem.$procmux$1821_Y, B=2606979, Y=$flatten\imem.\bmem.$procmux$1824_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1821_Y [30:0], B=31'0000000001001111100011110000011, Y=$flatten\imem.\bmem.$procmux$1824_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1824_Y [31] = $flatten\imem.\bmem.$procmux$1824_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1815:
      Old ports: A=$flatten\imem.\bmem.$procmux$1812_Y [30:0], B=31'1111110111101000100011100000011, Y=$flatten\imem.\bmem.$procmux$1815_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1812_Y [30:2], B=29'11111101111010001000111000000, Y=$flatten\imem.\bmem.$procmux$1815_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1815_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1827:
      Old ports: A=$flatten\imem.\bmem.$procmux$1824_Y, B=14263, Y=$flatten\imem.\bmem.$procmux$1827_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1824_Y [30:0], B=31'0000000000000000011011110110111, Y=$flatten\imem.\bmem.$procmux$1827_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1827_Y [31] = $flatten\imem.\bmem.$procmux$1827_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1818:
      Old ports: A=$flatten\imem.\bmem.$procmux$1815_Y [30:0], B=31'0000000000000000011011110110111, Y=$flatten\imem.\bmem.$procmux$1818_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1815_Y [30:2], B=29'00000000000000000110111101101, Y=$flatten\imem.\bmem.$procmux$1818_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1818_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1830:
      Old ports: A=$flatten\imem.\bmem.$procmux$1827_Y, B=32'11111110111101000000011110100011, Y=$flatten\imem.\bmem.$procmux$1830_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1827_Y [30:0], B=31'1111110111101000000011110100011, Y=$flatten\imem.\bmem.$procmux$1830_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1830_Y [31] = $flatten\imem.\bmem.$procmux$1830_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1821:
      Old ports: A=$flatten\imem.\bmem.$procmux$1818_Y [30:0], B=31'0001111111101111111011010010011, Y=$flatten\imem.\bmem.$procmux$1821_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1818_Y [30:2], B=29'00011111111011111110110100100, Y=$flatten\imem.\bmem.$procmux$1821_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1821_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1833:
      Old ports: A=$flatten\imem.\bmem.$procmux$1830_Y, B=329619, Y=$flatten\imem.\bmem.$procmux$1833_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1830_Y [30:0], B=31'0000000000001010000011110010011, Y=$flatten\imem.\bmem.$procmux$1833_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1833_Y [31] = $flatten\imem.\bmem.$procmux$1833_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1824:
      Old ports: A=$flatten\imem.\bmem.$procmux$1821_Y [30:0], B=31'0000000001001111100011110000011, Y=$flatten\imem.\bmem.$procmux$1824_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1821_Y [30:2], B=29'00000000010011111000111100000, Y=$flatten\imem.\bmem.$procmux$1824_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1824_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1836:
      Old ports: A=$flatten\imem.\bmem.$procmux$1833_Y, B=33621011, Y=$flatten\imem.\bmem.$procmux$1836_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1833_Y [30:0], B=31'0000010000000010000010000010011, Y=$flatten\imem.\bmem.$procmux$1836_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1836_Y [31] = $flatten\imem.\bmem.$procmux$1836_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1827:
      Old ports: A=$flatten\imem.\bmem.$procmux$1824_Y [30:0], B=31'0000000000000000011011110110111, Y=$flatten\imem.\bmem.$procmux$1827_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1824_Y [30:2], B=29'00000000000000000110111101101, Y=$flatten\imem.\bmem.$procmux$1827_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1827_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1839:
      Old ports: A=$flatten\imem.\bmem.$procmux$1836_Y, B=8465955, Y=$flatten\imem.\bmem.$procmux$1839_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1836_Y [30:0], B=31'0000000100000010010111000100011, Y=$flatten\imem.\bmem.$procmux$1839_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1839_Y [31] = $flatten\imem.\bmem.$procmux$1839_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1830:
      Old ports: A=$flatten\imem.\bmem.$procmux$1827_Y [30:0], B=31'1111110111101000000011110100011, Y=$flatten\imem.\bmem.$procmux$1830_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1827_Y [30:2], B=29'11111101111010000000111101000, Y=$flatten\imem.\bmem.$procmux$1830_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1830_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1842:
      Old ports: A=$flatten\imem.\bmem.$procmux$1839_Y, B=32'11111110000000010000000100010011, Y=$flatten\imem.\bmem.$procmux$1842_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1839_Y [30:0], B=31'1111110000000010000000100010011, Y=$flatten\imem.\bmem.$procmux$1842_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1842_Y [31] = $flatten\imem.\bmem.$procmux$1842_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1833:
      Old ports: A=$flatten\imem.\bmem.$procmux$1830_Y [30:0], B=31'0000000000001010000011110010011, Y=$flatten\imem.\bmem.$procmux$1833_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1830_Y [30:2], B=29'00000000000010100000111100100, Y=$flatten\imem.\bmem.$procmux$1833_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1833_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1845:
      Old ports: A=$flatten\imem.\bmem.$procmux$1842_Y, B=289407215, Y=$flatten\imem.\bmem.$procmux$1845_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1842_Y [30:0], B=31'0010001010000000000000011101111, Y=$flatten\imem.\bmem.$procmux$1845_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1845_Y [31] = $flatten\imem.\bmem.$procmux$1845_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1836:
      Old ports: A=$flatten\imem.\bmem.$procmux$1833_Y [30:0], B=31'0000010000000010000010000010011, Y=$flatten\imem.\bmem.$procmux$1836_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1833_Y [30:2], B=29'00000100000000100000100000100, Y=$flatten\imem.\bmem.$procmux$1836_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1836_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1848:
      Old ports: A=$flatten\imem.\bmem.$procmux$1845_Y, B=1427, Y=$flatten\imem.\bmem.$procmux$1848_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1845_Y [30:0], B=31'0000000000000000000010110010011, Y=$flatten\imem.\bmem.$procmux$1848_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1848_Y [31] = $flatten\imem.\bmem.$procmux$1848_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1839:
      Old ports: A=$flatten\imem.\bmem.$procmux$1836_Y [30:0], B=31'0000000100000010010111000100011, Y=$flatten\imem.\bmem.$procmux$1839_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1836_Y [30:2], B=29'00000001000000100101110001000, Y=$flatten\imem.\bmem.$procmux$1839_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1839_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1851:
      Old ports: A=$flatten\imem.\bmem.$procmux$1848_Y, B=1299, Y=$flatten\imem.\bmem.$procmux$1851_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1848_Y [30:0], B=31'0000000000000000000010100010011, Y=$flatten\imem.\bmem.$procmux$1851_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1851_Y [31] = $flatten\imem.\bmem.$procmux$1851_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1842:
      Old ports: A=$flatten\imem.\bmem.$procmux$1839_Y [30:0], B=31'1111110000000010000000100010011, Y=$flatten\imem.\bmem.$procmux$1842_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1839_Y [30:2], B=29'11111100000000100000001000100, Y=$flatten\imem.\bmem.$procmux$1842_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1842_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1854:
      Old ports: A=$flatten\imem.\bmem.$procmux$1851_Y, B=260112659, Y=$flatten\imem.\bmem.$procmux$1854_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1851_Y [30:0], B=31'0001111100000010000000100010011, Y=$flatten\imem.\bmem.$procmux$1854_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1854_Y [31] = $flatten\imem.\bmem.$procmux$1854_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1845:
      Old ports: A=$flatten\imem.\bmem.$procmux$1842_Y [30:0], B=31'0010001010000000000000011101111, Y=$flatten\imem.\bmem.$procmux$1845_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1842_Y [30:2], B=29'00100010100000000000000111011, Y=$flatten\imem.\bmem.$procmux$1845_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1845_Y [1:0] = 2'11
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1857:
      Old ports: A=$flatten\imem.\bmem.$procmux$1854_Y, B=32'11111111111111111010000100010111, Y=$flatten\imem.\bmem.$procmux$1857_Y
      New ports: A=$flatten\imem.\bmem.$procmux$1854_Y [30:0], B=31'1111111111111111010000100010111, Y=$flatten\imem.\bmem.$procmux$1857_Y [30:0]
      New connections: $flatten\imem.\bmem.$procmux$1857_Y [31] = $flatten\imem.\bmem.$procmux$1857_Y [30]
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1848:
      Old ports: A=$flatten\imem.\bmem.$procmux$1845_Y [30:0], B=31'0000000000000000000010110010011, Y=$flatten\imem.\bmem.$procmux$1848_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1845_Y [30:2], B=29'00000000000000000000101100100, Y=$flatten\imem.\bmem.$procmux$1848_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1848_Y [1:0] = 2'11
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1851:
      Old ports: A=$flatten\imem.\bmem.$procmux$1848_Y [30:0], B=31'0000000000000000000010100010011, Y=$flatten\imem.\bmem.$procmux$1851_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1848_Y [30:2], B=29'00000000000000000000101000100, Y=$flatten\imem.\bmem.$procmux$1851_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1851_Y [1:0] = 2'11
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1854:
      Old ports: A=$flatten\imem.\bmem.$procmux$1851_Y [30:0], B=31'0001111100000010000000100010011, Y=$flatten\imem.\bmem.$procmux$1854_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1851_Y [30:2], B=29'00011111000000100000001000100, Y=$flatten\imem.\bmem.$procmux$1854_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1854_Y [1:0] = 2'11
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1857:
      Old ports: A=$flatten\imem.\bmem.$procmux$1854_Y [30:0], B=31'1111111111111111010000100010111, Y=$flatten\imem.\bmem.$procmux$1857_Y [30:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1854_Y [30:2], B=29'11111111111111110100001000101, Y=$flatten\imem.\bmem.$procmux$1857_Y [30:2]
      New connections: $flatten\imem.\bmem.$procmux$1857_Y [1:0] = 2'11
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1860:
      Old ports: A=$flatten\imem.\bmem.$procmux$1857_Y [22:0], B=23'10000000000000001101111, Y=$auto$wreduce.cc:454:run$2179 [22:0]
      New ports: A=$flatten\imem.\bmem.$procmux$1857_Y [22:2], B=21'100000000000000011011, Y=$auto$wreduce.cc:454:run$2179 [22:2]
      New connections: $auto$wreduce.cc:454:run$2179 [1:0] = 2'11
  Optimizing cells in module \WB_InterConnect.
    Consolidated identical input bits for $mux cell $flatten\imem.\bmem.$procmux$1863:
      Old ports: A=$auto$wreduce.cc:454:run$2179 [4:0], B=5'10011, Y=$flatten\imem.\bmem.$procmux$1863_Y [4:0]
      New ports: A=$auto$wreduce.cc:454:run$2179 [4:2], B=3'100, Y=$flatten\imem.\bmem.$procmux$1863_Y [4:2]
      New connections: $flatten\imem.\bmem.$procmux$1863_Y [1:0] = 2'11
  Optimizing cells in module \WB_InterConnect.
Performed a total of 438 changes.

6.20.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\WB_InterConnect'.
Removed a total of 0 cells.

6.20.6. Executing OPT_SHARE pass.

6.20.7. Executing OPT_DFF pass (perform DFF optimizations).

6.20.8. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \WB_InterConnect..

6.20.9. Executing OPT_EXPR pass (perform const folding).
Optimizing module WB_InterConnect.
<suppressed ~3 debug messages>

6.20.10. Rerunning OPT passes. (Maybe there is more to do..)

6.20.11. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \WB_InterConnect..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~28 debug messages>

6.20.12. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \WB_InterConnect.
Performed a total of 0 changes.

6.20.13. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\WB_InterConnect'.
Removed a total of 0 cells.

6.20.14. Executing OPT_SHARE pass.

6.20.15. Executing OPT_DFF pass (perform DFF optimizations).

6.20.16. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \WB_InterConnect..

6.20.17. Executing OPT_EXPR pass (perform const folding).
Optimizing module WB_InterConnect.

6.20.18. Finished OPT passes. (There is nothing left to do.)

6.21. Executing TECHMAP pass (map to technology primitives).

6.21.1. Executing Verilog-2005 frontend: /build/bin/../share/yosys/techmap.v
Parsing Verilog input from `/build/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

6.21.2. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $logic_not.
Using extmapper simplemap for cells of type $eq.
Using extmapper simplemap for cells of type $mux.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $sdff.
Using extmapper simplemap for cells of type $dff.
Using extmapper simplemap for cells of type $sdffe.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $xor.
Using extmapper simplemap for cells of type $reduce_bool.
Using extmapper simplemap for cells of type $reduce_and.
Using extmapper simplemap for cells of type $ne.
Using template $paramod$672a140277c71df8314410f22acc08d55222c3c7\_90_alu for cells of type $alu.
Using template $paramod$1eb759649286d7485bd82f4dfc30385bade4b4b3\_90_alu for cells of type $alu.
Using template $paramod$8742280fdebca84e1c87f2a86ed84f62d558f4cc\_90_alu for cells of type $alu.
Using template $paramod$19189243523493d505a4933d1bad417c570ea8a6\_90_alu for cells of type $alu.
Using extmapper simplemap for cells of type $reduce_or.
Using extmapper simplemap for cells of type $sdffce.
Using template $paramod$53700bbee849b2010ad0b60a61ccd204a10e24ca\_90_alu for cells of type $alu.
Using template $paramod$32efbfac1c4dc57230cf86180788fdfd12e3b511\_90_alu for cells of type $alu.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000101 for cells of type $lcu.
Using extmapper simplemap for cells of type $pos.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000001010 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000001001 for cells of type $lcu.
Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000110 for cells of type $lcu.
No more expansions possible.
<suppressed ~1736 debug messages>

6.22. Executing OPT pass (performing simple optimizations).

6.22.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module WB_InterConnect.
<suppressed ~8542 debug messages>

6.22.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\WB_InterConnect'.
<suppressed ~9474 debug messages>
Removed a total of 3158 cells.

6.22.3. Executing OPT_DFF pass (perform DFF optimizations).

6.22.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \WB_InterConnect..
Removed 100 unused cells and 2139 unused wires.
<suppressed ~114 debug messages>

6.22.5. Finished fast OPT passes.

6.23. Executing ABC pass (technology mapping using ABC).

6.23.1. Extracting gate netlist of module `\WB_InterConnect' to `<abc-temp-dir>/input.blif'..
Extracted 8484 gates and 8840 wires to a netlist network with 353 inputs and 270 outputs.

6.23.1.1. Executing ABC.
Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC: 
ABC: + read_blif <abc-temp-dir>/input.blif 
ABC: + read_library <abc-temp-dir>/stdcells.genlib 
ABC: Entered genlib library with 13 gates from file "<abc-temp-dir>/stdcells.genlib".
ABC: + strash 
ABC: + dretime 
ABC: + map 
ABC: + write_blif <abc-temp-dir>/output.blif 

6.23.1.2. Re-integrating ABC results.
ABC RESULTS:               AND cells:       77
ABC RESULTS:            ANDNOT cells:     1849
ABC RESULTS:               MUX cells:      377
ABC RESULTS:              NAND cells:       53
ABC RESULTS:               NOR cells:      977
ABC RESULTS:               NOT cells:      262
ABC RESULTS:                OR cells:     4524
ABC RESULTS:             ORNOT cells:      171
ABC RESULTS:              XNOR cells:       10
ABC RESULTS:               XOR cells:       46
ABC RESULTS:        internal signals:     8217
ABC RESULTS:           input signals:      353
ABC RESULTS:          output signals:      270
Removing temp directory.

6.24. Executing OPT pass (performing simple optimizations).

6.24.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module WB_InterConnect.
<suppressed ~79 debug messages>

6.24.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\WB_InterConnect'.
<suppressed ~51 debug messages>
Removed a total of 17 cells.

6.24.3. Executing OPT_DFF pass (perform DFF optimizations).

6.24.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \WB_InterConnect..
Removed 4 unused cells and 1719 unused wires.
<suppressed ~368 debug messages>

6.24.5. Finished fast OPT passes.

6.25. Executing HIERARCHY pass (managing design hierarchy).

6.25.1. Analyzing design hierarchy..
Top module:  \WB_InterConnect

6.25.2. Analyzing design hierarchy..
Top module:  \WB_InterConnect
Removed 0 unused modules.

6.26. Printing statistics.

=== WB_InterConnect ===

   Number of wires:               8583
   Number of wire bits:          11058
   Number of public wires:         396
   Number of public wire bits:    2871
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:               8561
     $_ANDNOT_                    1849
     $_AND_                         77
     $_DFF_P_                       20
     $_MUX_                        377
     $_NAND_                        53
     $_NOR_                        966
     $_NOT_                        258
     $_ORNOT_                      170
     $_OR_                        4519
     $_SDFFCE_PN0P_                  3
     $_SDFFCE_PN1P_                  1
     $_SDFFE_PP0N_                  11
     $_SDFFE_PP0P_                 157
     $_SDFFE_PP1P_                  14
     $_SDFF_PN0_                     1
     $_SDFF_PP0_                    27
     $_SDFF_PP1_                     2
     $_XNOR_                        10
     $_XOR_                         46

6.27. Executing CHECK pass (checking for obvious problems).
Checking module WB_InterConnect...
Found and reported 0 problems.

7. Generating Graphviz representation of design.
Writing dot description to `/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/synthesis/post_techmap.dot'.
Dumping module WB_InterConnect to page 1.

8. Executing SHARE pass (SAT-based resource sharing).

9. Executing OPT pass (performing simple optimizations).

9.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module WB_InterConnect.

9.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\WB_InterConnect'.
Removed a total of 0 cells.

9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \WB_InterConnect..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \WB_InterConnect.
Performed a total of 0 changes.

9.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\WB_InterConnect'.
Removed a total of 0 cells.

9.6. Executing OPT_DFF pass (perform DFF optimizations).

9.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \WB_InterConnect..

9.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module WB_InterConnect.

9.9. Finished OPT passes. (There is nothing left to do.)

10. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \WB_InterConnect..
Removed 0 unused cells and 263 unused wires.
<suppressed ~263 debug messages>

11. Printing statistics.

=== WB_InterConnect ===

   Number of wires:               8320
   Number of wire bits:           8974
   Number of public wires:         133
   Number of public wire bits:     787
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:               8561
     $_ANDNOT_                    1849
     $_AND_                         77
     $_DFF_P_                       20
     $_MUX_                        377
     $_NAND_                        53
     $_NOR_                        966
     $_NOT_                        258
     $_ORNOT_                      170
     $_OR_                        4519
     $_SDFFCE_PN0P_                  3
     $_SDFFCE_PN1P_                  1
     $_SDFFE_PP0N_                  11
     $_SDFFE_PP0P_                 157
     $_SDFFE_PP1P_                  14
     $_SDFF_PN0_                     1
     $_SDFF_PP0_                    27
     $_SDFF_PP1_                     2
     $_XNOR_                        10
     $_XOR_                         46

mapping tbuf

12. Executing TECHMAP pass (map to technology primitives).

12.1. Executing Verilog-2005 frontend: /home/ali112000/Desktop/mpw/pdk/sky130A/libs.tech/openlane/sky130_fd_sc_hd/tribuff_map.v
Parsing Verilog input from `/home/ali112000/Desktop/mpw/pdk/sky130A/libs.tech/openlane/sky130_fd_sc_hd/tribuff_map.v' to AST representation.
Generating RTLIL representation for module `\$_TBUF_'.
Successfully finished Verilog frontend.

12.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~3 debug messages>

13. Executing SIMPLEMAP pass (map simple cells to gate primitives).

14. Executing TECHMAP pass (map to technology primitives).

14.1. Executing Verilog-2005 frontend: /home/ali112000/Desktop/mpw/pdk/sky130A/libs.tech/openlane/sky130_fd_sc_hd/latch_map.v
Parsing Verilog input from `/home/ali112000/Desktop/mpw/pdk/sky130A/libs.tech/openlane/sky130_fd_sc_hd/latch_map.v' to AST representation.
Generating RTLIL representation for module `\$_DLATCH_P_'.
Generating RTLIL representation for module `\$_DLATCH_N_'.
Successfully finished Verilog frontend.

14.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~4 debug messages>

15. Executing SIMPLEMAP pass (map simple cells to gate primitives).

16. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).
  cell sky130_fd_sc_hd__dfxtp_2 (noninv, pins=3, area=21.27) is a direct match for cell type $_DFF_P_.
  cell sky130_fd_sc_hd__dfrtp_2 (noninv, pins=4, area=26.28) is a direct match for cell type $_DFF_PN0_.
  cell sky130_fd_sc_hd__dfstp_2 (noninv, pins=4, area=26.28) is a direct match for cell type $_DFF_PN1_.
  cell sky130_fd_sc_hd__dfbbn_2 (noninv, pins=6, area=35.03) is a direct match for cell type $_DFFSR_NNN_.
  final dff cell mappings:
    unmapped dff cell: $_DFF_N_
    \sky130_fd_sc_hd__dfxtp_2 _DFF_P_ (.CLK( C), .D( D), .Q( Q));
    unmapped dff cell: $_DFF_NN0_
    unmapped dff cell: $_DFF_NN1_
    unmapped dff cell: $_DFF_NP0_
    unmapped dff cell: $_DFF_NP1_
    \sky130_fd_sc_hd__dfrtp_2 _DFF_PN0_ (.CLK( C), .D( D), .Q( Q), .RESET_B( R));
    \sky130_fd_sc_hd__dfstp_2 _DFF_PN1_ (.CLK( C), .D( D), .Q( Q), .SET_B( R));
    unmapped dff cell: $_DFF_PP0_
    unmapped dff cell: $_DFF_PP1_
    \sky130_fd_sc_hd__dfbbn_2 _DFFSR_NNN_ (.CLK_N( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B( R), .SET_B( S));
    unmapped dff cell: $_DFFSR_NNP_
    unmapped dff cell: $_DFFSR_NPN_
    unmapped dff cell: $_DFFSR_NPP_
    unmapped dff cell: $_DFFSR_PNN_
    unmapped dff cell: $_DFFSR_PNP_
    unmapped dff cell: $_DFFSR_PPN_
    unmapped dff cell: $_DFFSR_PPP_

16.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
Mapping DFF cells in module `\WB_InterConnect':
  mapped 236 $_DFF_P_ cells to \sky130_fd_sc_hd__dfxtp_2 cells.

17. Printing statistics.

=== WB_InterConnect ===

   Number of wires:               8722
   Number of wire bits:           9376
   Number of public wires:         133
   Number of public wire bits:     787
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:               8963
     $_ANDNOT_                    1849
     $_AND_                         77
     $_MUX_                        779
     $_NAND_                        53
     $_NOR_                        966
     $_NOT_                        258
     $_ORNOT_                      170
     $_OR_                        4519
     $_XNOR_                        10
     $_XOR_                         46
     sky130_fd_sc_hd__dfxtp_2      236

[INFO]: ABC: WireLoad : S_4

18. Executing ABC pass (technology mapping using ABC).

18.1. Extracting gate netlist of module `\WB_InterConnect' to `/tmp/yosys-abc-PRyfeJ/input.blif'..
Extracted 8727 gates and 9108 wires to a netlist network with 379 inputs and 319 outputs.

18.1.1. Executing ABC.
Running ABC command: /build/bin/yosys-abc -s -f /tmp/yosys-abc-PRyfeJ/abc.script 2>&1
ABC: ABC command line: "source /tmp/yosys-abc-PRyfeJ/abc.script".
ABC: 
ABC: + read_blif /tmp/yosys-abc-PRyfeJ/input.blif 
ABC: + read_lib -w /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/synthesis/trimmed.lib 
ABC: Parsing finished successfully.  Parsing time =     0.07 sec
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfsbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtp_1".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_2".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_4".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_8".
ABC: Library "sky130A_merged" from "/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/synthesis/trimmed.lib" has 175 cells (17 skipped: 14 seq; 3 tri-state; 0 no func; 0 dont_use).  Time =     0.10 sec
ABC: Memory =    7.77 MB. Time =     0.10 sec
ABC: Warning: Detected 2 multi-output gates (for example, "sky130_fd_sc_hd__fa_1").
ABC: + read_constr -v /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/synthesis/synthesis.sdc 
ABC: Setting driving cell to be "sky130_fd_sc_hd__inv_2".
ABC: Setting output load to be 33.442001.
ABC: + read_constr /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/synthesis/synthesis.sdc 
ABC: + fx 
ABC: + mfs 
ABC: + strash 
ABC: + refactor 
ABC: + balance 
ABC: + rewrite 
ABC: + refactor 
ABC: + balance 
ABC: + rewrite 
ABC: + rewrite -z 
ABC: + balance 
ABC: + refactor -z 
ABC: + rewrite -z 
ABC: + balance 
ABC: + retime -D -D 20000 -M 5 
ABC: + scleanup 
ABC: Error: The network is combinational.
ABC: + fraig_store 
ABC: + balance 
ABC: + fraig_store 
ABC: + balance 
ABC: + rewrite 
ABC: + refactor 
ABC: + balance 
ABC: + rewrite 
ABC: + rewrite -z 
ABC: + balance 
ABC: + refactor -z 
ABC: + rewrite -z 
ABC: + balance 
ABC: + fraig_store 
ABC: + balance 
ABC: + rewrite 
ABC: + refactor 
ABC: + balance 
ABC: + rewrite 
ABC: + rewrite -z 
ABC: + balance 
ABC: + refactor -z 
ABC: + rewrite -z 
ABC: + balance 
ABC: + fraig_store 
ABC: + balance 
ABC: + rewrite 
ABC: + refactor 
ABC: + balance 
ABC: + rewrite 
ABC: + rewrite -z 
ABC: + balance 
ABC: + refactor -z 
ABC: + rewrite -z 
ABC: + balance 
ABC: + fraig_store 
ABC: + fraig_restore 
ABC: + amap -m -Q 0.1 -F 20 -A 20 -C 5000 
ABC: + retime -D -D 20000 
ABC: + &get -n 
ABC: + &st 
ABC: + &dch 
ABC: + &nf 
ABC: + &put 
ABC: + buffer -N 5 -S 750.0 
ABC: + upsize -D 20000 
ABC: Current delay (10334.38 ps) does not exceed the target delay (20000.00 ps). Upsizing is not performed.
ABC: + dnsize -D 20000 
ABC: + stime -p 
ABC: WireLoad = "none"  Gates =   2386 ( 24.5 %)   Cap =  9.2 ff (  5.9 %)   Area =    17656.93 ( 75.5 %)   Delay = 10260.19 ps  (  2.1 %)               
ABC: Path  0 --     224 : 0    4 pi                       A =   0.00  Df =  25.9  -14.8 ps  S =  41.5 ps  Cin =  0.0 ff  Cout =   7.5 ff  Cmax =   0.0 ff  G =    0  
ABC: Path  1 --    1162 : 1    5 sky130_fd_sc_hd__buf_1   A =   3.75  Df = 205.8  -68.9 ps  S = 190.3 ps  Cin =  2.1 ff  Cout =  15.5 ff  Cmax = 130.0 ff  G =  701  
ABC: Path  2 --    1354 : 2    3 sky130_fd_sc_hd__xor2_2  A =  16.27  Df = 415.6  -93.9 ps  S = 123.0 ps  Cin =  8.6 ff  Cout =   5.3 ff  Cmax = 130.0 ff  G =   59  
ABC: Path  3 --    1355 : 3    3 sky130_fd_sc_hd__and3_2  A =   7.51  Df = 610.7  -79.4 ps  S =  52.3 ps  Cin =  1.5 ff  Cout =   4.6 ff  Cmax = 309.5 ff  G =  294  
ABC: Path  4 --    2238 : 4    1 sky130_fd_sc_hd__or4_2   A =   8.76  Df =1170.0  -18.0 ps  S =  92.1 ps  Cin =  1.5 ff  Cout =   1.8 ff  Cmax = 310.4 ff  G =  114  
ABC: Path  5 --    2244 : 4    1 sky130_fd_sc_hd__or4_2   A =   8.76  Df =1801.1 -399.6 ps  S =  89.9 ps  Cin =  1.5 ff  Cout =   1.4 ff  Cmax = 310.4 ff  G =   89  
ABC: Path  6 --    2245 : 4    1 sky130_fd_sc_hd__or4_2   A =   8.76  Df =2327.5 -842.2 ps  S =  89.8 ps  Cin =  1.5 ff  Cout =   1.4 ff  Cmax = 310.4 ff  G =   89  
ABC: Path  7 --    2246 : 4    1 sky130_fd_sc_hd__or4_2   A =   8.76  Df =2853.9-1284.7 ps  S =  89.9 ps  Cin =  1.5 ff  Cout =   1.4 ff  Cmax = 310.4 ff  G =   89  
ABC: Path  8 --    2247 : 4    1 sky130_fd_sc_hd__or4_2   A =   8.76  Df =3380.2-1727.2 ps  S =  89.9 ps  Cin =  1.5 ff  Cout =   1.4 ff  Cmax = 310.4 ff  G =   89  
ABC: Path  9 --    2248 : 4    1 sky130_fd_sc_hd__or4_2   A =   8.76  Df =3906.6-2169.7 ps  S =  89.9 ps  Cin =  1.5 ff  Cout =   1.4 ff  Cmax = 310.4 ff  G =   89  
ABC: Path 10 --    2249 : 4    1 sky130_fd_sc_hd__or4_2   A =   8.76  Df =4433.0-2612.1 ps  S =  89.9 ps  Cin =  1.5 ff  Cout =   1.4 ff  Cmax = 310.4 ff  G =   89  
ABC: Path 11 --    2250 : 4    1 sky130_fd_sc_hd__or4_2   A =   8.76  Df =4959.4-3054.7 ps  S =  89.9 ps  Cin =  1.5 ff  Cout =   1.4 ff  Cmax = 310.4 ff  G =   89  
ABC: Path 12 --    2251 : 4    1 sky130_fd_sc_hd__or4_2   A =   8.76  Df =5485.7-3497.2 ps  S =  89.9 ps  Cin =  1.5 ff  Cout =   1.4 ff  Cmax = 310.4 ff  G =   89  
ABC: Path 13 --    2252 : 4    1 sky130_fd_sc_hd__or4_2   A =   8.76  Df =6012.1-3939.7 ps  S =  89.9 ps  Cin =  1.5 ff  Cout =   1.4 ff  Cmax = 310.4 ff  G =   89  
ABC: Path 14 --    2253 : 4    1 sky130_fd_sc_hd__or4_2   A =   8.76  Df =6540.3-4383.2 ps  S =  90.9 ps  Cin =  1.5 ff  Cout =   1.6 ff  Cmax = 310.4 ff  G =  100  
ABC: Path 15 --    2255 : 4    1 sky130_fd_sc_hd__or4_2   A =   8.76  Df =7136.6-4892.4 ps  S =  89.9 ps  Cin =  1.5 ff  Cout =   1.4 ff  Cmax = 310.4 ff  G =   89  
ABC: Path 16 --    2256 : 4    1 sky130_fd_sc_hd__or4_2   A =   8.76  Df =7664.8-5336.0 ps  S =  90.9 ps  Cin =  1.5 ff  Cout =   1.6 ff  Cmax = 310.4 ff  G =  100  
ABC: Path 17 --    2258 : 4    1 sky130_fd_sc_hd__or4_2   A =   8.76  Df =8261.1-5845.2 ps  S =  89.9 ps  Cin =  1.5 ff  Cout =   1.4 ff  Cmax = 310.4 ff  G =   89  
ABC: Path 18 --    2259 : 4    1 sky130_fd_sc_hd__or4_2   A =   8.76  Df =8789.3-6288.5 ps  S =  90.9 ps  Cin =  1.5 ff  Cout =   1.6 ff  Cmax = 310.4 ff  G =  100  
ABC: Path 19 --    2263 : 4    1 sky130_fd_sc_hd__or4_2   A =   8.76  Df =9385.6-6797.7 ps  S =  89.9 ps  Cin =  1.5 ff  Cout =   1.4 ff  Cmax = 310.4 ff  G =   89  
ABC: Path 20 --    2264 : 4    1 sky130_fd_sc_hd__or4_2   A =   8.76  Df =9921.2-7244.7 ps  S =  95.3 ps  Cin =  1.5 ff  Cout =   2.5 ff  Cmax = 310.4 ff  G =  154  
ABC: Path 21 --    2269 : 4    1 sky130_fd_sc_hd__o211a_2 A =  10.01  Df =10260.2-7302.4 ps  S = 203.7 ps  Cin =  2.4 ff  Cout =  33.4 ff  Cmax = 268.3 ff  G = 1415  
ABC: Start-point = pi223 (\io_ibus_addr [2]).  End-point = po211 ($auto$rtlil.cc:2515:MuxGate$28479).
ABC: + print_stats -m 
ABC: netlist                       : i/o =  379/  319  lat =    0  nd =  2386  edge =   6067  area =17658.11  delay =22.00  lev = 22
ABC: + write_blif /tmp/yosys-abc-PRyfeJ/output.blif 

18.1.2. Re-integrating ABC results.
ABC RESULTS:   sky130_fd_sc_hd__a2111o_2 cells:       19
ABC RESULTS:   sky130_fd_sc_hd__a2111oi_2 cells:        1
ABC RESULTS:   sky130_fd_sc_hd__a211o_2 cells:       21
ABC RESULTS:   sky130_fd_sc_hd__a211oi_2 cells:        3
ABC RESULTS:   sky130_fd_sc_hd__a21bo_2 cells:        3
ABC RESULTS:   sky130_fd_sc_hd__a21boi_2 cells:        3
ABC RESULTS:   sky130_fd_sc_hd__a21o_2 cells:       41
ABC RESULTS:   sky130_fd_sc_hd__a21oi_2 cells:       57
ABC RESULTS:   sky130_fd_sc_hd__a221o_2 cells:       12
ABC RESULTS:   sky130_fd_sc_hd__a221oi_2 cells:        3
ABC RESULTS:   sky130_fd_sc_hd__a22o_2 cells:       92
ABC RESULTS:   sky130_fd_sc_hd__a2bb2o_2 cells:       22
ABC RESULTS:   sky130_fd_sc_hd__a311o_2 cells:        5
ABC RESULTS:   sky130_fd_sc_hd__a311oi_2 cells:        1
ABC RESULTS:   sky130_fd_sc_hd__a31o_2 cells:       30
ABC RESULTS:   sky130_fd_sc_hd__a31oi_2 cells:        3
ABC RESULTS:   sky130_fd_sc_hd__a32o_2 cells:       14
ABC RESULTS:   sky130_fd_sc_hd__and2_2 cells:       97
ABC RESULTS:   sky130_fd_sc_hd__and2b_2 cells:        7
ABC RESULTS:   sky130_fd_sc_hd__and3_2 cells:       24
ABC RESULTS:   sky130_fd_sc_hd__and3b_2 cells:       10
ABC RESULTS:   sky130_fd_sc_hd__and4_2 cells:        5
ABC RESULTS:   sky130_fd_sc_hd__and4b_2 cells:        1
ABC RESULTS:   sky130_fd_sc_hd__and4bb_2 cells:        4
ABC RESULTS:   sky130_fd_sc_hd__buf_1 cells:      541
ABC RESULTS:   sky130_fd_sc_hd__buf_2 cells:        2
ABC RESULTS:   sky130_fd_sc_hd__inv_2 cells:       41
ABC RESULTS:   sky130_fd_sc_hd__mux2_2 cells:      149
ABC RESULTS:   sky130_fd_sc_hd__nand2_2 cells:       89
ABC RESULTS:   sky130_fd_sc_hd__nand2b_2 cells:        1
ABC RESULTS:   sky130_fd_sc_hd__nand3b_2 cells:        1
ABC RESULTS:   sky130_fd_sc_hd__nand4b_2 cells:        4
ABC RESULTS:   sky130_fd_sc_hd__nor2_2 cells:      275
ABC RESULTS:   sky130_fd_sc_hd__nor2b_2 cells:        1
ABC RESULTS:   sky130_fd_sc_hd__nor3_2 cells:        7
ABC RESULTS:   sky130_fd_sc_hd__nor3b_2 cells:        2
ABC RESULTS:   sky130_fd_sc_hd__nor4_2 cells:        4
ABC RESULTS:   sky130_fd_sc_hd__nor4b_2 cells:        1
ABC RESULTS:   sky130_fd_sc_hd__o2111a_2 cells:        2
ABC RESULTS:   sky130_fd_sc_hd__o211a_2 cells:       61
ABC RESULTS:   sky130_fd_sc_hd__o21a_2 cells:       26
ABC RESULTS:   sky130_fd_sc_hd__o21ai_2 cells:       32
ABC RESULTS:   sky130_fd_sc_hd__o21ba_2 cells:       10
ABC RESULTS:   sky130_fd_sc_hd__o21bai_2 cells:        4
ABC RESULTS:   sky130_fd_sc_hd__o221a_2 cells:       18
ABC RESULTS:   sky130_fd_sc_hd__o221ai_2 cells:        1
ABC RESULTS:   sky130_fd_sc_hd__o22a_2 cells:       11
ABC RESULTS:   sky130_fd_sc_hd__o22ai_2 cells:        4
ABC RESULTS:   sky130_fd_sc_hd__o2bb2a_2 cells:       26
ABC RESULTS:   sky130_fd_sc_hd__o311a_2 cells:        5
ABC RESULTS:   sky130_fd_sc_hd__o31a_2 cells:        5
ABC RESULTS:   sky130_fd_sc_hd__o31ai_2 cells:        3
ABC RESULTS:   sky130_fd_sc_hd__o41a_2 cells:        1
ABC RESULTS:   sky130_fd_sc_hd__or2_2 cells:      167
ABC RESULTS:   sky130_fd_sc_hd__or2b_2 cells:       10
ABC RESULTS:   sky130_fd_sc_hd__or3_2 cells:      111
ABC RESULTS:   sky130_fd_sc_hd__or3b_2 cells:       15
ABC RESULTS:   sky130_fd_sc_hd__or4_2 cells:      234
ABC RESULTS:   sky130_fd_sc_hd__or4b_2 cells:       28
ABC RESULTS:   sky130_fd_sc_hd__or4bb_2 cells:        7
ABC RESULTS:   sky130_fd_sc_hd__xnor2_2 cells:        2
ABC RESULTS:   sky130_fd_sc_hd__xor2_2 cells:        7
ABC RESULTS:        internal signals:     8410
ABC RESULTS:           input signals:      379
ABC RESULTS:          output signals:      319
Removing temp directory.

19. Executing SETUNDEF pass (replace undef values with defined constants).

20. Executing HILOMAP pass (mapping to constant drivers).

21. Executing SPLITNETS pass (splitting up multi-bit signals).

22. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \WB_InterConnect..
Removed 60 unused cells and 9244 unused wires.
<suppressed ~189 debug messages>

23. Executing INSBUF pass (insert buffer cells for connected wires).
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31387: \io_dbus_addr [2] -> \io_dmem_io_addr [0]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31388: \io_dbus_addr [3] -> \io_dmem_io_addr [1]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31389: \io_dbus_addr [4] -> \io_dmem_io_addr [2]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31390: \io_dbus_addr [5] -> \io_dmem_io_addr [3]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31391: \io_dbus_addr [6] -> \io_dmem_io_addr [4]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31392: \io_dbus_addr [7] -> \io_dmem_io_addr [5]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31393: \io_dbus_addr [8] -> \io_dmem_io_addr [6]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31394: \io_dbus_addr [9] -> \io_dmem_io_addr [7]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31395: \io_dbus_wdata [0] -> \io_dmem_io_wdata [0]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31396: \io_dbus_wdata [1] -> \io_dmem_io_wdata [1]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31397: \io_dbus_wdata [2] -> \io_dmem_io_wdata [2]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31398: \io_dbus_wdata [3] -> \io_dmem_io_wdata [3]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31399: \io_dbus_wdata [4] -> \io_dmem_io_wdata [4]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31400: \io_dbus_wdata [5] -> \io_dmem_io_wdata [5]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31401: \io_dbus_wdata [6] -> \io_dmem_io_wdata [6]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31402: \io_dbus_wdata [7] -> \io_dmem_io_wdata [7]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31403: \io_dbus_wdata [8] -> \io_dmem_io_wdata [8]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31404: \io_dbus_wdata [9] -> \io_dmem_io_wdata [9]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31405: \io_dbus_wdata [10] -> \io_dmem_io_wdata [10]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31406: \io_dbus_wdata [11] -> \io_dmem_io_wdata [11]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31407: \io_dbus_wdata [12] -> \io_dmem_io_wdata [12]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31408: \io_dbus_wdata [13] -> \io_dmem_io_wdata [13]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31409: \io_dbus_wdata [14] -> \io_dmem_io_wdata [14]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31410: \io_dbus_wdata [15] -> \io_dmem_io_wdata [15]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31411: \io_dbus_wdata [16] -> \io_dmem_io_wdata [16]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31412: \io_dbus_wdata [17] -> \io_dmem_io_wdata [17]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31413: \io_dbus_wdata [18] -> \io_dmem_io_wdata [18]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31414: \io_dbus_wdata [19] -> \io_dmem_io_wdata [19]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31415: \io_dbus_wdata [20] -> \io_dmem_io_wdata [20]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31416: \io_dbus_wdata [21] -> \io_dmem_io_wdata [21]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31417: \io_dbus_wdata [22] -> \io_dmem_io_wdata [22]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31418: \io_dbus_wdata [23] -> \io_dmem_io_wdata [23]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31419: \io_dbus_wdata [24] -> \io_dmem_io_wdata [24]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31420: \io_dbus_wdata [25] -> \io_dmem_io_wdata [25]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31421: \io_dbus_wdata [26] -> \io_dmem_io_wdata [26]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31422: \io_dbus_wdata [27] -> \io_dmem_io_wdata [27]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31423: \io_dbus_wdata [28] -> \io_dmem_io_wdata [28]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31424: \io_dbus_wdata [29] -> \io_dmem_io_wdata [29]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31425: \io_dbus_wdata [30] -> \io_dmem_io_wdata [30]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31426: \io_dbus_wdata [31] -> \io_dmem_io_wdata [31]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31427: \io_dmem_io_st_type [0] -> \io_imem_io_st_type [0]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31428: \io_dmem_io_st_type [1] -> \io_imem_io_st_type [1]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31429: \io_dmem_io_st_type [2] -> \io_imem_io_st_type [2]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31430: \io_dmem_io_st_type [3] -> \io_imem_io_st_type [3]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31431: \io_dbus_wdata [0] -> \io_imem_io_wdata [0]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31432: \io_dbus_wdata [1] -> \io_imem_io_wdata [1]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31433: \io_dbus_wdata [2] -> \io_imem_io_wdata [2]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31434: \io_dbus_wdata [3] -> \io_imem_io_wdata [3]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31435: \io_dbus_wdata [4] -> \io_imem_io_wdata [4]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31436: \io_dbus_wdata [5] -> \io_imem_io_wdata [5]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31437: \io_dbus_wdata [6] -> \io_imem_io_wdata [6]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31438: \io_dbus_wdata [7] -> \io_imem_io_wdata [7]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31439: \io_dbus_wdata [8] -> \io_imem_io_wdata [8]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31440: \io_dbus_wdata [9] -> \io_imem_io_wdata [9]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31441: \io_dbus_wdata [10] -> \io_imem_io_wdata [10]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31442: \io_dbus_wdata [11] -> \io_imem_io_wdata [11]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31443: \io_dbus_wdata [12] -> \io_imem_io_wdata [12]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31444: \io_dbus_wdata [13] -> \io_imem_io_wdata [13]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31445: \io_dbus_wdata [14] -> \io_imem_io_wdata [14]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31446: \io_dbus_wdata [15] -> \io_imem_io_wdata [15]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31447: \io_dbus_wdata [16] -> \io_imem_io_wdata [16]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31448: \io_dbus_wdata [17] -> \io_imem_io_wdata [17]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31449: \io_dbus_wdata [18] -> \io_imem_io_wdata [18]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31450: \io_dbus_wdata [19] -> \io_imem_io_wdata [19]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31451: \io_dbus_wdata [20] -> \io_imem_io_wdata [20]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31452: \io_dbus_wdata [21] -> \io_imem_io_wdata [21]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31453: \io_dbus_wdata [22] -> \io_imem_io_wdata [22]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31454: \io_dbus_wdata [23] -> \io_imem_io_wdata [23]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31455: \io_dbus_wdata [24] -> \io_imem_io_wdata [24]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31456: \io_dbus_wdata [25] -> \io_imem_io_wdata [25]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31457: \io_dbus_wdata [26] -> \io_imem_io_wdata [26]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31458: \io_dbus_wdata [27] -> \io_imem_io_wdata [27]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31459: \io_dbus_wdata [28] -> \io_imem_io_wdata [28]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31460: \io_dbus_wdata [29] -> \io_imem_io_wdata [29]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31461: \io_dbus_wdata [30] -> \io_imem_io_wdata [30]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31462: \io_dbus_wdata [31] -> \io_imem_io_wdata [31]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31463: \io_spi_clk_en -> \io_spi_cs_en
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31464: \io_spi_clk_en -> \io_spi_mosi_en
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31465: \io_dbus_addr [0] -> \io_wbm_m2s_addr [0]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31466: \io_dbus_addr [1] -> \io_wbm_m2s_addr [1]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31467: \io_dbus_addr [2] -> \io_wbm_m2s_addr [2]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31468: \io_dbus_addr [3] -> \io_wbm_m2s_addr [3]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31469: \io_dbus_addr [4] -> \io_wbm_m2s_addr [4]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31470: \io_dbus_addr [5] -> \io_wbm_m2s_addr [5]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31471: \io_dbus_addr [6] -> \io_wbm_m2s_addr [6]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31472: \io_dbus_addr [7] -> \io_wbm_m2s_addr [7]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31473: \io_dbus_addr [8] -> \io_wbm_m2s_addr [8]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31474: \io_dbus_addr [9] -> \io_wbm_m2s_addr [9]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31475: \io_dbus_addr [10] -> \io_wbm_m2s_addr [10]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31476: \io_dbus_addr [11] -> \io_wbm_m2s_addr [11]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31477: \io_dbus_addr [12] -> \io_wbm_m2s_addr [12]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31478: \io_dbus_addr [13] -> \io_wbm_m2s_addr [13]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31479: \io_dbus_addr [14] -> \io_wbm_m2s_addr [14]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31480: \io_dbus_addr [15] -> \io_wbm_m2s_addr [15]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31481: \io_dbus_wdata [0] -> \io_wbm_m2s_data [0]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31482: \io_dbus_wdata [1] -> \io_wbm_m2s_data [1]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31483: \io_dbus_wdata [2] -> \io_wbm_m2s_data [2]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31484: \io_dbus_wdata [3] -> \io_wbm_m2s_data [3]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31485: \io_dbus_wdata [4] -> \io_wbm_m2s_data [4]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31486: \io_dbus_wdata [5] -> \io_wbm_m2s_data [5]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31487: \io_dbus_wdata [6] -> \io_wbm_m2s_data [6]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31488: \io_dbus_wdata [7] -> \io_wbm_m2s_data [7]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31489: \io_dbus_wdata [8] -> \io_wbm_m2s_data [8]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31490: \io_dbus_wdata [9] -> \io_wbm_m2s_data [9]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31491: \io_dbus_wdata [10] -> \io_wbm_m2s_data [10]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31492: \io_dbus_wdata [11] -> \io_wbm_m2s_data [11]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31493: \io_dbus_wdata [12] -> \io_wbm_m2s_data [12]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31494: \io_dbus_wdata [13] -> \io_wbm_m2s_data [13]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31495: \io_dbus_wdata [14] -> \io_wbm_m2s_data [14]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31496: \io_dbus_wdata [15] -> \io_wbm_m2s_data [15]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31497: \io_dbus_wdata [16] -> \io_wbm_m2s_data [16]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31498: \io_dbus_wdata [17] -> \io_wbm_m2s_data [17]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31499: \io_dbus_wdata [18] -> \io_wbm_m2s_data [18]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31500: \io_dbus_wdata [19] -> \io_wbm_m2s_data [19]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31501: \io_dbus_wdata [20] -> \io_wbm_m2s_data [20]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31502: \io_dbus_wdata [21] -> \io_wbm_m2s_data [21]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31503: \io_dbus_wdata [22] -> \io_wbm_m2s_data [22]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31504: \io_dbus_wdata [23] -> \io_wbm_m2s_data [23]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31505: \io_dbus_wdata [24] -> \io_wbm_m2s_data [24]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31506: \io_dbus_wdata [25] -> \io_wbm_m2s_data [25]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31507: \io_dbus_wdata [26] -> \io_wbm_m2s_data [26]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31508: \io_dbus_wdata [27] -> \io_wbm_m2s_data [27]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31509: \io_dbus_wdata [28] -> \io_wbm_m2s_data [28]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31510: \io_dbus_wdata [29] -> \io_wbm_m2s_data [29]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31511: \io_dbus_wdata [30] -> \io_wbm_m2s_data [30]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31512: \io_dbus_wdata [31] -> \io_wbm_m2s_data [31]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31513: \io_dmem_io_st_type [0] -> \io_wbm_m2s_sel [0]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31514: \io_dmem_io_st_type [1] -> \io_wbm_m2s_sel [1]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31515: \io_dmem_io_st_type [2] -> \io_wbm_m2s_sel [2]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31516: \io_dmem_io_st_type [3] -> \io_wbm_m2s_sel [3]
Added WB_InterConnect.$auto$insbuf.cc:79:execute$31517: \io_dbus_wr_en -> \io_wbm_m2s_we

24. Executing CHECK pass (checking for obvious problems).
Checking module WB_InterConnect...
Warning: Wire WB_InterConnect.\io_wbm_m2s_we is used but has no driver.
Warning: Wire WB_InterConnect.\io_wbm_m2s_stb is used but has no driver.
Warning: Wire WB_InterConnect.\io_wbm_m2s_sel [3] is used but has no driver.
Warning: Wire WB_InterConnect.\io_wbm_m2s_sel [2] is used but has no driver.
Warning: Wire WB_InterConnect.\io_wbm_m2s_sel [1] is used but has no driver.
Warning: Wire WB_InterConnect.\io_wbm_m2s_sel [0] is used but has no driver.
Warning: Wire WB_InterConnect.\io_wbm_m2s_data [31] is used but has no driver.
Warning: Wire WB_InterConnect.\io_wbm_m2s_data [30] is used but has no driver.
Warning: Wire WB_InterConnect.\io_wbm_m2s_data [29] is used but has no driver.
Warning: Wire WB_InterConnect.\io_wbm_m2s_data [28] is used but has no driver.
Warning: Wire WB_InterConnect.\io_wbm_m2s_data [27] is used but has no driver.
Warning: Wire WB_InterConnect.\io_wbm_m2s_data [26] is used but has no driver.
Warning: Wire WB_InterConnect.\io_wbm_m2s_data [25] is used but has no driver.
Warning: Wire WB_InterConnect.\io_wbm_m2s_data [24] is used but has no driver.
Warning: Wire WB_InterConnect.\io_wbm_m2s_data [23] is used but has no driver.
Warning: Wire WB_InterConnect.\io_wbm_m2s_data [22] is used but has no driver.
Warning: Wire WB_InterConnect.\io_wbm_m2s_data [21] is used but has no driver.
Warning: Wire WB_InterConnect.\io_wbm_m2s_data [20] is used but has no driver.
Warning: Wire WB_InterConnect.\io_wbm_m2s_data [19] is used but has no driver.
Warning: Wire WB_InterConnect.\io_wbm_m2s_data [18] is used but has no driver.
Warning: Wire WB_InterConnect.\io_wbm_m2s_data [17] is used but has no driver.
Warning: Wire WB_InterConnect.\io_wbm_m2s_data [16] is used but has no driver.
Warning: Wire WB_InterConnect.\io_wbm_m2s_data [15] is used but has no driver.
Warning: Wire WB_InterConnect.\io_wbm_m2s_data [14] is used but has no driver.
Warning: Wire WB_InterConnect.\io_wbm_m2s_data [13] is used but has no driver.
Warning: Wire WB_InterConnect.\io_wbm_m2s_data [12] is used but has no driver.
Warning: Wire WB_InterConnect.\io_wbm_m2s_data [11] is used but has no driver.
Warning: Wire WB_InterConnect.\io_wbm_m2s_data [10] is used but has no driver.
Warning: Wire WB_InterConnect.\io_wbm_m2s_data [9] is used but has no driver.
Warning: Wire WB_InterConnect.\io_wbm_m2s_data [8] is used but has no driver.
Warning: Wire WB_InterConnect.\io_wbm_m2s_data [7] is used but has no driver.
Warning: Wire WB_InterConnect.\io_wbm_m2s_data [6] is used but has no driver.
Warning: Wire WB_InterConnect.\io_wbm_m2s_data [5] is used but has no driver.
Warning: Wire WB_InterConnect.\io_wbm_m2s_data [4] is used but has no driver.
Warning: Wire WB_InterConnect.\io_wbm_m2s_data [3] is used but has no driver.
Warning: Wire WB_InterConnect.\io_wbm_m2s_data [2] is used but has no driver.
Warning: Wire WB_InterConnect.\io_wbm_m2s_data [1] is used but has no driver.
Warning: Wire WB_InterConnect.\io_wbm_m2s_data [0] is used but has no driver.
Warning: Wire WB_InterConnect.\io_wbm_m2s_addr [15] is used but has no driver.
Warning: Wire WB_InterConnect.\io_wbm_m2s_addr [14] is used but has no driver.
Warning: Wire WB_InterConnect.\io_wbm_m2s_addr [13] is used but has no driver.
Warning: Wire WB_InterConnect.\io_wbm_m2s_addr [12] is used but has no driver.
Warning: Wire WB_InterConnect.\io_wbm_m2s_addr [11] is used but has no driver.
Warning: Wire WB_InterConnect.\io_wbm_m2s_addr [10] is used but has no driver.
Warning: Wire WB_InterConnect.\io_wbm_m2s_addr [9] is used but has no driver.
Warning: Wire WB_InterConnect.\io_wbm_m2s_addr [8] is used but has no driver.
Warning: Wire WB_InterConnect.\io_wbm_m2s_addr [7] is used but has no driver.
Warning: Wire WB_InterConnect.\io_wbm_m2s_addr [6] is used but has no driver.
Warning: Wire WB_InterConnect.\io_wbm_m2s_addr [5] is used but has no driver.
Warning: Wire WB_InterConnect.\io_wbm_m2s_addr [4] is used but has no driver.
Warning: Wire WB_InterConnect.\io_wbm_m2s_addr [3] is used but has no driver.
Warning: Wire WB_InterConnect.\io_wbm_m2s_addr [2] is used but has no driver.
Warning: Wire WB_InterConnect.\io_wbm_m2s_addr [1] is used but has no driver.
Warning: Wire WB_InterConnect.\io_wbm_m2s_addr [0] is used but has no driver.
Warning: Wire WB_InterConnect.\io_uart_txen is used but has no driver.
Warning: Wire WB_InterConnect.\io_uart_tx is used but has no driver.
Warning: Wire WB_InterConnect.\io_uart_irq is used but has no driver.
Warning: Wire WB_InterConnect.\io_spi_mosi_en is used but has no driver.
Warning: Wire WB_InterConnect.\io_spi_mosi is used but has no driver.
Warning: Wire WB_InterConnect.\io_spi_irq is used but has no driver.
Warning: Wire WB_InterConnect.\io_spi_cs_en is used but has no driver.
Warning: Wire WB_InterConnect.\io_spi_cs is used but has no driver.
Warning: Wire WB_InterConnect.\io_spi_clk_en is used but has no driver.
Warning: Wire WB_InterConnect.\io_spi_clk is used but has no driver.
Warning: Wire WB_InterConnect.\io_motor_addr_sel is used but has no driver.
Warning: Wire WB_InterConnect.\io_imem_io_wr_en is used but has no driver.
Warning: Wire WB_InterConnect.\io_imem_io_wdata [31] is used but has no driver.
Warning: Wire WB_InterConnect.\io_imem_io_wdata [30] is used but has no driver.
Warning: Wire WB_InterConnect.\io_imem_io_wdata [29] is used but has no driver.
Warning: Wire WB_InterConnect.\io_imem_io_wdata [28] is used but has no driver.
Warning: Wire WB_InterConnect.\io_imem_io_wdata [27] is used but has no driver.
Warning: Wire WB_InterConnect.\io_imem_io_wdata [26] is used but has no driver.
Warning: Wire WB_InterConnect.\io_imem_io_wdata [25] is used but has no driver.
Warning: Wire WB_InterConnect.\io_imem_io_wdata [24] is used but has no driver.
Warning: Wire WB_InterConnect.\io_imem_io_wdata [23] is used but has no driver.
Warning: Wire WB_InterConnect.\io_imem_io_wdata [22] is used but has no driver.
Warning: Wire WB_InterConnect.\io_imem_io_wdata [21] is used but has no driver.
Warning: Wire WB_InterConnect.\io_imem_io_wdata [20] is used but has no driver.
Warning: Wire WB_InterConnect.\io_imem_io_wdata [19] is used but has no driver.
Warning: Wire WB_InterConnect.\io_imem_io_wdata [18] is used but has no driver.
Warning: Wire WB_InterConnect.\io_imem_io_wdata [17] is used but has no driver.
Warning: Wire WB_InterConnect.\io_imem_io_wdata [16] is used but has no driver.
Warning: Wire WB_InterConnect.\io_imem_io_wdata [15] is used but has no driver.
Warning: Wire WB_InterConnect.\io_imem_io_wdata [14] is used but has no driver.
Warning: Wire WB_InterConnect.\io_imem_io_wdata [13] is used but has no driver.
Warning: Wire WB_InterConnect.\io_imem_io_wdata [12] is used but has no driver.
Warning: Wire WB_InterConnect.\io_imem_io_wdata [11] is used but has no driver.
Warning: Wire WB_InterConnect.\io_imem_io_wdata [10] is used but has no driver.
Warning: Wire WB_InterConnect.\io_imem_io_wdata [9] is used but has no driver.
Warning: Wire WB_InterConnect.\io_imem_io_wdata [8] is used but has no driver.
Warning: Wire WB_InterConnect.\io_imem_io_wdata [7] is used but has no driver.
Warning: Wire WB_InterConnect.\io_imem_io_wdata [6] is used but has no driver.
Warning: Wire WB_InterConnect.\io_imem_io_wdata [5] is used but has no driver.
Warning: Wire WB_InterConnect.\io_imem_io_wdata [4] is used but has no driver.
Warning: Wire WB_InterConnect.\io_imem_io_wdata [3] is used but has no driver.
Warning: Wire WB_InterConnect.\io_imem_io_wdata [2] is used but has no driver.
Warning: Wire WB_InterConnect.\io_imem_io_wdata [1] is used but has no driver.
Warning: Wire WB_InterConnect.\io_imem_io_wdata [0] is used but has no driver.
Warning: Wire WB_InterConnect.\io_imem_io_st_type [3] is used but has no driver.
Warning: Wire WB_InterConnect.\io_imem_io_st_type [2] is used but has no driver.
Warning: Wire WB_InterConnect.\io_imem_io_st_type [1] is used but has no driver.
Warning: Wire WB_InterConnect.\io_imem_io_st_type [0] is used but has no driver.
Warning: Wire WB_InterConnect.\io_imem_io_cs is used but has no driver.
Warning: Wire WB_InterConnect.\io_imem_io_addr [8] is used but has no driver.
Warning: Wire WB_InterConnect.\io_imem_io_addr [7] is used but has no driver.
Warning: Wire WB_InterConnect.\io_imem_io_addr [6] is used but has no driver.
Warning: Wire WB_InterConnect.\io_imem_io_addr [5] is used but has no driver.
Warning: Wire WB_InterConnect.\io_imem_io_addr [4] is used but has no driver.
Warning: Wire WB_InterConnect.\io_imem_io_addr [3] is used but has no driver.
Warning: Wire WB_InterConnect.\io_imem_io_addr [2] is used but has no driver.
Warning: Wire WB_InterConnect.\io_imem_io_addr [1] is used but has no driver.
Warning: Wire WB_InterConnect.\io_imem_io_addr [0] is used but has no driver.
Warning: Wire WB_InterConnect.\io_ibus_valid is used but has no driver.
Warning: Wire WB_InterConnect.\io_ibus_inst [31] is used but has no driver.
Warning: Wire WB_InterConnect.\io_ibus_inst [30] is used but has no driver.
Warning: Wire WB_InterConnect.\io_ibus_inst [29] is used but has no driver.
Warning: Wire WB_InterConnect.\io_ibus_inst [28] is used but has no driver.
Warning: Wire WB_InterConnect.\io_ibus_inst [27] is used but has no driver.
Warning: Wire WB_InterConnect.\io_ibus_inst [26] is used but has no driver.
Warning: Wire WB_InterConnect.\io_ibus_inst [25] is used but has no driver.
Warning: Wire WB_InterConnect.\io_ibus_inst [24] is used but has no driver.
Warning: Wire WB_InterConnect.\io_ibus_inst [23] is used but has no driver.
Warning: Wire WB_InterConnect.\io_ibus_inst [22] is used but has no driver.
Warning: Wire WB_InterConnect.\io_ibus_inst [21] is used but has no driver.
Warning: Wire WB_InterConnect.\io_ibus_inst [20] is used but has no driver.
Warning: Wire WB_InterConnect.\io_ibus_inst [19] is used but has no driver.
Warning: Wire WB_InterConnect.\io_ibus_inst [18] is used but has no driver.
Warning: Wire WB_InterConnect.\io_ibus_inst [17] is used but has no driver.
Warning: Wire WB_InterConnect.\io_ibus_inst [16] is used but has no driver.
Warning: Wire WB_InterConnect.\io_ibus_inst [15] is used but has no driver.
Warning: Wire WB_InterConnect.\io_ibus_inst [14] is used but has no driver.
Warning: Wire WB_InterConnect.\io_ibus_inst [13] is used but has no driver.
Warning: Wire WB_InterConnect.\io_ibus_inst [12] is used but has no driver.
Warning: Wire WB_InterConnect.\io_ibus_inst [11] is used but has no driver.
Warning: Wire WB_InterConnect.\io_ibus_inst [10] is used but has no driver.
Warning: Wire WB_InterConnect.\io_ibus_inst [9] is used but has no driver.
Warning: Wire WB_InterConnect.\io_ibus_inst [8] is used but has no driver.
Warning: Wire WB_InterConnect.\io_ibus_inst [7] is used but has no driver.
Warning: Wire WB_InterConnect.\io_ibus_inst [6] is used but has no driver.
Warning: Wire WB_InterConnect.\io_ibus_inst [5] is used but has no driver.
Warning: Wire WB_InterConnect.\io_ibus_inst [4] is used but has no driver.
Warning: Wire WB_InterConnect.\io_ibus_inst [3] is used but has no driver.
Warning: Wire WB_InterConnect.\io_ibus_inst [2] is used but has no driver.
Warning: Wire WB_InterConnect.\io_ibus_inst [1] is used but has no driver.
Warning: Wire WB_InterConnect.\io_ibus_inst [0] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dmem_io_wr_en is used but has no driver.
Warning: Wire WB_InterConnect.\io_dmem_io_wdata [31] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dmem_io_wdata [30] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dmem_io_wdata [29] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dmem_io_wdata [28] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dmem_io_wdata [27] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dmem_io_wdata [26] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dmem_io_wdata [25] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dmem_io_wdata [24] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dmem_io_wdata [23] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dmem_io_wdata [22] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dmem_io_wdata [21] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dmem_io_wdata [20] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dmem_io_wdata [19] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dmem_io_wdata [18] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dmem_io_wdata [17] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dmem_io_wdata [16] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dmem_io_wdata [15] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dmem_io_wdata [14] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dmem_io_wdata [13] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dmem_io_wdata [12] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dmem_io_wdata [11] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dmem_io_wdata [10] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dmem_io_wdata [9] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dmem_io_wdata [8] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dmem_io_wdata [7] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dmem_io_wdata [6] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dmem_io_wdata [5] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dmem_io_wdata [4] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dmem_io_wdata [3] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dmem_io_wdata [2] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dmem_io_wdata [1] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dmem_io_wdata [0] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dmem_io_st_type [3] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dmem_io_st_type [2] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dmem_io_st_type [1] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dmem_io_st_type [0] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dmem_io_cs is used but has no driver.
Warning: Wire WB_InterConnect.\io_dmem_io_addr [7] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dmem_io_addr [6] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dmem_io_addr [5] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dmem_io_addr [4] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dmem_io_addr [3] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dmem_io_addr [2] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dmem_io_addr [1] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dmem_io_addr [0] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dbus_valid is used but has no driver.
Warning: Wire WB_InterConnect.\io_dbus_rdata [31] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dbus_rdata [30] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dbus_rdata [29] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dbus_rdata [28] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dbus_rdata [27] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dbus_rdata [26] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dbus_rdata [25] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dbus_rdata [24] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dbus_rdata [23] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dbus_rdata [22] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dbus_rdata [21] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dbus_rdata [20] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dbus_rdata [19] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dbus_rdata [18] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dbus_rdata [17] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dbus_rdata [16] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dbus_rdata [15] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dbus_rdata [14] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dbus_rdata [13] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dbus_rdata [12] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dbus_rdata [11] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dbus_rdata [10] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dbus_rdata [9] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dbus_rdata [8] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dbus_rdata [7] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dbus_rdata [6] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dbus_rdata [5] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dbus_rdata [4] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dbus_rdata [3] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dbus_rdata [2] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dbus_rdata [1] is used but has no driver.
Warning: Wire WB_InterConnect.\io_dbus_rdata [0] is used but has no driver.
Found and reported 224 problems.

25. Printing statistics.

=== WB_InterConnect ===

   Number of wires:               2574
   Number of wire bits:           2957
   Number of public wires:         276
   Number of public wire bits:     659
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:               2753
     sky130_fd_sc_hd__a2111o_2      19
     sky130_fd_sc_hd__a2111oi_2      1
     sky130_fd_sc_hd__a211o_2       21
     sky130_fd_sc_hd__a211oi_2       3
     sky130_fd_sc_hd__a21bo_2        3
     sky130_fd_sc_hd__a21boi_2       3
     sky130_fd_sc_hd__a21o_2        41
     sky130_fd_sc_hd__a21oi_2       57
     sky130_fd_sc_hd__a221o_2       12
     sky130_fd_sc_hd__a221oi_2       3
     sky130_fd_sc_hd__a22o_2        92
     sky130_fd_sc_hd__a2bb2o_2      22
     sky130_fd_sc_hd__a311o_2        5
     sky130_fd_sc_hd__a311oi_2       1
     sky130_fd_sc_hd__a31o_2        30
     sky130_fd_sc_hd__a31oi_2        3
     sky130_fd_sc_hd__a32o_2        14
     sky130_fd_sc_hd__and2_2        97
     sky130_fd_sc_hd__and2b_2        7
     sky130_fd_sc_hd__and3_2        24
     sky130_fd_sc_hd__and3b_2       10
     sky130_fd_sc_hd__and4_2         5
     sky130_fd_sc_hd__and4b_2        1
     sky130_fd_sc_hd__and4bb_2       4
     sky130_fd_sc_hd__buf_1        541
     sky130_fd_sc_hd__buf_2        133
     sky130_fd_sc_hd__dfxtp_2      236
     sky130_fd_sc_hd__inv_2         41
     sky130_fd_sc_hd__mux2_2       149
     sky130_fd_sc_hd__nand2_2       89
     sky130_fd_sc_hd__nand2b_2       1
     sky130_fd_sc_hd__nand3b_2       1
     sky130_fd_sc_hd__nand4b_2       4
     sky130_fd_sc_hd__nor2_2       275
     sky130_fd_sc_hd__nor2b_2        1
     sky130_fd_sc_hd__nor3_2         7
     sky130_fd_sc_hd__nor3b_2        2
     sky130_fd_sc_hd__nor4_2         4
     sky130_fd_sc_hd__nor4b_2        1
     sky130_fd_sc_hd__o2111a_2       2
     sky130_fd_sc_hd__o211a_2       61
     sky130_fd_sc_hd__o21a_2        26
     sky130_fd_sc_hd__o21ai_2       32
     sky130_fd_sc_hd__o21ba_2       10
     sky130_fd_sc_hd__o21bai_2       4
     sky130_fd_sc_hd__o221a_2       18
     sky130_fd_sc_hd__o221ai_2       1
     sky130_fd_sc_hd__o22a_2        11
     sky130_fd_sc_hd__o22ai_2        4
     sky130_fd_sc_hd__o2bb2a_2      26
     sky130_fd_sc_hd__o311a_2        5
     sky130_fd_sc_hd__o31a_2         5
     sky130_fd_sc_hd__o31ai_2        3
     sky130_fd_sc_hd__o41a_2         1
     sky130_fd_sc_hd__or2_2        167
     sky130_fd_sc_hd__or2b_2        10
     sky130_fd_sc_hd__or3_2        111
     sky130_fd_sc_hd__or3b_2        15
     sky130_fd_sc_hd__or4_2        234
     sky130_fd_sc_hd__or4b_2        28
     sky130_fd_sc_hd__or4bb_2        7
     sky130_fd_sc_hd__xnor2_2        2
     sky130_fd_sc_hd__xor2_2         7

   Chip area for module '\WB_InterConnect': 23332.377600

26. Executing Verilog backend.
Dumping module `\WB_InterConnect'.

Warnings: 224 unique messages, 224 total
End of script. Logfile hash: 0326f7d303, CPU: user 14.92s system 0.09s, MEM: 85.13 MB peak
Yosys 0.12+45 (git sha1 UNKNOWN, gcc 8.3.1 -fPIC -Os)
Time spent: 47% 2x abc (13 sec), 12% 10x opt_reduce (3 sec), ...