OpenROAD 8d53e9b018dec98fa63e907ddeb6c5406f035361 
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/merged_unpadded.lef
[INFO ODB-0223]     Created 13 technology layers
[INFO ODB-0224]     Created 25 technology vias
[INFO ODB-0225]     Created 441 library cells
[INFO ODB-0226] Finished LEF file:  /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/merged_unpadded.lef
[INFO ODB-0127] Reading DEF file: /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/routing/19-global.def
[INFO ODB-0128] Design: WB_InterConnect
[INFO ODB-0094] 		Created 100000 Insts
[INFO ODB-0130]     Created 430 pins.
[INFO ODB-0131]     Created 123497 components and 472337 component-terminals.
[INFO ODB-0132]     Created 2 special nets and 460556 connections.
[INFO ODB-0133]     Created 3381 nets and 11781 connections.
[INFO ODB-0134] Finished DEF file: /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/routing/19-global.def
[INFO ORD-0030] Using 2 thread(s).
[INFO DRT-0149] Reading tech and libs.

Units:                1000
Number of layers:     13
Number of macros:     441
Number of vias:       25
Number of viarulegen: 25

[INFO DRT-0150] Reading design.

Design:                   WB_InterConnect
Die area:                 ( 0 0 ) ( 1100000 1100000 )
Number of track patterns: 12
Number of DEF vias:       3
Number of components:     123497
Number of terminals:      430
Number of snets:          2
Number of nets:           3381

[INFO DRT-0167] List of default vias:
  Layer mcon
    default via: L1M1_PR
  Layer via
    default via: M1M2_PR
  Layer via2
    default via: M2M3_PR
  Layer via3
    default via: M3M4_PR
  Layer via4
    default via: M4M5_PR
[INFO DRT-0162] Library cell analysis.
[INFO DRT-0163] Instance analysis.
  Complete 10000 instances.
  Complete 20000 instances.
  Complete 30000 instances.
  Complete 40000 instances.
  Complete 50000 instances.
  Complete 60000 instances.
  Complete 70000 instances.
  Complete 80000 instances.
  Complete 90000 instances.
  Complete 100000 instances.
[INFO DRT-0164] Number of unique instances = 342.
[INFO DRT-0168] Init region query.
[INFO DRT-0018]   Complete 10000 insts.
[INFO DRT-0018]   Complete 20000 insts.
[INFO DRT-0018]   Complete 30000 insts.
[INFO DRT-0018]   Complete 40000 insts.
[INFO DRT-0018]   Complete 50000 insts.
[INFO DRT-0018]   Complete 60000 insts.
[INFO DRT-0018]   Complete 70000 insts.
[INFO DRT-0018]   Complete 80000 insts.
[INFO DRT-0018]   Complete 90000 insts.
[INFO DRT-0019]   Complete 100000 insts.
[INFO DRT-0024]   Complete FR_MASTERSLICE.
[INFO DRT-0024]   Complete FR_VIA.
[INFO DRT-0024]   Complete li1.
[INFO DRT-0024]   Complete mcon.
[INFO DRT-0024]   Complete met1.
[INFO DRT-0024]   Complete via.
[INFO DRT-0024]   Complete met2.
[INFO DRT-0024]   Complete via2.
[INFO DRT-0024]   Complete met3.
[INFO DRT-0024]   Complete via3.
[INFO DRT-0024]   Complete met4.
[INFO DRT-0024]   Complete via4.
[INFO DRT-0024]   Complete met5.
[INFO DRT-0033] FR_MASTERSLICE shape region query size = 0.
[INFO DRT-0033] FR_VIA shape region query size = 0.
[INFO DRT-0033] li1 shape region query size = 689675.
[INFO DRT-0033] mcon shape region query size = 1876160.
[INFO DRT-0033] met1 shape region query size = 253659.
[INFO DRT-0033] via shape region query size = 13895.
[INFO DRT-0033] met2 shape region query size = 5679.
[INFO DRT-0033] via2 shape region query size = 11116.
[INFO DRT-0033] met3 shape region query size = 5865.
[INFO DRT-0033] via3 shape region query size = 11116.
[INFO DRT-0033] met4 shape region query size = 2807.
[INFO DRT-0033] via4 shape region query size = 0.
[INFO DRT-0033] met5 shape region query size = 0.
[INFO DRT-0165] Start pin access.
[INFO DRT-0076]   Complete 100 pins.
[INFO DRT-0076]   Complete 200 pins.
[INFO DRT-0076]   Complete 300 pins.
[INFO DRT-0076]   Complete 400 pins.
[INFO DRT-0076]   Complete 500 pins.
[INFO DRT-0076]   Complete 600 pins.
[INFO DRT-0076]   Complete 700 pins.
[INFO DRT-0076]   Complete 800 pins.
[INFO DRT-0076]   Complete 900 pins.
[INFO DRT-0077]   Complete 1000 pins.
[INFO DRT-0078]   Complete 1264 pins.
[INFO DRT-0079]   Complete 100 unique inst patterns.
[INFO DRT-0079]   Complete 200 unique inst patterns.
[INFO DRT-0079]   Complete 300 unique inst patterns.
[INFO DRT-0081]   Complete 336 unique inst patterns.
[INFO DRT-0082]   Complete 1000 groups.
[INFO DRT-0082]   Complete 2000 groups.
[INFO DRT-0082]   Complete 3000 groups.
[INFO DRT-0082]   Complete 4000 groups.
[INFO DRT-0084]   Complete 4687 groups.
#scanned instances     = 123497
#unique  instances     = 342
#stdCellGenAp          = 9553
#stdCellValidPlanarAp  = 66
#stdCellValidViaAp     = 7350
#stdCellPinNoAp        = 0
#stdCellPinCnt         = 11781
#instTermValidViaApCnt = 0
#macroGenAp            = 0
#macroValidPlanarAp    = 0
#macroValidViaAp       = 0
#macroNoAp             = 0
[INFO DRT-0166] Complete pin access.
[INFO DRT-0267] cpu time = 00:00:13, elapsed time = 00:00:06, memory = 524.04 (MB), peak = 589.43 (MB)
[INFO DRT-0151] Reading guide.

Number of guides:     30268

[INFO DRT-0169] Post process guides.
[INFO DRT-0176] GCELLGRID X 0 DO 159 STEP 6900 ;
[INFO DRT-0177] GCELLGRID Y 0 DO 159 STEP 6900 ;
[INFO DRT-0026]   Complete 10000 origin guides.
[INFO DRT-0026]   Complete 20000 origin guides.
[INFO DRT-0026]   Complete 30000 origin guides.
[INFO DRT-0028]   Complete FR_MASTERSLICE.
[INFO DRT-0028]   Complete FR_VIA.
[INFO DRT-0028]   Complete li1.
[INFO DRT-0028]   Complete mcon.
[INFO DRT-0028]   Complete met1.
[INFO DRT-0028]   Complete via.
[INFO DRT-0028]   Complete met2.
[INFO DRT-0028]   Complete via2.
[INFO DRT-0028]   Complete met3.
[INFO DRT-0028]   Complete via3.
[INFO DRT-0028]   Complete met4.
[INFO DRT-0028]   Complete via4.
[INFO DRT-0028]   Complete met5.
[INFO DRT-0178] Init guide query.
[INFO DRT-0035]   Complete FR_MASTERSLICE (guide).
[INFO DRT-0035]   Complete FR_VIA (guide).
[INFO DRT-0035]   Complete li1 (guide).
[INFO DRT-0035]   Complete mcon (guide).
[INFO DRT-0035]   Complete met1 (guide).
[INFO DRT-0035]   Complete via (guide).
[INFO DRT-0035]   Complete met2 (guide).
[INFO DRT-0035]   Complete via2 (guide).
[INFO DRT-0035]   Complete met3 (guide).
[INFO DRT-0035]   Complete via3 (guide).
[INFO DRT-0035]   Complete met4 (guide).
[INFO DRT-0035]   Complete via4 (guide).
[INFO DRT-0035]   Complete met5 (guide).
[INFO DRT-0036] FR_MASTERSLICE guide region query size = 0.
[INFO DRT-0036] FR_VIA guide region query size = 0.
[INFO DRT-0036] li1 guide region query size = 9717.
[INFO DRT-0036] mcon guide region query size = 0.
[INFO DRT-0036] met1 guide region query size = 8414.
[INFO DRT-0036] via guide region query size = 0.
[INFO DRT-0036] met2 guide region query size = 5579.
[INFO DRT-0036] via2 guide region query size = 0.
[INFO DRT-0036] met3 guide region query size = 1762.
[INFO DRT-0036] via3 guide region query size = 0.
[INFO DRT-0036] met4 guide region query size = 540.
[INFO DRT-0036] via4 guide region query size = 0.
[INFO DRT-0036] met5 guide region query size = 0.
[INFO DRT-0179] Init gr pin query.
[INFO DRT-0185] Post process initialize RPin region query.
[INFO DRT-0181] Start track assignment.
[INFO DRT-0184] Done with 15836 vertical wires in 4 frboxes and 10176 horizontal wires in 4 frboxes.
[INFO DRT-0186] Done with 2856 vertical wires in 4 frboxes and 3120 horizontal wires in 4 frboxes.
[INFO DRT-0182] Complete track assignment.
[INFO DRT-0267] cpu time = 00:00:08, elapsed time = 00:00:04, memory = 734.71 (MB), peak = 979.48 (MB)
[INFO DRT-0187] Start routing data preparation.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 734.71 (MB), peak = 979.48 (MB)
[INFO DRT-0194] Start detail routing.
[INFO DRT-0195] Start 0th optimization iteration.
    Completing 10% with 0 violations.
    elapsed time = 00:00:13, memory = 1951.31 (MB).
    Completing 20% with 0 violations.
    elapsed time = 00:00:16, memory = 3203.42 (MB).
    Completing 30% with 631 violations.
    elapsed time = 00:00:27, memory = 3503.58 (MB).
    Completing 40% with 631 violations.
    elapsed time = 00:00:38, memory = 4009.28 (MB).
    Completing 50% with 631 violations.
    elapsed time = 00:00:40, memory = 4630.57 (MB).
    Completing 60% with 1421 violations.
    elapsed time = 00:00:49, memory = 3376.51 (MB).
    Completing 70% with 1421 violations.
    elapsed time = 00:00:53, memory = 3376.51 (MB).
    Completing 80% with 1835 violations.
    elapsed time = 00:01:18, memory = 4058.54 (MB).
    Completing 90% with 1835 violations.
    elapsed time = 00:01:20, memory = 4508.42 (MB).
    Completing 100% with 2424 violations.
    elapsed time = 00:01:24, memory = 5111.57 (MB).
[INFO DRT-0199]   Number of violations = 3632.
[INFO DRT-0267] cpu time = 00:02:39, elapsed time = 00:01:24, memory = 5111.57 (MB), peak = 5124.29 (MB)
Total wire length = 409754 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 173330 um.
Total wire length on LAYER met2 = 154383 um.
Total wire length on LAYER met3 = 51365 um.
Total wire length on LAYER met4 = 30675 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 28943.
Up-via summary (total 28943):.

------------------------
 FR_MASTERSLICE        0
            li1    11777
           met1    13695
           met2     2485
           met3      986
           met4        0
------------------------
                   28943


[INFO DRT-0195] Start 1st optimization iteration.
    Completing 10% with 3632 violations.
    elapsed time = 00:00:13, memory = 4793.62 (MB).
    Completing 20% with 3632 violations.
    elapsed time = 00:00:18, memory = 6048.64 (MB).
    Completing 30% with 3203 violations.
    elapsed time = 00:00:23, memory = 4088.86 (MB).
    Completing 40% with 3203 violations.
    elapsed time = 00:00:35, memory = 5048.44 (MB).
    Completing 50% with 3203 violations.
    elapsed time = 00:00:39, memory = 6364.38 (MB).
    Completing 60% with 2595 violations.
    elapsed time = 00:00:48, memory = 4089.05 (MB).
    Completing 70% with 2595 violations.
    elapsed time = 00:00:52, memory = 4089.05 (MB).
    Completing 80% with 2114 violations.
    elapsed time = 00:01:09, memory = 4089.09 (MB).
    Completing 90% with 2114 violations.
    elapsed time = 00:01:13, memory = 4708.38 (MB).
    Completing 100% with 1734 violations.
    elapsed time = 00:01:16, memory = 5330.53 (MB).
[INFO DRT-0199]   Number of violations = 1739.
[INFO DRT-0267] cpu time = 00:02:26, elapsed time = 00:01:16, memory = 5330.53 (MB), peak = 6495.17 (MB)
Total wire length = 408304 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 173067 um.
Total wire length on LAYER met2 = 153591 um.
Total wire length on LAYER met3 = 51164 um.
Total wire length on LAYER met4 = 30482 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 28790.
Up-via summary (total 28790):.

------------------------
 FR_MASTERSLICE        0
            li1    11769
           met1    13564
           met2     2468
           met3      989
           met4        0
------------------------
                   28790


[INFO DRT-0195] Start 2nd optimization iteration.
    Completing 10% with 1739 violations.
    elapsed time = 00:00:09, memory = 4089.12 (MB).
    Completing 20% with 1739 violations.
    elapsed time = 00:00:09, memory = 4089.12 (MB).
    Completing 30% with 1751 violations.
    elapsed time = 00:00:16, memory = 4089.12 (MB).
    Completing 40% with 1751 violations.
    elapsed time = 00:00:18, memory = 4089.12 (MB).
    Completing 50% with 1751 violations.
    elapsed time = 00:00:31, memory = 4089.12 (MB).
    Completing 60% with 1594 violations.
    elapsed time = 00:00:44, memory = 4089.12 (MB).
    Completing 70% with 1594 violations.
    elapsed time = 00:00:44, memory = 4089.12 (MB).
    Completing 80% with 1499 violations.
    elapsed time = 00:00:55, memory = 4089.12 (MB).
    Completing 90% with 1499 violations.
    elapsed time = 00:00:56, memory = 4089.12 (MB).
    Completing 100% with 1320 violations.
    elapsed time = 00:00:56, memory = 4089.12 (MB).
[INFO DRT-0199]   Number of violations = 1320.
[INFO DRT-0267] cpu time = 00:01:35, elapsed time = 00:00:57, memory = 4089.12 (MB), peak = 6495.17 (MB)
Total wire length = 407133 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 172524 um.
Total wire length on LAYER met2 = 153219 um.
Total wire length on LAYER met3 = 51086 um.
Total wire length on LAYER met4 = 30303 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 28513.
Up-via summary (total 28513):.

------------------------
 FR_MASTERSLICE        0
            li1    11769
           met1    13334
           met2     2461
           met3      949
           met4        0
------------------------
                   28513


[INFO DRT-0195] Start 3rd optimization iteration.
    Completing 10% with 1320 violations.
    elapsed time = 00:00:19, memory = 4089.12 (MB).
    Completing 20% with 1320 violations.
    elapsed time = 00:00:19, memory = 4089.12 (MB).
    Completing 30% with 1157 violations.
    elapsed time = 00:00:27, memory = 4089.12 (MB).
    Completing 40% with 1157 violations.
    elapsed time = 00:00:35, memory = 4089.12 (MB).
    Completing 50% with 1157 violations.
    elapsed time = 00:00:35, memory = 4089.12 (MB).
    Completing 60% with 1103 violations.
    elapsed time = 00:00:54, memory = 4089.12 (MB).
    Completing 70% with 1103 violations.
    elapsed time = 00:00:54, memory = 4089.12 (MB).
    Completing 80% with 904 violations.
    elapsed time = 00:01:16, memory = 4089.12 (MB).
    Completing 90% with 904 violations.
    elapsed time = 00:01:16, memory = 4089.12 (MB).
    Completing 100% with 624 violations.
    elapsed time = 00:01:23, memory = 4089.12 (MB).
[INFO DRT-0199]   Number of violations = 624.
[INFO DRT-0267] cpu time = 00:02:18, elapsed time = 00:01:24, memory = 4089.12 (MB), peak = 6495.17 (MB)
Total wire length = 406991 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 171143 um.
Total wire length on LAYER met2 = 152727 um.
Total wire length on LAYER met3 = 52149 um.
Total wire length on LAYER met4 = 30970 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 29005.
Up-via summary (total 29005):.

------------------------
 FR_MASTERSLICE        0
            li1    11769
           met1    13487
           met2     2709
           met3     1040
           met4        0
------------------------
                   29005


[INFO DRT-0195] Start 4th optimization iteration.
    Completing 10% with 624 violations.
    elapsed time = 00:00:03, memory = 4089.12 (MB).
    Completing 20% with 624 violations.
    elapsed time = 00:00:03, memory = 4089.12 (MB).
    Completing 30% with 611 violations.
    elapsed time = 00:00:22, memory = 4089.12 (MB).
    Completing 40% with 611 violations.
    elapsed time = 00:00:27, memory = 4089.12 (MB).
    Completing 50% with 611 violations.
    elapsed time = 00:00:27, memory = 4089.12 (MB).
    Completing 60% with 492 violations.
    elapsed time = 00:00:40, memory = 4089.12 (MB).
    Completing 70% with 492 violations.
    elapsed time = 00:00:40, memory = 4089.12 (MB).
    Completing 80% with 484 violations.
    elapsed time = 00:00:49, memory = 4089.12 (MB).
    Completing 90% with 484 violations.
    elapsed time = 00:00:50, memory = 4089.12 (MB).
    Completing 100% with 447 violations.
    elapsed time = 00:00:59, memory = 4089.12 (MB).
[INFO DRT-0199]   Number of violations = 447.
[INFO DRT-0267] cpu time = 00:01:12, elapsed time = 00:00:59, memory = 4089.12 (MB), peak = 6495.17 (MB)
Total wire length = 406989 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 170917 um.
Total wire length on LAYER met2 = 152554 um.
Total wire length on LAYER met3 = 52340 um.
Total wire length on LAYER met4 = 31177 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 29144.
Up-via summary (total 29144):.

------------------------
 FR_MASTERSLICE        0
            li1    11769
           met1    13545
           met2     2759
           met3     1071
           met4        0
------------------------
                   29144


[INFO DRT-0195] Start 5th optimization iteration.
    Completing 10% with 447 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 20% with 447 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 30% with 446 violations.
    elapsed time = 00:00:15, memory = 4089.12 (MB).
    Completing 40% with 446 violations.
    elapsed time = 00:00:16, memory = 4089.12 (MB).
    Completing 50% with 446 violations.
    elapsed time = 00:00:16, memory = 4089.12 (MB).
    Completing 60% with 388 violations.
    elapsed time = 00:00:26, memory = 4089.12 (MB).
    Completing 70% with 388 violations.
    elapsed time = 00:00:26, memory = 4089.12 (MB).
    Completing 80% with 340 violations.
    elapsed time = 00:00:41, memory = 4089.12 (MB).
    Completing 90% with 340 violations.
    elapsed time = 00:00:42, memory = 4089.12 (MB).
    Completing 100% with 284 violations.
    elapsed time = 00:00:52, memory = 4089.12 (MB).
[INFO DRT-0199]   Number of violations = 284.
[INFO DRT-0267] cpu time = 00:00:55, elapsed time = 00:00:52, memory = 4089.12 (MB), peak = 6495.17 (MB)
Total wire length = 406861 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 170836 um.
Total wire length on LAYER met2 = 152536 um.
Total wire length on LAYER met3 = 52311 um.
Total wire length on LAYER met4 = 31177 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 29143.
Up-via summary (total 29143):.

------------------------
 FR_MASTERSLICE        0
            li1    11769
           met1    13561
           met2     2758
           met3     1055
           met4        0
------------------------
                   29143


[INFO DRT-0195] Start 6th optimization iteration.
    Completing 10% with 284 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 20% with 284 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 30% with 252 violations.
    elapsed time = 00:00:14, memory = 4089.12 (MB).
    Completing 40% with 252 violations.
    elapsed time = 00:00:14, memory = 4089.12 (MB).
    Completing 50% with 252 violations.
    elapsed time = 00:00:36, memory = 4089.12 (MB).
    Completing 60% with 252 violations.
    elapsed time = 00:00:36, memory = 4089.12 (MB).
    Completing 70% with 252 violations.
    elapsed time = 00:00:36, memory = 4089.12 (MB).
    Completing 80% with 246 violations.
    elapsed time = 00:00:51, memory = 4089.12 (MB).
    Completing 90% with 246 violations.
    elapsed time = 00:00:51, memory = 4089.12 (MB).
    Completing 100% with 213 violations.
    elapsed time = 00:01:00, memory = 4089.12 (MB).
[INFO DRT-0199]   Number of violations = 213.
[INFO DRT-0267] cpu time = 00:01:00, elapsed time = 00:01:00, memory = 4089.12 (MB), peak = 6495.17 (MB)
Total wire length = 406869 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 170668 um.
Total wire length on LAYER met2 = 152376 um.
Total wire length on LAYER met3 = 52437 um.
Total wire length on LAYER met4 = 31387 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 29213.
Up-via summary (total 29213):.

------------------------
 FR_MASTERSLICE        0
            li1    11769
           met1    13567
           met2     2791
           met3     1086
           met4        0
------------------------
                   29213


[INFO DRT-0195] Start 7th optimization iteration.
    Completing 10% with 213 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 20% with 213 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 30% with 165 violations.
    elapsed time = 00:00:05, memory = 4089.12 (MB).
    Completing 40% with 165 violations.
    elapsed time = 00:00:05, memory = 4089.12 (MB).
    Completing 50% with 165 violations.
    elapsed time = 00:00:22, memory = 4089.12 (MB).
    Completing 60% with 165 violations.
    elapsed time = 00:00:22, memory = 4089.12 (MB).
    Completing 70% with 165 violations.
    elapsed time = 00:00:22, memory = 4089.12 (MB).
    Completing 80% with 149 violations.
    elapsed time = 00:00:27, memory = 4089.12 (MB).
    Completing 90% with 149 violations.
    elapsed time = 00:00:27, memory = 4089.12 (MB).
    Completing 100% with 138 violations.
    elapsed time = 00:00:31, memory = 4089.12 (MB).
[INFO DRT-0199]   Number of violations = 138.
[INFO DRT-0267] cpu time = 00:00:33, elapsed time = 00:00:31, memory = 4089.12 (MB), peak = 6495.17 (MB)
Total wire length = 406833 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 170663 um.
Total wire length on LAYER met2 = 152301 um.
Total wire length on LAYER met3 = 52366 um.
Total wire length on LAYER met4 = 31502 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 29231.
Up-via summary (total 29231):.

------------------------
 FR_MASTERSLICE        0
            li1    11769
           met1    13569
           met2     2790
           met3     1103
           met4        0
------------------------
                   29231


[INFO DRT-0195] Start 8th optimization iteration.
    Completing 10% with 138 violations.
    elapsed time = 00:00:05, memory = 4089.12 (MB).
    Completing 20% with 138 violations.
    elapsed time = 00:00:05, memory = 4089.12 (MB).
    Completing 30% with 138 violations.
    elapsed time = 00:00:14, memory = 4089.12 (MB).
    Completing 40% with 138 violations.
    elapsed time = 00:00:14, memory = 4089.12 (MB).
    Completing 50% with 138 violations.
    elapsed time = 00:00:33, memory = 4089.12 (MB).
    Completing 60% with 138 violations.
    elapsed time = 00:00:33, memory = 4089.12 (MB).
    Completing 70% with 138 violations.
    elapsed time = 00:00:33, memory = 4089.12 (MB).
    Completing 80% with 138 violations.
    elapsed time = 00:00:34, memory = 4089.12 (MB).
    Completing 90% with 138 violations.
    elapsed time = 00:00:34, memory = 4089.12 (MB).
    Completing 100% with 135 violations.
    elapsed time = 00:00:45, memory = 4089.12 (MB).
[INFO DRT-0199]   Number of violations = 135.
[INFO DRT-0267] cpu time = 00:00:52, elapsed time = 00:00:45, memory = 4089.12 (MB), peak = 6495.17 (MB)
Total wire length = 406833 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 170665 um.
Total wire length on LAYER met2 = 152300 um.
Total wire length on LAYER met3 = 52365 um.
Total wire length on LAYER met4 = 31502 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 29233.
Up-via summary (total 29233):.

------------------------
 FR_MASTERSLICE        0
            li1    11769
           met1    13569
           met2     2792
           met3     1103
           met4        0
------------------------
                   29233


[INFO DRT-0195] Start 9th optimization iteration.
    Completing 10% with 135 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 20% with 135 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 30% with 135 violations.
    elapsed time = 00:00:01, memory = 4089.12 (MB).
    Completing 40% with 135 violations.
    elapsed time = 00:00:01, memory = 4089.12 (MB).
    Completing 50% with 135 violations.
    elapsed time = 00:00:18, memory = 4089.12 (MB).
    Completing 60% with 135 violations.
    elapsed time = 00:00:18, memory = 4089.12 (MB).
    Completing 70% with 135 violations.
    elapsed time = 00:00:18, memory = 4089.12 (MB).
    Completing 80% with 135 violations.
    elapsed time = 00:00:18, memory = 4089.12 (MB).
    Completing 90% with 135 violations.
    elapsed time = 00:00:18, memory = 4089.12 (MB).
    Completing 100% with 135 violations.
    elapsed time = 00:00:23, memory = 4089.12 (MB).
[INFO DRT-0199]   Number of violations = 135.
[INFO DRT-0267] cpu time = 00:00:24, elapsed time = 00:00:23, memory = 4089.12 (MB), peak = 6495.17 (MB)
Total wire length = 406833 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 170665 um.
Total wire length on LAYER met2 = 152300 um.
Total wire length on LAYER met3 = 52365 um.
Total wire length on LAYER met4 = 31502 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 29233.
Up-via summary (total 29233):.

------------------------
 FR_MASTERSLICE        0
            li1    11769
           met1    13569
           met2     2792
           met3     1103
           met4        0
------------------------
                   29233


[INFO DRT-0195] Start 10th optimization iteration.
    Completing 10% with 135 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 20% with 135 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 30% with 82 violations.
    elapsed time = 00:00:06, memory = 4089.12 (MB).
    Completing 40% with 82 violations.
    elapsed time = 00:00:06, memory = 4089.12 (MB).
    Completing 50% with 82 violations.
    elapsed time = 00:00:06, memory = 4089.12 (MB).
    Completing 60% with 69 violations.
    elapsed time = 00:00:07, memory = 4089.12 (MB).
    Completing 70% with 69 violations.
    elapsed time = 00:00:07, memory = 4089.12 (MB).
    Completing 80% with 69 violations.
    elapsed time = 00:00:24, memory = 4089.12 (MB).
    Completing 90% with 69 violations.
    elapsed time = 00:00:24, memory = 4089.12 (MB).
    Completing 100% with 64 violations.
    elapsed time = 00:00:25, memory = 4089.12 (MB).
[INFO DRT-0199]   Number of violations = 64.
[INFO DRT-0267] cpu time = 00:00:26, elapsed time = 00:00:26, memory = 4089.12 (MB), peak = 6495.17 (MB)
Total wire length = 406780 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 170676 um.
Total wire length on LAYER met2 = 152236 um.
Total wire length on LAYER met3 = 52337 um.
Total wire length on LAYER met4 = 31530 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 29253.
Up-via summary (total 29253):.

------------------------
 FR_MASTERSLICE        0
            li1    11769
           met1    13585
           met2     2791
           met3     1108
           met4        0
------------------------
                   29253


[INFO DRT-0195] Start 11th optimization iteration.
    Completing 10% with 64 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 20% with 64 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 30% with 58 violations.
    elapsed time = 00:00:11, memory = 4089.12 (MB).
    Completing 40% with 58 violations.
    elapsed time = 00:00:11, memory = 4089.12 (MB).
    Completing 50% with 58 violations.
    elapsed time = 00:00:11, memory = 4089.12 (MB).
    Completing 60% with 57 violations.
    elapsed time = 00:00:12, memory = 4089.12 (MB).
    Completing 70% with 57 violations.
    elapsed time = 00:00:12, memory = 4089.12 (MB).
    Completing 80% with 55 violations.
    elapsed time = 00:00:17, memory = 4089.12 (MB).
    Completing 90% with 55 violations.
    elapsed time = 00:00:17, memory = 4089.12 (MB).
    Completing 100% with 55 violations.
    elapsed time = 00:00:17, memory = 4089.12 (MB).
[INFO DRT-0199]   Number of violations = 55.
[INFO DRT-0267] cpu time = 00:00:17, elapsed time = 00:00:17, memory = 4089.12 (MB), peak = 6495.17 (MB)
Total wire length = 406825 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 170600 um.
Total wire length on LAYER met2 = 152240 um.
Total wire length on LAYER met3 = 52423 um.
Total wire length on LAYER met4 = 31560 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 29287.
Up-via summary (total 29287):.

------------------------
 FR_MASTERSLICE        0
            li1    11769
           met1    13598
           met2     2804
           met3     1116
           met4        0
------------------------
                   29287


[INFO DRT-0195] Start 12th optimization iteration.
    Completing 10% with 55 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 20% with 55 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 30% with 55 violations.
    elapsed time = 00:00:17, memory = 4089.12 (MB).
    Completing 40% with 55 violations.
    elapsed time = 00:00:17, memory = 4089.12 (MB).
    Completing 50% with 55 violations.
    elapsed time = 00:00:17, memory = 4089.12 (MB).
    Completing 60% with 55 violations.
    elapsed time = 00:00:17, memory = 4089.12 (MB).
    Completing 70% with 55 violations.
    elapsed time = 00:00:17, memory = 4089.12 (MB).
    Completing 80% with 55 violations.
    elapsed time = 00:00:17, memory = 4089.12 (MB).
    Completing 90% with 55 violations.
    elapsed time = 00:00:17, memory = 4089.12 (MB).
    Completing 100% with 55 violations.
    elapsed time = 00:00:17, memory = 4089.12 (MB).
[INFO DRT-0199]   Number of violations = 55.
[INFO DRT-0267] cpu time = 00:00:17, elapsed time = 00:00:17, memory = 4089.12 (MB), peak = 6495.17 (MB)
Total wire length = 406825 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 170600 um.
Total wire length on LAYER met2 = 152240 um.
Total wire length on LAYER met3 = 52423 um.
Total wire length on LAYER met4 = 31560 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 29287.
Up-via summary (total 29287):.

------------------------
 FR_MASTERSLICE        0
            li1    11769
           met1    13598
           met2     2804
           met3     1116
           met4        0
------------------------
                   29287


[INFO DRT-0195] Start 13th optimization iteration.
    Completing 10% with 55 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 20% with 55 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 30% with 6 violations.
    elapsed time = 00:00:02, memory = 4089.12 (MB).
    Completing 40% with 6 violations.
    elapsed time = 00:00:02, memory = 4089.12 (MB).
    Completing 50% with 6 violations.
    elapsed time = 00:00:06, memory = 4089.12 (MB).
    Completing 60% with 6 violations.
    elapsed time = 00:00:06, memory = 4089.12 (MB).
    Completing 70% with 6 violations.
    elapsed time = 00:00:06, memory = 4089.12 (MB).
    Completing 80% with 6 violations.
    elapsed time = 00:00:06, memory = 4089.12 (MB).
    Completing 90% with 6 violations.
    elapsed time = 00:00:06, memory = 4089.12 (MB).
    Completing 100% with 6 violations.
    elapsed time = 00:00:06, memory = 4089.12 (MB).
[INFO DRT-0199]   Number of violations = 6.
[INFO DRT-0267] cpu time = 00:00:07, elapsed time = 00:00:07, memory = 4089.12 (MB), peak = 6495.17 (MB)
Total wire length = 406835 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 170626 um.
Total wire length on LAYER met2 = 152232 um.
Total wire length on LAYER met3 = 52400 um.
Total wire length on LAYER met4 = 31575 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 29279.
Up-via summary (total 29279):.

------------------------
 FR_MASTERSLICE        0
            li1    11769
           met1    13589
           met2     2807
           met3     1114
           met4        0
------------------------
                   29279


[INFO DRT-0195] Start 14th optimization iteration.
    Completing 10% with 6 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 20% with 6 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 30% with 6 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 40% with 6 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 50% with 6 violations.
    elapsed time = 00:00:03, memory = 4089.12 (MB).
    Completing 60% with 5 violations.
    elapsed time = 00:00:03, memory = 4089.12 (MB).
    Completing 70% with 5 violations.
    elapsed time = 00:00:03, memory = 4089.12 (MB).
    Completing 80% with 5 violations.
    elapsed time = 00:00:03, memory = 4089.12 (MB).
    Completing 90% with 5 violations.
    elapsed time = 00:00:03, memory = 4089.12 (MB).
    Completing 100% with 5 violations.
    elapsed time = 00:00:03, memory = 4089.12 (MB).
[INFO DRT-0199]   Number of violations = 5.
[INFO DRT-0267] cpu time = 00:00:03, elapsed time = 00:00:03, memory = 4089.12 (MB), peak = 6495.17 (MB)
Total wire length = 406817 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 170614 um.
Total wire length on LAYER met2 = 152211 um.
Total wire length on LAYER met3 = 52413 um.
Total wire length on LAYER met4 = 31578 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 29271.
Up-via summary (total 29271):.

------------------------
 FR_MASTERSLICE        0
            li1    11769
           met1    13581
           met2     2808
           met3     1113
           met4        0
------------------------
                   29271


[INFO DRT-0195] Start 15th optimization iteration.
    Completing 10% with 5 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 20% with 5 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 30% with 5 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 40% with 5 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 50% with 5 violations.
    elapsed time = 00:00:01, memory = 4089.12 (MB).
    Completing 60% with 0 violations.
    elapsed time = 00:00:01, memory = 4089.12 (MB).
    Completing 70% with 0 violations.
    elapsed time = 00:00:01, memory = 4089.12 (MB).
    Completing 80% with 0 violations.
    elapsed time = 00:00:01, memory = 4089.12 (MB).
    Completing 90% with 0 violations.
    elapsed time = 00:00:01, memory = 4089.12 (MB).
    Completing 100% with 0 violations.
    elapsed time = 00:00:01, memory = 4089.12 (MB).
[INFO DRT-0199]   Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:01, elapsed time = 00:00:01, memory = 4089.12 (MB), peak = 6495.17 (MB)
Total wire length = 406828 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 170617 um.
Total wire length on LAYER met2 = 152227 um.
Total wire length on LAYER met3 = 52411 um.
Total wire length on LAYER met4 = 31571 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 29272.
Up-via summary (total 29272):.

------------------------
 FR_MASTERSLICE        0
            li1    11769
           met1    13584
           met2     2806
           met3     1113
           met4        0
------------------------
                   29272


[INFO DRT-0195] Start 17th optimization iteration.
    Completing 10% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 20% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 30% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 40% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 50% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 60% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 70% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 80% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 90% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 100% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
[INFO DRT-0199]   Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 4089.12 (MB), peak = 6495.17 (MB)
Total wire length = 406828 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 170617 um.
Total wire length on LAYER met2 = 152227 um.
Total wire length on LAYER met3 = 52411 um.
Total wire length on LAYER met4 = 31571 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 29272.
Up-via summary (total 29272):.

------------------------
 FR_MASTERSLICE        0
            li1    11769
           met1    13584
           met2     2806
           met3     1113
           met4        0
------------------------
                   29272


[INFO DRT-0195] Start 25th optimization iteration.
    Completing 10% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 20% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 30% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 40% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 50% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 60% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 70% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 80% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 90% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 100% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
[INFO DRT-0199]   Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 4089.12 (MB), peak = 6495.17 (MB)
Total wire length = 406828 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 170617 um.
Total wire length on LAYER met2 = 152227 um.
Total wire length on LAYER met3 = 52411 um.
Total wire length on LAYER met4 = 31571 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 29272.
Up-via summary (total 29272):.

------------------------
 FR_MASTERSLICE        0
            li1    11769
           met1    13584
           met2     2806
           met3     1113
           met4        0
------------------------
                   29272


[INFO DRT-0195] Start 33rd optimization iteration.
    Completing 10% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 20% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 30% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 40% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 50% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 60% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 70% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 80% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 90% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 100% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
[INFO DRT-0199]   Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 4089.12 (MB), peak = 6495.17 (MB)
Total wire length = 406828 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 170617 um.
Total wire length on LAYER met2 = 152227 um.
Total wire length on LAYER met3 = 52411 um.
Total wire length on LAYER met4 = 31571 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 29272.
Up-via summary (total 29272):.

------------------------
 FR_MASTERSLICE        0
            li1    11769
           met1    13584
           met2     2806
           met3     1113
           met4        0
------------------------
                   29272


[INFO DRT-0195] Start 41st optimization iteration.
    Completing 10% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 20% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 30% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 40% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 50% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 60% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 70% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 80% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 90% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 100% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
[INFO DRT-0199]   Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 4089.12 (MB), peak = 6495.17 (MB)
Total wire length = 406828 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 170617 um.
Total wire length on LAYER met2 = 152227 um.
Total wire length on LAYER met3 = 52411 um.
Total wire length on LAYER met4 = 31571 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 29272.
Up-via summary (total 29272):.

------------------------
 FR_MASTERSLICE        0
            li1    11769
           met1    13584
           met2     2806
           met3     1113
           met4        0
------------------------
                   29272


[INFO DRT-0195] Start 49th optimization iteration.
    Completing 10% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 20% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 30% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 40% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 50% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 60% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 70% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 80% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 90% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 100% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
[INFO DRT-0199]   Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 4089.12 (MB), peak = 6495.17 (MB)
Total wire length = 406828 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 170617 um.
Total wire length on LAYER met2 = 152227 um.
Total wire length on LAYER met3 = 52411 um.
Total wire length on LAYER met4 = 31571 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 29272.
Up-via summary (total 29272):.

------------------------
 FR_MASTERSLICE        0
            li1    11769
           met1    13584
           met2     2806
           met3     1113
           met4        0
------------------------
                   29272


[INFO DRT-0195] Start 57th optimization iteration.
    Completing 10% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 20% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 30% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 40% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 50% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 60% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 70% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 80% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 90% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
    Completing 100% with 0 violations.
    elapsed time = 00:00:00, memory = 4089.12 (MB).
[INFO DRT-0199]   Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 4089.12 (MB), peak = 6495.17 (MB)
Total wire length = 406828 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 170617 um.
Total wire length on LAYER met2 = 152227 um.
Total wire length on LAYER met3 = 52411 um.
Total wire length on LAYER met4 = 31571 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 29272.
Up-via summary (total 29272):.

------------------------
 FR_MASTERSLICE        0
            li1    11769
           met1    13584
           met2     2806
           met3     1113
           met4        0
------------------------
                   29272


[INFO DRT-0198] Complete detail routing.
Total wire length = 406828 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 170617 um.
Total wire length on LAYER met2 = 152227 um.
Total wire length on LAYER met3 = 52411 um.
Total wire length on LAYER met4 = 31571 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 29272.
Up-via summary (total 29272):.

------------------------
 FR_MASTERSLICE        0
            li1    11769
           met1    13584
           met2     2806
           met3     1113
           met4        0
------------------------
                   29272


[INFO DRT-0267] cpu time = 00:15:12, elapsed time = 00:10:48, memory = 4089.12 (MB), peak = 6495.17 (MB)

[INFO DRT-0180] Post processing.
Saving to /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/results/routing/WB_InterConnect.def