OpenROAD 8d53e9b018dec98fa63e907ddeb6c5406f035361 
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/merged.lef
[INFO ODB-0223]     Created 13 technology layers
[INFO ODB-0224]     Created 25 technology vias
[INFO ODB-0225]     Created 441 library cells
[INFO ODB-0226] Finished LEF file:  /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/merged.lef
[INFO ODB-0127] Reading DEF file: /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/floorplan/3-initial_fp.def
[INFO ODB-0128] Design: WB_InterConnect
[INFO ODB-0130]     Created 428 pins.
[INFO ODB-0131]     Created 2753 components and 20435 component-terminals.
[INFO ODB-0133]     Created 2957 nets and 9423 connections.
[INFO ODB-0134] Finished DEF file: /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/floorplan/3-initial_fp.def
Top-level design name: WB_InterConnect
Warning: Some pins weren't matched by the config file
Those are: ['io_imem_io_cs', 'io_imem_io_wr_en', 'io_spi_clk_en', 'io_spi_cs_en', 'io_spi_mosi_en', 'io_uart_txen', 'io_imem_io_addr[0]', 'io_imem_io_rdata[0]', 'io_imem_io_st_type[0]', 'io_imem_io_wdata[0]', 'io_imem_io_addr[1]', 'io_imem_io_rdata[1]', 'io_imem_io_st_type[1]', 'io_imem_io_wdata[1]', 'io_imem_io_addr[2]', 'io_imem_io_rdata[2]', 'io_imem_io_st_type[2]', 'io_imem_io_wdata[2]', 'io_imem_io_addr[3]', 'io_imem_io_rdata[3]', 'io_imem_io_st_type[3]', 'io_imem_io_wdata[3]', 'io_imem_io_addr[4]', 'io_imem_io_rdata[4]', 'io_imem_io_wdata[4]', 'io_imem_io_addr[5]', 'io_imem_io_rdata[5]', 'io_imem_io_wdata[5]', 'io_imem_io_addr[6]', 'io_imem_io_rdata[6]', 'io_imem_io_wdata[6]', 'io_imem_io_addr[7]', 'io_imem_io_rdata[7]', 'io_imem_io_wdata[7]', 'io_imem_io_addr[8]', 'io_imem_io_rdata[8]', 'io_imem_io_wdata[8]', 'io_imem_io_rdata[9]', 'io_imem_io_wdata[9]', 'io_imem_io_rdata[10]', 'io_imem_io_wdata[10]', 'io_imem_io_rdata[11]', 'io_imem_io_wdata[11]', 'io_imem_io_rdata[12]', 'io_imem_io_wdata[12]', 'io_imem_io_rdata[13]', 'io_imem_io_wdata[13]', 'io_imem_io_rdata[14]', 'io_imem_io_wdata[14]', 'io_imem_io_rdata[15]', 'io_imem_io_wdata[15]', 'io_imem_io_rdata[16]', 'io_imem_io_wdata[16]', 'io_imem_io_rdata[17]', 'io_imem_io_wdata[17]', 'io_imem_io_rdata[18]', 'io_imem_io_wdata[18]', 'io_imem_io_rdata[19]', 'io_imem_io_wdata[19]', 'io_imem_io_rdata[20]', 'io_imem_io_wdata[20]', 'io_imem_io_rdata[21]', 'io_imem_io_wdata[21]', 'io_imem_io_rdata[22]', 'io_imem_io_wdata[22]', 'io_imem_io_rdata[23]', 'io_imem_io_wdata[23]', 'io_imem_io_rdata[24]', 'io_imem_io_wdata[24]', 'io_imem_io_rdata[25]', 'io_imem_io_wdata[25]', 'io_imem_io_rdata[26]', 'io_imem_io_wdata[26]', 'io_imem_io_rdata[27]', 'io_imem_io_wdata[27]', 'io_imem_io_rdata[28]', 'io_imem_io_wdata[28]', 'io_imem_io_rdata[29]', 'io_imem_io_wdata[29]', 'io_imem_io_rdata[30]', 'io_imem_io_wdata[30]', 'io_imem_io_rdata[31]', 'io_imem_io_wdata[31]']
Assigning random sides to the above pins
Block boundaries: 0 0 1100000 1100000
Writing /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/floorplan/4-io.def...