CVC: Log output to /home/ali112000/mpw5/UETRV-ECORE/openlane/Core/runs/Core/reports/finishing/Core.rpt
CVC: Error output to /home/ali112000/mpw5/UETRV-ECORE/openlane/Core/runs/Core/reports/finishing/Core.rpt.error.gz
CVC: Debug output to /home/ali112000/mpw5/UETRV-ECORE/openlane/Core/runs/Core/reports/finishing/Core.rpt.debug.gz
CVC: Circuit Validation Check  Version 1.1.0
CVC: Start: Mon Mar 21 23:37:53 2022

Using the following parameters for CVC (Circuit Validation Check) from /openlane/scripts/cvc/sky130A/cvcrc.sky130A
CVC_TOP = 'Core'
CVC_NETLIST = '/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/runs/Core/tmp/finishing/Core.cdl'
CVC_MODE = 'Core'
CVC_MODEL_FILE = '/openlane/scripts/cvc/sky130A/cvc.sky130A.models'
CVC_POWER_FILE = '/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/runs/Core/tmp/finishing/Core.power'
CVC_FUSE_FILE = ''
CVC_REPORT_FILE = '/home/ali112000/mpw5/UETRV-ECORE/openlane/Core/runs/Core/reports/finishing/Core.rpt'
CVC_REPORT_TITLE = 'CVC $CVC_TOP'
CVC_CIRCUIT_ERROR_LIMIT = '100'
CVC_SEARCH_LIMIT = '100'
CVC_LEAK_LIMIT = '0.0002'
CVC_SOI = 'false'
CVC_SCRC = 'false'
CVC_VTH_GATES = 'false'
CVC_MIN_VTH_GATES = 'false'
CVC_IGNORE_VTH_FLOATING = 'false'
CVC_IGNORE_NO_LEAK_FLOATING = 'false'
CVC_LEAK_OVERVOLTAGE = 'true'
CVC_LOGIC_DIODES = 'false'
CVC_ANALOG_GATES = 'true'
CVC_BACKUP_RESULTS = 'false'
CVC_MOS_DIODE_ERROR_THRESHOLD = '0'
CVC_SHORT_ERROR_THRESHOLD = '0'
CVC_BIAS_ERROR_THRESHOLD = '0'
CVC_FORWARD_ERROR_THRESHOLD = '0'
CVC_FLOATING_ERROR_THRESHOLD = '0'
CVC_GATE_ERROR_THRESHOLD = '0'
CVC_LEAK?_ERROR_THRESHOLD = '0'
CVC_EXPECTED_ERROR_THRESHOLD = '0'
CVC_OVERVOLTAGE_ERROR_THRESHOLD = '0'
CVC_PARALLEL_CIRCUIT_PORT_LIMIT = '0'
CVC_CELL_ERROR_LIMIT_FILE = ''
CVC_CELL_CHECKSUM_FILE = ''
CVC_LARGE_CIRCUIT_SIZE = '10000000'
CVC_NET_CHECK_FILE = ''
CVC_MODEL_CHECK_FILE = ''
End of parameters

CVC: Reading device model settings...
CVC: Reading power settings...
CVC: Parsing netlist /home/ali112000/mpw5/UETRV-ECORE/openlane/Core/runs/Core/tmp/finishing/Core.cdl
Cdl fixed data size 736123
Usage CDL: Time: 0  Memory: 30752  I/O: 4560  Swap: 0
CVC: Counting and linking...
CVC: Assigning IDs ...
Usage DB: Time: 0  Memory: 33652  I/O: 4560  Swap: 0
CVC: 43385(43385) instances, 60267(60267) nets, 133742(133742) devices.
CVC: Setting models ...
Setting model tolerances...
CVC: Shorting switches...
	Shorted 0 short
Setting instance power...

ModelList> filename /openlane/scripts/cvc/sky130A/cvc.sky130A.models
 Model> sky130_fd_pr__cap_mim_m3_1         0 C->capacitor  Parameters>
 Model> sky130_fd_pr__cap_mim_m3_2         0 C->capacitor  Parameters>
 Model> sky130_fd_pr__cap_var         0 C->capacitor  Parameters>
 Model> condiode           0 D->diode      Parameters> Diodes> 1-2
 Model> sky130_fd_pr__diode_pd2nw_05v5         0 D->diode      Parameters> Diodes> 1-2
 Model> sky130_fd_pr__diode_pw2nd_05v5         0 D->diode      Parameters> Diodes> 1-2
 Model> sky130_fd_pr__diode_pw2nd_11v0         0 D->diode      Parameters> Diodes> 1-2
 Model> sky130_fd_pr__model__parasitic__diode_ps2dn         0 D->diode      Parameters> Diodes> 1-2
 Model> sky130_fd_pr__model__parasitic__diode_ps2nw         0 D->diode      Parameters> Diodes> 1-2
 Model> sky130_fd_pr__model__parasitic__diode_pw2dn         0 D->diode      Parameters> Diodes> 1-2
 Model> nfet_01v8      66871 M->nmos       Parameters> Vth=0.2 Vds=1.8 Vgs=1.8 R=L/W*7000 Diodes> 4-1 4-3
 Model> pfet_01v8_hvt     66871 M->pmos       Parameters> Vth=-0.2 Vds=1.8 Vgs=1.8 R=L/W*7000 Diodes> 1-4 3-4
 Model> sky130_fd_bs_flash__special_sonosfet_star         0 M->nmos       Parameters> Vth=0.2 R=L/W*7000 Diodes> 4-1 4-3
 Model> sky130_fd_pr__esd_nfet_g5v0d10v5         0 M->nmos       Parameters> Vth=0.2 R=L/W*7000 Diodes> 4-1 4-3
 Model> sky130_fd_pr__nfet_01v8         0 M->nmos       Parameters> Vth=0.2 Vds=1.8 Vgs=1.8 R=L/W*7000 Diodes> 4-1 4-3
 Model> sky130_fd_pr__nfet_01v8_lvt         0 M->nmos       Parameters> Vth=0.1 Vds=1.8 Vgs=1.8 R=L/W*7000 Diodes> 4-1 4-3
 Model> sky130_fd_pr__nfet_03v3_nvt         0 M->nmos       Parameters> Vth=0.2 Vds=3.3 Vgs=3.3 R=L/W*7000 Diodes> 4-1 4-3
 Model> sky130_fd_pr__nfet_05v0_nvt         0 M->nmos       Parameters> Vth=0.2 R=L/W*7000 Diodes> 4-1 4-3
 Model> sky130_fd_pr__nfet_g5v0d10v5         0 M->nmos       Parameters> Vth=0.2 R=L/W*7000 Diodes> 4-1 4-3
 Model> sky130_fd_pr__pfet_01v8         0 M->pmos       Parameters> Vth=-0.2 Vds=1.8 Vgs=1.8 R=L/W*7000 Diodes> 1-4 3-4
 Model> sky130_fd_pr__pfet_01v8_hvt         0 M->pmos       Parameters> Vth=-0.3 Vds=1.8 Vgs=1.8 R=L/W*7000 Diodes> 1-4 3-4
 Model> sky130_fd_pr__pfet_01v8_lvt         0 M->pmos       Parameters> Vth=-0.1 Vds=1.8 Vgs=1.8 R=L/W*7000 Diodes> 1-4 3-4
 Model> sky130_fd_pr__pfet_g5v0d10v5         0 M->pmos       Parameters> Vth=-0.2 R=L/W*7000 Diodes> 1-4 3-4
 Model> sky130_fd_pr__special_nfet_latch         0 M->nmos       Parameters> Vth=0.2 Vds=1.8 Vgs=1.8 R=L/W*7000 Diodes> 4-1 4-3
 Model> sky130_fd_pr__special_pfet_pass         0 M->pmos       Parameters> Vth=-0.2 Vds=1.8 Vgs=1.8 R=L/W*7000 Diodes> 1-4 3-4
 Model> sky130_fd_pr__pnp_05v5         0 Q->bipolar    Parameters>
 Model> short              0 R->switch_on  Parameters>
 Model> sky130_fd_pr__res_generic_m1         0 R->resistor   Parameters> R=l/w
 Model> sky130_fd_pr__res_generic_m2         0 R->resistor   Parameters> R=l/w
 Model> sky130_fd_pr__res_generic_m3         0 R->resistor   Parameters> R=l/w
 Model> sky130_fd_pr__res_generic_m4         0 R->resistor   Parameters> R=l/w
 Model> sky130_fd_pr__res_generic_m5         0 R->resistor   Parameters> R=l/w
 Model> sky130_fd_pr__res_generic_nd         0 R->resistor   Parameters> R=l/w*120
 Model> sky130_fd_pr__res_generic_nd__hv         0 R->resistor   Parameters> R=l/w*114
 Model> sky130_fd_pr__res_generic_pd__hv         0 R->resistor   Parameters> R=l/w*191
 Model> sky130_fd_pr__res_generic_po         0 R->resistor   Parameters> R=l/w*48
 Model> sky130_fd_pr__res_high_po         0 R->resistor   Parameters> R=l/w*2000
 Model> sky130_fd_pr__res_xhigh_po         0 R->resistor   Parameters> R=l/w*2000
ModelList> end

Power List> filename /home/ali112000/mpw5/UETRV-ECORE/openlane/Core/runs/Core/tmp/finishing/Core.power
 vccd1 power 1.8 -> 1.8 power
 vssd1 power 0.0 -> 0.0 power
 clock~>std_input input std_input -> min@0.0 max@1.8 input family(std_input;)
 io_dbus_valid~>std_input input std_input -> min@0.0 max@1.8 input family(std_input;)
 io_ibus_valid~>std_input input std_input -> min@0.0 max@1.8 input family(std_input;)
 io_irq_motor_irq~>std_input input std_input -> min@0.0 max@1.8 input family(std_input;)
 io_irq_spi_irq~>std_input input std_input -> min@0.0 max@1.8 input family(std_input;)
 io_irq_uart_irq~>std_input input std_input -> min@0.0 max@1.8 input family(std_input;)
 reset~>std_input input std_input -> min@0.0 max@1.8 input family(std_input;)
io_dbus_rdata[31:0]~>std_input input std_input
 ->io_dbus_rdata[0] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_rdata[10] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_rdata[11] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_rdata[12] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_rdata[13] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_rdata[14] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_rdata[15] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_rdata[16] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_rdata[17] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_rdata[18] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_rdata[19] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_rdata[1] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_rdata[20] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_rdata[21] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_rdata[22] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_rdata[23] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_rdata[24] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_rdata[25] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_rdata[26] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_rdata[27] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_rdata[28] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_rdata[29] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_rdata[2] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_rdata[30] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_rdata[31] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_rdata[3] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_rdata[4] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_rdata[5] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_rdata[6] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_rdata[7] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_rdata[8] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_rdata[9] input std_input -> min@0.0 max@1.8 input family(std_input;)
io_ibus_inst[31:0]~>std_input input std_input
 ->io_ibus_inst[0] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_inst[10] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_inst[11] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_inst[12] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_inst[13] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_inst[14] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_inst[15] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_inst[16] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_inst[17] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_inst[18] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_inst[19] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_inst[1] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_inst[20] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_inst[21] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_inst[22] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_inst[23] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_inst[24] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_inst[25] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_inst[26] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_inst[27] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_inst[28] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_inst[29] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_inst[2] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_inst[30] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_inst[31] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_inst[3] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_inst[4] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_inst[5] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_inst[6] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_inst[7] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_inst[8] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_inst[9] input std_input -> min@0.0 max@1.8 input family(std_input;)
> expected values
> macros
 #define std_input min@vssd1 max@vccd1 -> min@0.0 max@1.8
Power List> end

CVC: Linking devices...
Usage EQUIV: Time: 0  Memory: 48068  I/O: 4632  Swap: 0
Power nets 83
Hash dump:parameter->resistance map
Contains 53 buckets, 52 elements
Element count 0, 23
Element count 1, 15
Element count 2, 8
Element count 3, 7
Unused hash: 0.43, average depth 2.12
Hash dump:text->circuit map
Contains 337 buckets, 438 elements
Element count 0, 71
Element count 1, 135
Element count 2, 96
Element count 3, 29
Element count 4, 6
Unused hash: 0.21, average depth 2.00
Hash dump:string->text map
Contains 53201 buckets, 55797 elements
Element count 0, 18639
Element count 1, 19590
Element count 2, 10167
Element count 3, 3630
Element count 4, 937
Element count 5, 202
Element count 6, 29
Element count 7, 6
Element count 8, 0
Element count 9, 1
Unused hash: 0.35, average depth 2.05
CVC: Shorting non conducting resistors...
CVC: Calculating resistor voltages...
Usage RES: Time: 0  Memory: 48068  I/O: 4640  Swap: 0
Power nets 83
CVC: Calculating min/max voltages...
Processing trivial nets found 22304 trivial nets
CVC: Ignoring invalid calculations...
CVC:   Removed 0 calculations
Copying master nets
CVC: Ignoring non-conducting devices...
CVC:   Ignored 0 devices
Usage MIN/MAX1: Time: 0  Memory: 49972  I/O: 4640  Swap: 0
Power nets 23069
! Checking forward bias diode errors: 

! Checking nmos source/drain vs bias errors: 

! Checking nmos gate vs source errors: 

! Checking pmos source/drain vs bias errors: 

! Checking pmos gate vs source errors: 

Usage ERROR: Time: 0  Memory: 49972  I/O: 4640  Swap: 0
CVC: Propagating Simulation voltages 1...
Usage SIM1: Time: 0  Memory: 51028  I/O: 4640  Swap: 0
Power nets 23069
CVC: Propagating Simulation voltages 3...
Usage SIM2: Time: 0  Memory: 51556  I/O: 4640  Swap: 0
Power nets 23069
Added 0 latch voltages
CVC: Calculating min/max voltages...
Processing trivial nets found 22304 trivial nets
CVC: Ignoring invalid calculations...
CVC:   Removed 0 calculations
Copying master nets
CVC: Ignoring non-conducting devices...
CVC:   Ignored 0 devices
Usage MIN/MAX2: Time: 0  Memory: 53404  I/O: 4640  Swap: 0
Power nets 46055
! Checking overvoltage errors

! Checking nmos possible leak errors: 

! Checking pmos possible leak errors: 

! Checking mos floating input errors:

! Checking expected values:

CVC: Error Counts
CVC: Fuse Problems:         0
CVC: Min Voltage Conflicts: 0
CVC: Max Voltage Conflicts: 0
CVC: Leaks:                 0
CVC: LDD drain->source:     0
CVC: HI-Z Inputs:           0
CVC: Forward Bias Diodes:   0
CVC: NMOS Source vs Bulk:   0
CVC: NMOS Gate vs Source:   0
CVC: NMOS Possible Leaks:   0
CVC: PMOS Source vs Bulk:   0
CVC: PMOS Gate vs Source:   0
CVC: PMOS Possible Leaks:   0
CVC: Overvoltage-VBG:       0
CVC: Overvoltage-VBS:       0
CVC: Overvoltage-VDS:       0
CVC: Overvoltage-VGS:       0
CVC: Model errors:          0
CVC: Unexpected voltage :   0
CVC: Total:                 0
Usage Total: Time: 1  Memory: 53928  I/O: 4680  Swap: 0
Virtual net update/access 487588/13790011
CVC: Log output to /home/ali112000/mpw5/UETRV-ECORE/openlane/Core/runs/Core/reports/finishing/Core.rpt
CVC: End: Mon Mar 21 23:37:54 2022