CVC: Log output to /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/reports/finishing/WB_InterConnect.rpt
CVC: Error output to /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/reports/finishing/WB_InterConnect.rpt.error.gz
CVC: Debug output to /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/reports/finishing/WB_InterConnect.rpt.debug.gz
CVC: Circuit Validation Check  Version 1.1.0
CVC: Start: Tue Mar 22 00:15:29 2022

Using the following parameters for CVC (Circuit Validation Check) from /openlane/scripts/cvc/sky130A/cvcrc.sky130A
CVC_TOP = 'WB_InterConnect'
CVC_NETLIST = '/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/finishing/WB_InterConnect.cdl'
CVC_MODE = 'WB_InterConnect'
CVC_MODEL_FILE = '/openlane/scripts/cvc/sky130A/cvc.sky130A.models'
CVC_POWER_FILE = '/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/finishing/WB_InterConnect.power'
CVC_FUSE_FILE = ''
CVC_REPORT_FILE = '/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/reports/finishing/WB_InterConnect.rpt'
CVC_REPORT_TITLE = 'CVC $CVC_TOP'
CVC_CIRCUIT_ERROR_LIMIT = '100'
CVC_SEARCH_LIMIT = '100'
CVC_LEAK_LIMIT = '0.0002'
CVC_SOI = 'false'
CVC_SCRC = 'false'
CVC_VTH_GATES = 'false'
CVC_MIN_VTH_GATES = 'false'
CVC_IGNORE_VTH_FLOATING = 'false'
CVC_IGNORE_NO_LEAK_FLOATING = 'false'
CVC_LEAK_OVERVOLTAGE = 'true'
CVC_LOGIC_DIODES = 'false'
CVC_ANALOG_GATES = 'true'
CVC_BACKUP_RESULTS = 'false'
CVC_MOS_DIODE_ERROR_THRESHOLD = '0'
CVC_SHORT_ERROR_THRESHOLD = '0'
CVC_BIAS_ERROR_THRESHOLD = '0'
CVC_FORWARD_ERROR_THRESHOLD = '0'
CVC_FLOATING_ERROR_THRESHOLD = '0'
CVC_GATE_ERROR_THRESHOLD = '0'
CVC_LEAK?_ERROR_THRESHOLD = '0'
CVC_EXPECTED_ERROR_THRESHOLD = '0'
CVC_OVERVOLTAGE_ERROR_THRESHOLD = '0'
CVC_PARALLEL_CIRCUIT_PORT_LIMIT = '0'
CVC_CELL_ERROR_LIMIT_FILE = ''
CVC_CELL_CHECKSUM_FILE = ''
CVC_LARGE_CIRCUIT_SIZE = '10000000'
CVC_NET_CHECK_FILE = ''
CVC_MODEL_CHECK_FILE = ''
End of parameters

CVC: Reading device model settings...
CVC: Reading power settings...
CVC: Parsing netlist /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/finishing/WB_InterConnect.cdl
Cdl fixed data size 1934446
Usage CDL: Time: 0  Memory: 66696  I/O: 8  Swap: 0
CVC: Counting and linking...
CVC: Assigning IDs ...
Usage DB: Time: 0  Memory: 75208  I/O: 8  Swap: 0
CVC: 123498(123498) instances, 13126(13126) nets, 190352(190352) devices.
CVC: Setting models ...
Setting model tolerances...
CVC: Shorting switches...
	Shorted 0 short
Setting instance power...

ModelList> filename /openlane/scripts/cvc/sky130A/cvc.sky130A.models
 Model> sky130_fd_pr__cap_mim_m3_1         0 C->capacitor  Parameters>
 Model> sky130_fd_pr__cap_mim_m3_2         0 C->capacitor  Parameters>
 Model> sky130_fd_pr__cap_var         0 C->capacitor  Parameters>
 Model> condiode           0 D->diode      Parameters> Diodes> 1-2
 Model> sky130_fd_pr__diode_pd2nw_05v5         0 D->diode      Parameters> Diodes> 1-2
 Model> sky130_fd_pr__diode_pw2nd_05v5         0 D->diode      Parameters> Diodes> 1-2
 Model> sky130_fd_pr__diode_pw2nd_11v0         0 D->diode      Parameters> Diodes> 1-2
 Model> sky130_fd_pr__model__parasitic__diode_ps2dn         0 D->diode      Parameters> Diodes> 1-2
 Model> sky130_fd_pr__model__parasitic__diode_ps2nw         0 D->diode      Parameters> Diodes> 1-2
 Model> sky130_fd_pr__model__parasitic__diode_pw2dn         0 D->diode      Parameters> Diodes> 1-2
 Model> nfet_01v8      95176 M->nmos       Parameters> Vth=0.2 Vds=1.8 Vgs=1.8 R=L/W*7000 Diodes> 4-1 4-3
 Model> pfet_01v8_hvt     95176 M->pmos       Parameters> Vth=-0.2 Vds=1.8 Vgs=1.8 R=L/W*7000 Diodes> 1-4 3-4
 Model> sky130_fd_bs_flash__special_sonosfet_star         0 M->nmos       Parameters> Vth=0.2 R=L/W*7000 Diodes> 4-1 4-3
 Model> sky130_fd_pr__esd_nfet_g5v0d10v5         0 M->nmos       Parameters> Vth=0.2 R=L/W*7000 Diodes> 4-1 4-3
 Model> sky130_fd_pr__nfet_01v8         0 M->nmos       Parameters> Vth=0.2 Vds=1.8 Vgs=1.8 R=L/W*7000 Diodes> 4-1 4-3
 Model> sky130_fd_pr__nfet_01v8_lvt         0 M->nmos       Parameters> Vth=0.1 Vds=1.8 Vgs=1.8 R=L/W*7000 Diodes> 4-1 4-3
 Model> sky130_fd_pr__nfet_03v3_nvt         0 M->nmos       Parameters> Vth=0.2 Vds=3.3 Vgs=3.3 R=L/W*7000 Diodes> 4-1 4-3
 Model> sky130_fd_pr__nfet_05v0_nvt         0 M->nmos       Parameters> Vth=0.2 R=L/W*7000 Diodes> 4-1 4-3
 Model> sky130_fd_pr__nfet_g5v0d10v5         0 M->nmos       Parameters> Vth=0.2 R=L/W*7000 Diodes> 4-1 4-3
 Model> sky130_fd_pr__pfet_01v8         0 M->pmos       Parameters> Vth=-0.2 Vds=1.8 Vgs=1.8 R=L/W*7000 Diodes> 1-4 3-4
 Model> sky130_fd_pr__pfet_01v8_hvt         0 M->pmos       Parameters> Vth=-0.3 Vds=1.8 Vgs=1.8 R=L/W*7000 Diodes> 1-4 3-4
 Model> sky130_fd_pr__pfet_01v8_lvt         0 M->pmos       Parameters> Vth=-0.1 Vds=1.8 Vgs=1.8 R=L/W*7000 Diodes> 1-4 3-4
 Model> sky130_fd_pr__pfet_g5v0d10v5         0 M->pmos       Parameters> Vth=-0.2 R=L/W*7000 Diodes> 1-4 3-4
 Model> sky130_fd_pr__special_nfet_latch         0 M->nmos       Parameters> Vth=0.2 Vds=1.8 Vgs=1.8 R=L/W*7000 Diodes> 4-1 4-3
 Model> sky130_fd_pr__special_pfet_pass         0 M->pmos       Parameters> Vth=-0.2 Vds=1.8 Vgs=1.8 R=L/W*7000 Diodes> 1-4 3-4
 Model> sky130_fd_pr__pnp_05v5         0 Q->bipolar    Parameters>
 Model> short              0 R->switch_on  Parameters>
 Model> sky130_fd_pr__res_generic_m1         0 R->resistor   Parameters> R=l/w
 Model> sky130_fd_pr__res_generic_m2         0 R->resistor   Parameters> R=l/w
 Model> sky130_fd_pr__res_generic_m3         0 R->resistor   Parameters> R=l/w
 Model> sky130_fd_pr__res_generic_m4         0 R->resistor   Parameters> R=l/w
 Model> sky130_fd_pr__res_generic_m5         0 R->resistor   Parameters> R=l/w
 Model> sky130_fd_pr__res_generic_nd         0 R->resistor   Parameters> R=l/w*120
 Model> sky130_fd_pr__res_generic_nd__hv         0 R->resistor   Parameters> R=l/w*114
 Model> sky130_fd_pr__res_generic_pd__hv         0 R->resistor   Parameters> R=l/w*191
 Model> sky130_fd_pr__res_generic_po         0 R->resistor   Parameters> R=l/w*48
 Model> sky130_fd_pr__res_high_po         0 R->resistor   Parameters> R=l/w*2000
 Model> sky130_fd_pr__res_xhigh_po         0 R->resistor   Parameters> R=l/w*2000
ModelList> end

Power List> filename /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/finishing/WB_InterConnect.power
 vccd1 power 1.8 -> 1.8 power
 vssd1 power 0.0 -> 0.0 power
 clock~>std_input input std_input -> min@0.0 max@1.8 input family(std_input;)
 io_dbus_rd_en~>std_input input std_input -> min@0.0 max@1.8 input family(std_input;)
 io_dbus_wr_en~>std_input input std_input -> min@0.0 max@1.8 input family(std_input;)
 io_motor_ack_i~>std_input input std_input -> min@0.0 max@1.8 input family(std_input;)
 io_spi_miso~>std_input input std_input -> min@0.0 max@1.8 input family(std_input;)
 io_uart_rx~>std_input input std_input -> min@0.0 max@1.8 input family(std_input;)
 reset~>std_input input std_input -> min@0.0 max@1.8 input family(std_input;)
io_dbus_addr[31:0]~>std_input input std_input
 ->io_dbus_addr[0] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_addr[10] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_addr[11] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_addr[12] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_addr[13] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_addr[14] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_addr[15] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_addr[16] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_addr[17] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_addr[18] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_addr[19] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_addr[1] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_addr[20] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_addr[21] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_addr[22] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_addr[23] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_addr[24] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_addr[25] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_addr[26] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_addr[27] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_addr[28] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_addr[29] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_addr[2] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_addr[30] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_addr[31] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_addr[3] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_addr[4] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_addr[5] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_addr[6] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_addr[7] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_addr[8] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_addr[9] input std_input -> min@0.0 max@1.8 input family(std_input;)
io_dbus_ld_type[2:0]~>std_input input std_input
 ->io_dbus_ld_type[0] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_ld_type[1] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_ld_type[2] input std_input -> min@0.0 max@1.8 input family(std_input;)
io_dbus_st_type[1:0]~>std_input input std_input
 ->io_dbus_st_type[0] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_st_type[1] input std_input -> min@0.0 max@1.8 input family(std_input;)
io_dbus_wdata[31:0]~>std_input input std_input
 ->io_dbus_wdata[0] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_wdata[10] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_wdata[11] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_wdata[12] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_wdata[13] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_wdata[14] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_wdata[15] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_wdata[16] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_wdata[17] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_wdata[18] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_wdata[19] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_wdata[1] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_wdata[20] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_wdata[21] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_wdata[22] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_wdata[23] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_wdata[24] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_wdata[25] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_wdata[26] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_wdata[27] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_wdata[28] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_wdata[29] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_wdata[2] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_wdata[30] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_wdata[31] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_wdata[3] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_wdata[4] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_wdata[5] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_wdata[6] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_wdata[7] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_wdata[8] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dbus_wdata[9] input std_input -> min@0.0 max@1.8 input family(std_input;)
io_dmem_io_rdata[31:0]~>std_input input std_input
 ->io_dmem_io_rdata[0] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dmem_io_rdata[10] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dmem_io_rdata[11] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dmem_io_rdata[12] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dmem_io_rdata[13] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dmem_io_rdata[14] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dmem_io_rdata[15] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dmem_io_rdata[16] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dmem_io_rdata[17] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dmem_io_rdata[18] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dmem_io_rdata[19] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dmem_io_rdata[1] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dmem_io_rdata[20] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dmem_io_rdata[21] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dmem_io_rdata[22] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dmem_io_rdata[23] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dmem_io_rdata[24] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dmem_io_rdata[25] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dmem_io_rdata[26] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dmem_io_rdata[27] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dmem_io_rdata[28] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dmem_io_rdata[29] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dmem_io_rdata[2] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dmem_io_rdata[30] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dmem_io_rdata[31] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dmem_io_rdata[3] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dmem_io_rdata[4] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dmem_io_rdata[5] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dmem_io_rdata[6] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dmem_io_rdata[7] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dmem_io_rdata[8] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_dmem_io_rdata[9] input std_input -> min@0.0 max@1.8 input family(std_input;)
io_ibus_addr[31:0]~>std_input input std_input
 ->io_ibus_addr[0] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_addr[10] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_addr[11] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_addr[12] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_addr[13] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_addr[14] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_addr[15] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_addr[16] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_addr[17] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_addr[18] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_addr[19] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_addr[1] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_addr[20] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_addr[21] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_addr[22] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_addr[23] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_addr[24] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_addr[25] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_addr[26] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_addr[27] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_addr[28] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_addr[29] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_addr[2] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_addr[30] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_addr[31] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_addr[3] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_addr[4] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_addr[5] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_addr[6] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_addr[7] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_addr[8] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_ibus_addr[9] input std_input -> min@0.0 max@1.8 input family(std_input;)
io_imem_io_rdata[31:0]~>std_input input std_input
 ->io_imem_io_rdata[0] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_imem_io_rdata[10] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_imem_io_rdata[11] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_imem_io_rdata[12] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_imem_io_rdata[13] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_imem_io_rdata[14] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_imem_io_rdata[15] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_imem_io_rdata[16] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_imem_io_rdata[17] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_imem_io_rdata[18] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_imem_io_rdata[19] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_imem_io_rdata[1] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_imem_io_rdata[20] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_imem_io_rdata[21] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_imem_io_rdata[22] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_imem_io_rdata[23] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_imem_io_rdata[24] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_imem_io_rdata[25] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_imem_io_rdata[26] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_imem_io_rdata[27] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_imem_io_rdata[28] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_imem_io_rdata[29] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_imem_io_rdata[2] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_imem_io_rdata[30] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_imem_io_rdata[31] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_imem_io_rdata[3] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_imem_io_rdata[4] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_imem_io_rdata[5] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_imem_io_rdata[6] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_imem_io_rdata[7] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_imem_io_rdata[8] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_imem_io_rdata[9] input std_input -> min@0.0 max@1.8 input family(std_input;)
io_motor_data_i[31:0]~>std_input input std_input
 ->io_motor_data_i[0] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_motor_data_i[10] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_motor_data_i[11] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_motor_data_i[12] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_motor_data_i[13] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_motor_data_i[14] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_motor_data_i[15] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_motor_data_i[16] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_motor_data_i[17] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_motor_data_i[18] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_motor_data_i[19] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_motor_data_i[1] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_motor_data_i[20] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_motor_data_i[21] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_motor_data_i[22] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_motor_data_i[23] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_motor_data_i[24] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_motor_data_i[25] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_motor_data_i[26] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_motor_data_i[27] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_motor_data_i[28] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_motor_data_i[29] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_motor_data_i[2] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_motor_data_i[30] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_motor_data_i[31] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_motor_data_i[3] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_motor_data_i[4] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_motor_data_i[5] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_motor_data_i[6] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_motor_data_i[7] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_motor_data_i[8] input std_input -> min@0.0 max@1.8 input family(std_input;)
 ->io_motor_data_i[9] input std_input -> min@0.0 max@1.8 input family(std_input;)
> expected values
> macros
 #define std_input min@vssd1 max@vccd1 -> min@0.0 max@1.8
Power List> end

CVC: Linking devices...
Usage EQUIV: Time: 0  Memory: 86140  I/O: 48  Swap: 0
Power nets 216
Hash dump:parameter->resistance map
Contains 53 buckets, 44 elements
Element count 0, 14
Element count 1, 34
Element count 2, 5
Unused hash: 0.26, average depth 1.23
Hash dump:text->circuit map
Contains 337 buckets, 438 elements
Element count 0, 65
Element count 1, 135
Element count 2, 112
Element count 3, 21
Element count 4, 4
Unused hash: 0.19, average depth 1.91
Hash dump:string->text map
Contains 107897 buckets, 128013 elements
Element count 0, 32995
Element count 1, 39083
Element count 2, 23047
Element count 3, 9249
Element count 4, 2686
Element count 5, 698
Element count 6, 122
Element count 7, 15
Element count 8, 1
Element count 9, 0
Element count 10, 1
Unused hash: 0.31, average depth 2.19
CVC: Shorting non conducting resistors...
CVC: Calculating resistor voltages...
Usage RES: Time: 0  Memory: 86140  I/O: 56  Swap: 0
Power nets 216
CVC: Calculating min/max voltages...
Processing trivial nets found 5176 trivial nets
CVC: Ignoring invalid calculations...
CVC:   Removed 0 calculations
Copying master nets
CVC: Ignoring non-conducting devices...
CVC:   Ignored 0 devices
Usage MIN/MAX1: Time: 0  Memory: 86464  I/O: 56  Swap: 0
Power nets 4169
! Checking forward bias diode errors: 

! Checking nmos source/drain vs bias errors: 

! Checking nmos gate vs source errors: 

! Checking pmos source/drain vs bias errors: 

! Checking pmos gate vs source errors: 

Usage ERROR: Time: 1  Memory: 86464  I/O: 56  Swap: 0
CVC: Propagating Simulation voltages 1...
Usage SIM1: Time: 1  Memory: 87256  I/O: 56  Swap: 0
Power nets 4169
CVC: Propagating Simulation voltages 3...
Usage SIM2: Time: 1  Memory: 87520  I/O: 56  Swap: 0
Power nets 4169
Added 0 latch voltages
CVC: Calculating min/max voltages...
Processing trivial nets found 5176 trivial nets
CVC: Ignoring invalid calculations...
CVC:   Removed 0 calculations
Copying master nets
CVC: Ignoring non-conducting devices...
CVC:   Ignored 0 devices
Usage MIN/MAX2: Time: 1  Memory: 87784  I/O: 56  Swap: 0
Power nets 8122
! Checking overvoltage errors

! Checking nmos possible leak errors: 

! Checking pmos possible leak errors: 

! Checking mos floating input errors:

! Checking expected values:

CVC: Error Counts
CVC: Fuse Problems:         0
CVC: Min Voltage Conflicts: 0
CVC: Max Voltage Conflicts: 0
CVC: Leaks:                 0
CVC: LDD drain->source:     0
CVC: HI-Z Inputs:           0
CVC: Forward Bias Diodes:   0
CVC: NMOS Source vs Bulk:   0
CVC: NMOS Gate vs Source:   0
CVC: NMOS Possible Leaks:   0
CVC: PMOS Source vs Bulk:   0
CVC: PMOS Gate vs Source:   0
CVC: PMOS Possible Leaks:   0
CVC: Overvoltage-VBG:       0
CVC: Overvoltage-VBS:       0
CVC: Overvoltage-VDS:       0
CVC: Overvoltage-VGS:       0
CVC: Model errors:          0
CVC: Unexpected voltage :   0
CVC: Total:                 0
Usage Total: Time: 1  Memory: 88312  I/O: 96  Swap: 0
Virtual net update/access 113111/10759649
CVC: Log output to /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/reports/finishing/WB_InterConnect.rpt
CVC: End: Tue Mar 22 00:15:30 2022