)]}'
{
  "commit": "333db4364fd4e89840832e9d165fb161b6851f56",
  "tree": "2fa204fb2eeb981f48b77e6bceb34be8020b44ed",
  "parents": [
    "30864c733615b95fca915e6e1bd7ec7d7b9875ab"
  ],
  "author": {
    "name": "Ali Imran",
    "email": "ali1120001@outlook.com",
    "time": "Fri Mar 18 16:40:57 2022 +0500"
  },
  "committer": {
    "name": "Ali Imran",
    "email": "ali1120001@outlook.com",
    "time": "Fri Mar 18 16:40:57 2022 +0500"
  },
  "message": "SPI Verilog added\n",
  "tree_diff": [
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "410f830b0cd6460bc04c316064ac4f51e86d2afa",
      "new_mode": 33188,
      "new_path": "verilog/rtl/SPI.v"
    }
  ]
}