diff --git a/gds/user_proj_example.gds b/gds/user_proj_example.gds
index e274624..d7873fc 100644
--- a/gds/user_proj_example.gds
+++ b/gds/user_proj_example.gds
Binary files differ
diff --git a/mag/user_proj_example.mag b/mag/user_proj_example.mag
index 13fb410..b1c01aa 100644
--- a/mag/user_proj_example.mag
+++ b/mag/user_proj_example.mag
@@ -1,7 +1,7 @@
 magic
 tech sky130A
 magscale 1 2
-timestamp 1647721677
+timestamp 1647723123
 << viali >>
 rect 118157 117317 118191 117351
 rect 3801 117249 3835 117283
diff --git a/maglef/user_proj_example.mag b/maglef/user_proj_example.mag
index af9b212..75e9cc5 100644
--- a/maglef/user_proj_example.mag
+++ b/maglef/user_proj_example.mag
@@ -1,7 +1,7 @@
 magic
 tech sky130A
 magscale 1 2
-timestamp 1647721696
+timestamp 1647723143
 << obsli1 >>
 rect 1104 2159 238832 117521
 << obsm1 >>
diff --git a/sdc/user_proj_example.sdc b/sdc/user_proj_example.sdc
index 03a54f9..b19ee81 100644
--- a/sdc/user_proj_example.sdc
+++ b/sdc/user_proj_example.sdc
@@ -1,6 +1,6 @@
 ###############################################################################
 # Created by write_sdc
-# Sat Mar 19 20:26:34 2022
+# Sat Mar 19 20:50:32 2022
 ###############################################################################
 current_design user_proj_example
 ###############################################################################
diff --git a/sdf/user_proj_example.sdf b/sdf/user_proj_example.sdf
index da14169..d65bd82 100644
--- a/sdf/user_proj_example.sdf
+++ b/sdf/user_proj_example.sdf
@@ -1,7 +1,7 @@
 (DELAYFILE
  (SDFVERSION "3.0")
  (DESIGN "user_proj_example")
- (DATE "Sat Mar 19 20:27:50 2022")
+ (DATE "Sat Mar 19 20:51:56 2022")
  (VENDOR "Parallax")
  (PROGRAM "STA")
  (VERSION "2.3.1")
diff --git a/signoff/user_proj_example/final_summary_report.csv b/signoff/user_proj_example/final_summary_report.csv
index 2d338d8..5325fbe 100644
--- a/signoff/user_proj_example/final_summary_report.csv
+++ b/signoff/user_proj_example/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/home/asrock/caravel_tutorial/RNG/openlane/user_proj_example,user_proj_example,user_proj_example,flow completed,0h6m1s0ms,0h2m22s0ms,6035.714285714286,0.72,2112.5,1.82,2813.96,1521,0,0,0,0,0,0,0,3,0,0,-1,109377,15213,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,84789426.0,0.0,4.18,3.78,2.17,0.01,-1,1034,1934,31,931,0,0,0,1197,32,0,65,157,177,212,94,2,102,98,29,424,9844,0,10268,100.0,10.0,10,AREA 1,3,35,1,100,153.18,0.3,0.3,sky130_fd_sc_hd,4,3
+0,/home/asrock/caravel_tutorial/RNG/openlane/user_proj_example,user_proj_example,user_proj_example,flow completed,0h6m34s0ms,0h2m47s0ms,6035.714285714286,0.72,2112.5,1.82,2643.2,1521,0,0,0,0,0,0,0,3,0,0,-1,109377,15213,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,84789426.0,0.0,4.18,3.78,2.17,0.01,-1,1034,1934,31,931,0,0,0,1197,32,0,65,157,177,212,94,2,102,98,29,424,9844,0,10268,100.0,10.0,10,AREA 1,3,35,1,100,153.18,0.3,0.3,sky130_fd_sc_hd,4,3