# Caravel user project includes
-v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v	     
-v $(USER_PROJECT_VERILOG)/rtl/user_proj_example.v
-v $(USER_PROJECT_VERILOG)/rtl/4ft4_top.v
-v $(USER_PROJECT_VERILOG)/../4ft4/rtl/wb_system.v
-v $(USER_PROJECT_VERILOG)/../4ft4/rtl/cpu.v
-v $(USER_PROJECT_VERILOG)/../4ft4/rtl/cpu_control.v
-v $(USER_PROJECT_VERILOG)/../4ft4/rtl/alu.v
-v $(USER_PROJECT_VERILOG)/../4ft4/rtl/datapath.v
-v $(USER_PROJECT_VERILOG)/../4ft4/rtl/pc_stack.v
-v $(USER_PROJECT_VERILOG)/../4ft4/rtl/rom.v
-v $(USER_PROJECT_VERILOG)/../4ft4/rtl/ram.v
+define+NO_TRISTATE
# https://github.com/steveicarus/iverilog/issues/187
+define+ROM_FILE_BASE="../../rtl/4ft4_rom"
+define+ROM_CAPACITY=256
+incdir+$(USER_PROJECT_VERILOG)/../4ft4/rtl