)]}'
{
  "commit": "75d46a20aa31bf5788680d9bdf638b767ac06b8e",
  "tree": "c429d5dc4d85a95c9d15af132e6e9388c1ee1df7",
  "parents": [
    "4b9b4bd1ac2d395556283d0d9bdb5c213bb79409"
  ],
  "author": {
    "name": "Andrew Foote",
    "email": "afoote97@gmail.com",
    "time": "Mon Mar 21 09:32:12 2022 -0700"
  },
  "committer": {
    "name": "Andrew Foote",
    "email": "afoote97@gmail.com",
    "time": "Mon Mar 21 10:22:07 2022 -0700"
  },
  "message": "update 4ft4 submodule \u0026 4ft4_top\n\nconnect rom in \u0026 ram out to gpio.\n\nadd LA probes for halt and reset.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "29c58f8e6708e35a8777bd6f3543aac852e843d2",
      "old_mode": 57344,
      "old_path": "4ft4",
      "new_id": "9417585b62b77f0bda72091bcc064eb2b8b623a8",
      "new_mode": 57344,
      "new_path": "4ft4"
    },
    {
      "type": "modify",
      "old_id": "8336c2a868fc6d417a2f20a1333c8a641eba667b",
      "old_mode": 33188,
      "old_path": "verilog/dv/4ft4_fib/4ft4_fib.c",
      "new_id": "f24b2228e64e78d8f1d8e8d8c06967ea153f53cb",
      "new_mode": 33188,
      "new_path": "verilog/dv/4ft4_fib/4ft4_fib.c"
    },
    {
      "type": "modify",
      "old_id": "b823795a7a7d7eaeb9b2e8d449a158b4af6727c0",
      "old_mode": 33188,
      "old_path": "verilog/rtl/4ft4_top.v",
      "new_id": "17f4fec8addc5d100a975698b21c8ca89e40a15e",
      "new_mode": 33188,
      "new_path": "verilog/rtl/4ft4_top.v"
    }
  ]
}