)]}'
{
  "commit": "51973ac7072a1a23666ffe7a9f213b90b2a14cd8",
  "tree": "640535978237e537ab3afdb3b080f4ec5e5a76f3",
  "parents": [
    "75d46a20aa31bf5788680d9bdf638b767ac06b8e"
  ],
  "author": {
    "name": "Andrew Foote",
    "email": "afoote97@gmail.com",
    "time": "Mon Mar 21 10:22:47 2022 -0700"
  },
  "committer": {
    "name": "Andrew Foote",
    "email": "afoote97@gmail.com",
    "time": "Mon Mar 21 10:22:47 2022 -0700"
  },
  "message": "use LA halt \u0026 reset in 4ft4_fib\n\ncontrol 4ft4 execution using the LA probes to avoid\nthe processor cycling through the whole 12 bit space to\nget back to the fib program.\n\nalso check only the sum (but still output the values on the mgmt out\nlines) to speed up simuation.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "f24b2228e64e78d8f1d8e8d8c06967ea153f53cb",
      "old_mode": 33188,
      "old_path": "verilog/dv/4ft4_fib/4ft4_fib.c",
      "new_id": "7d6cd1e5a08594972429438cc16de774a7771804",
      "new_mode": 33188,
      "new_path": "verilog/dv/4ft4_fib/4ft4_fib.c"
    },
    {
      "type": "modify",
      "old_id": "42554d242862a927a0c8534b36fe150b3bbe8c18",
      "old_mode": 33188,
      "old_path": "verilog/dv/4ft4_fib/signals.tcl",
      "new_id": "cf4812ab3d56311e6047b3aebf1c4e7733640603",
      "new_mode": 33188,
      "new_path": "verilog/dv/4ft4_fib/signals.tcl"
    }
  ]
}