)]}'
{
  "commit": "4b9b4bd1ac2d395556283d0d9bdb5c213bb79409",
  "tree": "3989e597c1882d4b7ff31c216afa1f480e9d9ec4",
  "parents": [
    "02e3477409bf5b52d02ab318573ccbb1f59d8275"
  ],
  "author": {
    "name": "Andrew Foote",
    "email": "afoote97@gmail.com",
    "time": "Sun Mar 20 23:23:40 2022 -0700"
  },
  "committer": {
    "name": "Andrew Foote",
    "email": "afoote97@gmail.com",
    "time": "Sun Mar 20 23:24:59 2022 -0700"
  },
  "message": "update 4ft4_fib testing \u0026 enable gatelevel run\n\nupdate includes.gl.caravel_user_project to enable gatelevel run.\n\nrun RTL with WITH_ROM_RESET to match the synthesized design.\n\nmake tb run longer because with reset rom the cpu runs through the\nfull 12bit address space so it takes longer to get to the fib\ncomputation.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "18b12564ef118fac96f7b27547fb338406f76332",
      "old_mode": 33188,
      "old_path": "verilog/dv/4ft4_fib/4ft4_fib_tb.v",
      "new_id": "f76e2f046eedee98b6f2254d167b2d573b55540d",
      "new_mode": 33188,
      "new_path": "verilog/dv/4ft4_fib/4ft4_fib_tb.v"
    },
    {
      "type": "modify",
      "old_id": "f5047d52774d0d49a9ac85bccdd4058aa01916bf",
      "old_mode": 33188,
      "old_path": "verilog/includes/includes.gl.caravel_user_project",
      "new_id": "fc393ff9adb29ae613bbe51af69358517e51be14",
      "new_mode": 33188,
      "new_path": "verilog/includes/includes.gl.caravel_user_project"
    },
    {
      "type": "modify",
      "old_id": "68b766940d03ed163acb9e2835c8e5cec959bf7f",
      "old_mode": 33188,
      "old_path": "verilog/includes/includes.rtl.caravel_user_project",
      "new_id": "1e734ebec3d3254d279a9c00837a2500374b9b41",
      "new_mode": 33188,
      "new_path": "verilog/includes/includes.rtl.caravel_user_project"
    }
  ]
}