diff --git a/verilog/dv/4ft4_fib/4ft4_fib_tb.v b/verilog/dv/4ft4_fib/4ft4_fib_tb.v
index 18b1256..f76e2f0 100644
--- a/verilog/dv/4ft4_fib/4ft4_fib_tb.v
+++ b/verilog/dv/4ft4_fib/4ft4_fib_tb.v
@@ -50,16 +50,17 @@
         $dumpfile("4ft4_fib.vcd");
         $dumpvars(0, tb_4ft4_fib);
 
+        `ifndef GL
         for (i = 0; i < 3; i++) begin
             $dumpvars(0, uut.mprj.mprj.sys.cpu.pc_stack.program_counters[i]);
         end
-
         for (i = 0; i < 16; i++) begin
             $dumpvars(0, uut.mprj.mprj.sys.cpu.datapath.registers[i]);
         end
+        `endif
 
         // Repeat cycles of 1000 clock edges as needed to complete testbench
-        repeat (40) begin
+        repeat (60) begin
             repeat (1000) @(posedge clock);
             $display("+1000 cycles");
             $fflush();
diff --git a/verilog/includes/includes.gl.caravel_user_project b/verilog/includes/includes.gl.caravel_user_project
index f5047d5..fc393ff 100644
--- a/verilog/includes/includes.gl.caravel_user_project
+++ b/verilog/includes/includes.gl.caravel_user_project
@@ -1,3 +1,3 @@
-# Caravel user project includes	     
--v $(USER_PROJECT_VERILOG)/gl/user_project_wrapper.v	     
--v $(USER_PROJECT_VERILOG)/gl/user_proj_example.v     
+# Caravel user project includes
+-v $(USER_PROJECT_VERILOG)/gl/user_project_wrapper.v
+-v $(USER_PROJECT_VERILOG)/gl/top_4ft4.v
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project
index 68b7669..1e734eb 100644
--- a/verilog/includes/includes.rtl.caravel_user_project
+++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -1,6 +1,5 @@
 # Caravel user project includes
 -v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v	     
--v $(USER_PROJECT_VERILOG)/rtl/user_proj_example.v
 -v $(USER_PROJECT_VERILOG)/rtl/4ft4_top.v
 -v $(USER_PROJECT_VERILOG)/../4ft4/rtl/wb_system.v
 -v $(USER_PROJECT_VERILOG)/../4ft4/rtl/cpu.v
@@ -14,4 +13,5 @@
 # https://github.com/steveicarus/iverilog/issues/187
 +define+ROM_FILE_BASE="../../rtl/4ft4_rom"
 +define+ROM_CAPACITY=256
++define+WITH_ROM_RESET
 +incdir+$(USER_PROJECT_VERILOG)/../4ft4/rtl