)]}'
{
  "commit": "8945b088ba833f9ea78a26271067d9d514523f0d",
  "tree": "6db3aec137136a65354657e87b874db1dd1eae11",
  "parents": [
    "04927e0e3e75762033e6994ddec90b46f149fd54"
  ],
  "author": {
    "name": "Janavind",
    "email": "jaravind@aggies.ncat.edu",
    "time": "Mon Mar 14 13:49:36 2022 -0400"
  },
  "committer": {
    "name": "Janavind",
    "email": "jaravind@aggies.ncat.edu",
    "time": "Mon Mar 14 13:49:36 2022 -0400"
  },
  "message": "\tmodified:   def/user_proj_example.def\n\tmodified:   gds/user_proj_example.gds\n\tmodified:   lef/user_proj_example.lef\n\tmodified:   mag/user_proj_example.mag\n\tmodified:   maglef/user_proj_example.mag\n\tmodified:   openlane/user_project_wrapper/config.tcl\n\tmodified:   openlane/user_project_wrapper/macro.cfg\n\tmodified:   signoff/user_proj_example/final_summary_report.csv\n\tmodified:   spi/lvs/user_proj_example.spice\n\tmodified:   verilog/gl/user_proj_example.v\n\topenlane/user_project_wrapper/macros/\n\tsdc/\n\tsdf/\n\tspef/\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "d6dd535038f290a2fac77dc4ab52b54d557400bc",
      "old_mode": 33188,
      "old_path": "def/user_proj_example.def",
      "new_id": "3b780ca5a1d29effcd5c103909a5f141164eef2a",
      "new_mode": 33188,
      "new_path": "def/user_proj_example.def"
    },
    {
      "type": "modify",
      "old_id": "babcca509c7559cfdae5151328578b36a1fea4e1",
      "old_mode": 33188,
      "old_path": "gds/user_proj_example.gds",
      "new_id": "6f7ef03ec06a2f2a4c6c152f0f46f9c22acca97b",
      "new_mode": 33188,
      "new_path": "gds/user_proj_example.gds"
    },
    {
      "type": "modify",
      "old_id": "1677bbf34352c988bdc06aef3cd7fe39c30b5e2a",
      "old_mode": 33188,
      "old_path": "lef/user_proj_example.lef",
      "new_id": "9d518f07fec8c5635badb03c4bb9af81478ff323",
      "new_mode": 33188,
      "new_path": "lef/user_proj_example.lef"
    },
    {
      "type": "modify",
      "old_id": "9f2cd8976eba2282ac7fd0b0ee5c7c41f0f6e1f5",
      "old_mode": 33188,
      "old_path": "mag/user_proj_example.mag",
      "new_id": "052152f4b42647cef4c9b8325b93d318a7461b1a",
      "new_mode": 33188,
      "new_path": "mag/user_proj_example.mag"
    },
    {
      "type": "modify",
      "old_id": "1d42d4e4ccf47c5cb94f120119ea125520433dc0",
      "old_mode": 33188,
      "old_path": "maglef/user_proj_example.mag",
      "new_id": "043a3f09d13dd2b27bd19172292f54abd6fe72da",
      "new_mode": 33188,
      "new_path": "maglef/user_proj_example.mag"
    },
    {
      "type": "modify",
      "old_id": "27c5d2f0987bd7accaee6fc133ff94b307d1dab0",
      "old_mode": 33261,
      "old_path": "openlane/user_project_wrapper/config.tcl",
      "new_id": "115bc131f3659d83c78ed621e36a00d5f9797cf0",
      "new_mode": 33261,
      "new_path": "openlane/user_project_wrapper/config.tcl"
    },
    {
      "type": "modify",
      "old_id": "33bb1865ec9ca05dae076b4b4079ce99147ba378",
      "old_mode": 33188,
      "old_path": "openlane/user_project_wrapper/macro.cfg",
      "new_id": "e038cb0dc2c03ef3f156794cb41693366d0a1fee",
      "new_mode": 33188,
      "new_path": "openlane/user_project_wrapper/macro.cfg"
    },
    {
      "type": "modify",
      "old_id": "2c78a3e7ca6a51b20c0ba7abd5e7e52c3ee44c27",
      "old_mode": 33188,
      "old_path": "signoff/user_proj_example/final_summary_report.csv",
      "new_id": "2edb71e99ba0e5c4aaed04c17cce0b04d92e4ab7",
      "new_mode": 33188,
      "new_path": "signoff/user_proj_example/final_summary_report.csv"
    },
    {
      "type": "modify",
      "old_id": "ac0b6f2f2d3bfc09a56da073d49595552fe2874f",
      "old_mode": 33188,
      "old_path": "spi/lvs/user_proj_example.spice",
      "new_id": "e6e87dca409e80ab26f25b32f583b706155cdb44",
      "new_mode": 33188,
      "new_path": "spi/lvs/user_proj_example.spice"
    },
    {
      "type": "modify",
      "old_id": "f4ffaa8df546bb432ccad5869be79c20d56f3285",
      "old_mode": 33188,
      "old_path": "verilog/gl/user_proj_example.v",
      "new_id": "68dcf846c56eb56713960667916cbfec8fd1cfd4",
      "new_mode": 33188,
      "new_path": "verilog/gl/user_proj_example.v"
    }
  ]
}