2022-03-21 22:56:58 - [INFO] - {{Project Git Info}} Repository: https://github.com/steve-aurifexlabs/mpw5.git | Branch: mpw5-final | Commit: fd08fc0f557a678f3774b8bde5d4cc3813f9c39f
2022-03-21 22:56:58 - [INFO] - {{EXTRACTING FILES}} Extracting compressed files in: accelerated_risc-v_cpus
2022-03-21 22:56:58 - [INFO] - {{Project Type Info}} digital
2022-03-21 22:56:58 - [INFO] - {{Project GDS Info}} user_project_wrapper: c81dc84ad335de78831c4c298e72ff05df00c46c
2022-03-21 22:56:59 - [INFO] - {{Tools Info}} KLayout: v0.27.8 | Magic: v8.3.274
2022-03-21 22:56:59 - [INFO] - {{PDKs Info}} Open PDKs: 27ecf1c16911f7dd4428ffab96f62c1fb876ea70 | Skywater PDK: c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
2022-03-21 22:56:59 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in 'accelerated_risc-v_cpus/jobs/mpw_precheck/dc7b8112-3076-42fd-985c-c8348a7847ac/logs'
2022-03-21 22:56:59 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: [License, Makefile, Default, Documentation, Consistency, XOR, Magic DRC, Klayout FEOL, Klayout BEOL, Klayout Offgrid, Klayout Metal Minimum Clear Area Density, Klayout Pin Label Purposes Overlapping Drawing, Klayout ZeroArea]
2022-03-21 22:56:59 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 13: License
2022-03-21 22:56:59 - [INFO] - An approved LICENSE (Apache-2.0) was found in accelerated_risc-v_cpus.
2022-03-21 22:56:59 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root.
2022-03-21 22:57:00 - [INFO] - An approved LICENSE (Apache-2.0) was found in accelerated_risc-v_cpus.
2022-03-21 22:57:00 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules
2022-03-21 22:57:00 - [ERROR] - SPDX COMPLIANCE SYMLINK FILE NOT FOUND in accelerated_risc-v_cpus/openlane/Makefile
2022-03-21 22:57:01 - [WARNING] - {{SPDX COMPLIANCE CHECK FAILED}} Found 47 non-compliant file(s) with the SPDX Standard.
2022-03-21 22:57:01 - [INFO] - SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['accelerated_risc-v_cpus/Makefile', 'accelerated_risc-v_cpus/docs/Makefile', 'accelerated_risc-v_cpus/docs/environment.yml', 'accelerated_risc-v_cpus/docs/source/conf.py', 'accelerated_risc-v_cpus/docs/source/index.rst', 'accelerated_risc-v_cpus/docs/source/quickstart.rst', 'accelerated_risc-v_cpus/openlane/user_proj_example/config.json', 'accelerated_risc-v_cpus/openlane/user_proj_example/config.tcl', 'accelerated_risc-v_cpus/openlane/user_project_wrapper/config.json', 'accelerated_risc-v_cpus/openlane/user_project_wrapper/config.tcl', 'accelerated_risc-v_cpus/sdc/user_proj_example.sdc', 'accelerated_risc-v_cpus/sdc/user_project_wrapper.sdc', 'accelerated_risc-v_cpus/sdf/user_proj_example.sdf', 'accelerated_risc-v_cpus/sdf/user_project_wrapper.sdf', 'accelerated_risc-v_cpus/spef/user_proj_example.spef']
2022-03-21 22:57:01 - [INFO] - For the full SPDX compliance report check: accelerated_risc-v_cpus/jobs/mpw_precheck/dc7b8112-3076-42fd-985c-c8348a7847ac/logs/spdx_compliance_report.log
2022-03-21 22:57:01 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 13: Makefile
2022-03-21 22:57:01 - [INFO] - {{MAKEFILE CHECK PASSED}} Makefile valid.
2022-03-21 22:57:01 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 13: Default
2022-03-21 22:57:01 - [INFO] - {{README DEFAULT CHECK PASSED}} Project 'README.md' was modified and is not identical to the default 'README.md'
2022-03-21 22:57:01 - [INFO] - {{CONTENT DEFAULT CHECK PASSED}} Project 'gds' was modified and is not identical to the default 'gds'
2022-03-21 22:57:01 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 13: Documentation
2022-03-21 22:57:01 - [INFO] - {{DOCUMENTATION CHECK PASSED}} Project documentation is appropriate.
2022-03-21 22:57:01 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 13: Consistency
2022-03-21 22:57:06 - [INFO] - HIERARCHY CHECK PASSED: Module user_project_wrapper is instantiated in caravel. 
2022-03-21 22:57:06 - [INFO] - COMPLEXITY CHECK PASSED: Netlist caravel contains at least 8 instances (90 instances). 
2022-03-21 22:57:06 - [INFO] - MODELING CHECK PASSED: Netlist caravel is structural.
2022-03-21 22:57:06 - [INFO] - SUBMODULE HOOKS CHECK PASSED: All module ports for user_project_wrapper are correctly connected in the top level netlist caravel.
2022-03-21 22:57:06 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in caravel are connected to power
2022-03-21 22:57:06 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} caravel netlist passed all consistency checks.
2022-03-21 22:57:06 - [INFO] - PORTS CHECK PASSED: Netlist user_project_wrapper ports match the golden wrapper ports
2022-03-21 22:57:06 - [INFO] - COMPLEXITY CHECK PASSED: Netlist user_project_wrapper contains at least 1 instances (1 instances). 
2022-03-21 22:57:06 - [INFO] - MODELING CHECK PASSED: Netlist user_project_wrapper is structural.
2022-03-21 22:57:06 - [INFO] - LAYOUT CHECK PASSED: The GDS layout for user_project_wrapper matches the provided structural netlist.
2022-03-21 22:57:06 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in user_project_wrapper are connected to power
2022-03-21 22:57:06 - [INFO] - PORT TYPES CHECK PASSED: Netlist user_project_wrapper port types match the golden wrapper port types.
2022-03-21 22:57:06 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} user_project_wrapper netlist passed all consistency checks.
2022-03-21 22:57:06 - [INFO] - {{CONSISTENCY CHECK PASSED}} The user netlist and the top netlist are valid.
2022-03-21 22:57:07 - [INFO] - {{STEP UPDATE}} Executing Check 6 of 13: XOR
2022-03-21 22:57:19 - [INFO] - {{XOR CHECK UPDATE}} Total XOR differences: 0, for more details view accelerated_risc-v_cpus/jobs/mpw_precheck/dc7b8112-3076-42fd-985c-c8348a7847ac/outputs/user_project_wrapper.xor.gds
2022-03-21 22:57:19 - [INFO] - {{XOR CHECK PASSED}} The GDS file has no XOR violations.
2022-03-21 22:57:19 - [INFO] - {{STEP UPDATE}} Executing Check 7 of 13: Magic DRC
2022-03-21 23:01:53 - [INFO] - 0 DRC violations
2022-03-21 23:01:53 - [INFO] - {{MAGIC DRC CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2022-03-21 23:01:53 - [INFO] - {{STEP UPDATE}} Executing Check 8 of 13: Klayout FEOL
2022-03-21 23:02:31 - [INFO] - No DRC Violations found
2022-03-21 23:02:31 - [INFO] - {{Klayout FEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2022-03-21 23:02:31 - [INFO] - {{STEP UPDATE}} Executing Check 9 of 13: Klayout BEOL
2022-03-21 23:07:40 - [INFO] - No DRC Violations found
2022-03-21 23:07:40 - [INFO] - {{Klayout BEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2022-03-21 23:07:40 - [INFO] - {{STEP UPDATE}} Executing Check 10 of 13: Klayout Offgrid
2022-03-21 23:08:38 - [INFO] - No DRC Violations found
2022-03-21 23:08:38 - [INFO] - {{Klayout Offgrid CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2022-03-21 23:08:38 - [INFO] - {{STEP UPDATE}} Executing Check 11 of 13: Klayout Metal Minimum Clear Area Density
2022-03-21 23:08:54 - [INFO] - No DRC Violations found
2022-03-21 23:08:54 - [INFO] - {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2022-03-21 23:08:54 - [INFO] - {{STEP UPDATE}} Executing Check 12 of 13: Klayout Pin Label Purposes Overlapping Drawing
2022-03-21 23:09:04 - [INFO] - No DRC Violations found
2022-03-21 23:09:04 - [INFO] - {{Klayout Pin Label Purposes Overlapping Drawing CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2022-03-21 23:09:04 - [INFO] - {{STEP UPDATE}} Executing Check 13 of 13: Klayout ZeroArea
2022-03-21 23:09:08 - [INFO] - No DRC Violations found
2022-03-21 23:09:08 - [INFO] - {{Klayout ZeroArea CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2022-03-21 23:09:08 - [INFO] - {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in 'accelerated_risc-v_cpus/jobs/mpw_precheck/dc7b8112-3076-42fd-985c-c8348a7847ac/logs'
2022-03-21 23:09:08 - [INFO] - {{SUCCESS}} All Checks Passed !!!