)]}'
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        "time": "Tue Mar 08 19:41:04 2022 -0800"
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        "name": "Derek H-M",
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        "time": "Wed Mar 02 00:53:01 2022 -0800"
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      "message": "Change pins for clk and d_in\n\n* Use the \"analog\" pins of two GPIO cells instead for the ESD protection\n* Fix the absolute paths in several .mag files\n"
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      "message": "Edits and fixes to shift register layout\n\n* Add shift register schematic\n* LVS complete for shift register\n* Edits to project top level:\n  * power clamps connected\n  * alternate data sources connected to pwr and gnd\n"
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      "message": "Add schematic and spice TB for proj_sstl_test cell\n"
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        "time": "Sun Feb 27 12:23:10 2022 -0800"
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      "message": "Incorporate updated SSTL\n\n* Has better DQ port sizes\n"
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        "email": "derekcom16@gmail.com",
        "time": "Sat Feb 26 16:36:20 2022 -0800"
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      "message": "Add top level user_project_wrapper cell\n\n* Add SSTL test circuit and wire up most signals\n"
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    {
      "commit": "b5e09a961d21f83933e33083b9a0add9d6f7d429",
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      "author": {
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        "time": "Mon Feb 21 18:00:00 2022 -0800"
      },
      "committer": {
        "name": "Derek H-M",
        "email": "derekcom16@gmail.com",
        "time": "Mon Feb 14 23:20:17 2022 -0800"
      },
      "message": "Integrate updated SSTL into test circuit\n"
    },
    {
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        "email": "derekcom16@gmail.com",
        "time": "Sun Feb 20 15:15:56 2022 -0800"
      },
      "committer": {
        "name": "Derek H-M",
        "email": "derekcom16@gmail.com",
        "time": "Sun Feb 20 15:18:32 2022 -0800"
      },
      "message": "Update SSTL test circuit\n\n* Add lvs extraction script\n"
    },
    {
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        "time": "Mon Feb 14 19:59:00 2022 -0800"
      },
      "committer": {
        "name": "Derek H-M",
        "email": "derekcom16@gmail.com",
        "time": "Mon Feb 14 19:59:00 2022 -0800"
      },
      "message": "Add more to SSTL test cell\n\n* TODO: seperate digital and I/O logic to use two seprate\n  power supplies\n"
    },
    {
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        "time": "Sat Feb 05 19:45:27 2022 -0800"
      },
      "committer": {
        "name": "Derek H-M",
        "email": "derekcom16@gmail.com",
        "time": "Sat Feb 05 19:45:27 2022 -0800"
      },
      "message": "proj_sstl_test cell partially complete\n\n* Move example project cells to subfolder\n* Add shift reg\n"
    },
    {
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        "time": "Sat Feb 05 17:29:37 2022 -0800"
      },
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        "email": "derekcom16@gmail.com",
        "time": "Sat Feb 05 17:29:37 2022 -0800"
      },
      "message": "Update README, import SSTL layout\n"
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    {
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        "time": "Thu Feb 10 09:51:42 2022 -0800"
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        "time": "Thu Feb 10 09:51:42 2022 -0800"
      },
      "message": "Merge pull request #18 from efabless/EFIC-233\n\nEFIC-233"
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      "author": {
        "name": "Ahmed El Omla",
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        "time": "Tue Feb 08 16:15:27 2022 +0200"
      },
      "committer": {
        "name": "Ahmed El Omla",
        "email": "ahmed.el-omla@efabless.com",
        "time": "Tue Feb 08 16:15:27 2022 +0200"
      },
      "message": "EFIC-233 - Update CI\n"
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    {
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        "time": "Thu Feb 03 10:31:51 2022 -0800"
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      "message": "Merge pull request #17 from efabless/ol_fix\n\nUpdate Caravel to `mpw-5a`"
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      },
      "committer": {
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        "email": "noreply@github.com",
        "time": "Thu Feb 03 20:29:50 2022 +0200"
      },
      "message": "Update index.rst"
    },
    {
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        "time": "Thu Feb 03 18:28:36 2022 +0000"
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      "committer": {
        "name": "Donn",
        "email": "me@donn.website",
        "time": "Thu Feb 03 18:28:36 2022 +0000"
      },
      "message": "Update Caravel to `mpw-5a`\n\nAlso remove `make pdk-nonnative`.\n"
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    {
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        "time": "Fri Jan 28 12:40:31 2022 -0800"
      },
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        "email": "noreply@github.com",
        "time": "Fri Jan 28 12:40:31 2022 -0800"
      },
      "message": "Merge pull request #16 from efabless/EFIC-232\n\nEFIC-232 - Makefile Updates"
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    {
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        "time": "Fri Jan 28 19:56:44 2022 +0200"
      },
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        "time": "Fri Jan 28 19:56:44 2022 +0200"
      },
      "message": "Makefile Updates\n\nUpdates to \u0027Makefile\u0027 reflected appropriate mpw-5 shuttle tags and updated precheck instructions"
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      "author": {
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        "email": "tim@opencircuitdesign.com",
        "time": "Sun Dec 19 17:03:41 2021 -0500"
      },
      "committer": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Sun Dec 19 17:03:41 2021 -0500"
      },
      "message": "Modified the xschem schematics so that the wrapper level correctly\nrepresents the metal resistors that were added to the layout to\nmaintain all the pins on isolated nets.  The LVS with the xschem\nnetlist is now correct with the modified layout.  The verilog\nnetlist has not yet been updated.\n"
    },
    {
      "commit": "ea5ff7d937a3422c805b506215ae5242935638b2",
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        "time": "Sat Dec 18 10:44:16 2021 -0500"
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        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Sat Dec 18 10:44:16 2021 -0500"
      },
      "message": "Updated the layout to properly use the metal resistors in front of\npins that are connected to the same net.  Updated the GDS with this\nchange, and also to properly generate hierarchical layers, which\napparently had not been done previously.  Verilog and schematic\nhave not yet been updated with the metal resistor change, and so\nwill fail LVS until they are.\n"
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      },
      "committer": {
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        "time": "Fri Dec 17 13:40:01 2021 -0800"
      },
      "message": "Update Makefile"
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    {
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        "time": "Fri Dec 17 13:38:25 2021 -0800"
      },
      "message": "Merge pull request #13 from efabless/caravel_openframe\n\nremove submodule"
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      "committer": {
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        "time": "Fri Dec 17 13:36:23 2021 -0800"
      },
      "message": "Update user_project_ci.yml"
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    {
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      "committer": {
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        "time": "Fri Dec 17 13:35:46 2021 -0800"
      },
      "message": "Update caravan_build.yml"
    },
    {
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        "time": "Fri Dec 17 13:33:34 2021 -0800"
      },
      "message": "Update run-truck.sh"
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    {
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        "time": "Fri Dec 17 13:33:15 2021 -0800"
      },
      "message": "Update run-set-id.sh"
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    {
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        "time": "Fri Dec 17 13:32:55 2021 -0800"
      },
      "message": "Update user_project_ci.yml"
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    {
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      "committer": {
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        "time": "Fri Dec 17 13:32:23 2021 -0800"
      },
      "message": "Update caravan_build.yml"
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    {
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        "time": "Fri Dec 17 13:31:34 2021 -0800"
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      "message": "Delete auto_update_submodule.yml"
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    {
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      },
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        "email": "jeffdi@efabless.com",
        "time": "Thu Dec 16 12:07:52 2021 -0800"
      },
      "message": "remove submodule\n"
    },
    {
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        "time": "Wed Oct 27 11:57:38 2021 -0700"
      },
      "committer": {
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        "email": "noreply@github.com",
        "time": "Wed Oct 27 11:57:38 2021 -0700"
      },
      "message": "Merge pull request #12 from Manarabdelaty/update_gds\n\nUpdate gds view to match the mag view"
    },
    {
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      },
      "committer": {
        "name": "manarabdelaty",
        "email": "manarabdelatty@aucegypt.edu",
        "time": "Wed Oct 27 20:43:58 2021 +0200"
      },
      "message": "Update gds view to match the mag view\n"
    },
    {
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        "time": "Mon Oct 25 12:12:33 2021 -0700"
      },
      "committer": {
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        "time": "Mon Oct 25 12:12:33 2021 -0700"
      },
      "message": "Delete info.yaml"
    },
    {
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        "time": "Sun Oct 24 10:08:46 2021 -0700"
      },
      "committer": {
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        "email": "noreply@github.com",
        "time": "Sun Oct 24 10:08:46 2021 -0700"
      },
      "message": "Update index.rst\n\nAdd\\ checklist item for spice netlist"
    },
    {
      "commit": "f4d92bf2d5dbda8fe5d04d051879691524dcebd0",
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      "author": {
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        "email": "tim@opencircuitdesign.com",
        "time": "Tue Oct 12 15:49:11 2021 -0400"
      },
      "committer": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Tue Oct 12 15:49:11 2021 -0400"
      },
      "message": "Additional corrections to the analog wrapper testbench schematic to\nproperly quote net names with brackets, and to name a net that is\nreferenced in the plot command but hadn\u0027t been named in the\nschematic.\n"
    },
    {
      "commit": "00336fefcbe85ba1859b311b66fa1b68f7d2bf46",
      "tree": "46197294e2a37b6789841ba058e6b437825d56a8",
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      "author": {
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        "email": "tim@opencircuitdesign.com",
        "time": "Mon Oct 11 21:43:55 2021 -0400"
      },
      "committer": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Mon Oct 11 21:43:55 2021 -0400"
      },
      "message": "Modified the xschem files to reflect the handling of Tcl variables\nthat was implemented since this repository was first created.  This\nmakes use of xschemrc to define PDKPATH and to allow it to be\noverridden from the local OS environment.\n"
    },
    {
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