v {xschem version=3.0.0 file_version=1.2 }
G {}
K {type=subcircuit
format="@name @@DQ @@pd_ctrl[6:0] @@pu_ctrl[6:0] @@pd_cal_ctrl[3:0] @@pu_cal_ctrl[3:0] @VDD @GND @symname"
template="name=X1 VDD=VDD GND=GND"
extra="VDD GND"}
V {}
S {}
E {}
L 4 460 -120 500 -120 {}
L 4 20 -60 60 -60 {}
L 4 20 -90 60 -90 {}
L 4 20 -180 60 -180 {}
L 4 20 -150 60 -150 {}
B 5 497.5 -122.5 502.5 -117.5 {name=DQ
dir=inout}
B 5 17.5 -62.5 22.5 -57.5 {name=pd_ctrl[6:0]
dir=in}
B 5 17.5 -92.5 22.5 -87.5 {name=pd_cal_ctrl[3:0]
dir=in}
B 5 17.5 -182.5 22.5 -177.5 {name=pu_ctrl[6:0]
dir=in}
B 5 17.5 -152.5 22.5 -147.5 {name=pu_cal_ctrl[3:0]
dir=in}
P 4 5 60 -200 460 -200 460 -40 60 -40 60 -200 {}
T {DDR3 SSTL} 150 -140 0 0 0.8 0.8 {}
T {DQ} 430 -130 0 0 0.3 0.3 {}
T {pd_ctrl[6:0]} 70 -70 0 0 0.3 0.3 {}
T {pd_cal_ctrl[3:0]} 70 -100 0 0 0.3 0.3 {}
T {@name} 230 -230 0 0 0.3 0.3 {}
T {pu_ctrl[6:0]} 70 -190 0 0 0.3 0.3 {}
T {pu_cal_ctrl[3:0]} 70 -160 0 0 0.3 0.3 {}