diff --git a/README.md b/README.md
index a2a1286..2e0e11b 100644
--- a/README.md
+++ b/README.md
@@ -44,7 +44,7 @@
 `tx/rx_pu/pd_cal` signals control the calibration FETs within the legs.
 
 As can be seen in the diagram, there are 3 alternate data inputs. This allows external signals to be substituted for the input signal.
-In this design, `data_0` is tied to VDD, `data_2` is tied to VSS (ground) and `data_3` is connected to `la_data_out[0]`.
+In this design, `data_0` is tied to VDD, `data_2` is tied to VSS (ground) and `data_3` is connected to `la_data_in[0]`.
 The ability to set the signal output to a static high or low voltage will be helpful when manually performing the calibration procedure in the lab.
 
 ## Pinout
diff --git a/gds/user_analog_project_wrapper.gds b/gds/user_analog_project_wrapper.gds
index 00de0a7..ae30b80 100644
--- a/gds/user_analog_project_wrapper.gds
+++ b/gds/user_analog_project_wrapper.gds
Binary files differ
diff --git a/mag/analog_proj_wrapper_tb.spice b/mag/analog_proj_wrapper_tb.spice
index 8050637..29cf90d 100755
--- a/mag/analog_proj_wrapper_tb.spice
+++ b/mag/analog_proj_wrapper_tb.spice
@@ -116,7 +116,7 @@
 
 * signal in
 vsig io_analog[10] 0 0 PULSE 0 1.5 1n 10p 10p 5n 10n 0
-vsigalt la_data_out[0] 0 0
+vsigalt la_data_in[0] 0 0
 
 * Connect VDD and VSS
 vvddio  io_clamp_high[2] VDD 0
diff --git a/mag/user_analog_project_wrapper.mag b/mag/user_analog_project_wrapper.mag
index 37c58a7..d5cd7fd 100644
--- a/mag/user_analog_project_wrapper.mag
+++ b/mag/user_analog_project_wrapper.mag
@@ -1,7 +1,12 @@
 magic
 tech sky130A
 magscale 1 2
-timestamp 1646875120
+timestamp 1646892135
+<< checkpaint >>
+rect 5740 641398 8428 644558
+rect 14245 644248 50495 686919
+rect 14669 644232 17190 644248
+rect 52936 641398 55624 644558
 << metal1 >>
 rect 7241 643202 7251 643298
 rect 7469 643202 7479 643298
@@ -462,12 +467,12 @@
 rect 57514 641802 57739 642827
 rect 57514 641568 57739 641577
 rect 6999 641231 7206 641240
-rect 126679 3554 127384 4191
-rect 126679 3530 127435 3554
-rect 126679 2835 126731 3530
-rect 127426 2835 127435 3530
-rect 126922 698 127187 2835
-rect 127384 2820 127435 2835
+rect 125497 3554 126202 4191
+rect 125497 3530 126253 3554
+rect 125497 2835 125549 3530
+rect 126244 2835 126253 3530
+rect 125740 698 126005 2835
+rect 126202 2820 126253 2835
 rect 524 -800 636 480
 rect 1706 -800 1818 480
 rect 2888 -800 3000 480
@@ -574,7 +579,7 @@
 rect 122270 -800 122382 480
 rect 123452 -800 123564 480
 rect 124634 -800 124746 480
-rect 125816 -800 125928 480
+rect 125816 -800 125928 698
 rect 126998 -800 127110 698
 rect 128180 -800 128292 480
 rect 129362 -800 129474 480
@@ -1035,7 +1040,7 @@
 rect 52883 642658 53101 642754
 rect 57514 641577 57739 641802
 rect 6999 641240 7206 641447
-rect 126731 2835 127426 3530
+rect 125549 2835 126244 3530
 << metal3 >>
 rect 16194 702300 21194 704800
 rect 18694 688664 21194 702300
@@ -1389,13 +1394,13 @@
 rect 583520 5090 584800 5202
 rect -800 3908 480 4020
 rect 583520 3908 584800 4020
-rect 126727 3535 127430 3540
-rect 126726 3534 127431 3535
+rect 125545 3535 126248 3540
+rect 125544 3534 126249 3535
 rect -800 2726 480 2838
-rect 126726 2831 126727 3534
-rect 127430 2831 127431 3534
-rect 126726 2830 127431 2831
-rect 126727 2825 127430 2830
+rect 125544 2831 125545 3534
+rect 126248 2831 126249 3534
+rect 125544 2830 126249 2831
+rect 125545 2825 126248 2830
 rect 583520 2726 584800 2838
 rect -800 1544 480 1656
 rect 583520 1544 584800 1656
@@ -1427,11 +1432,11 @@
 rect 49834 643200 50265 643202
 rect 26365 642336 26687 642658
 rect 50444 642330 50869 642755
-rect 126727 3530 127430 3534
-rect 126727 2835 126731 3530
-rect 126731 2835 127426 3530
-rect 127426 2835 127430 3530
-rect 126727 2831 127430 2835
+rect 125545 3530 126248 3534
+rect 125545 2835 125549 3530
+rect 125549 2835 126244 3530
+rect 126244 2835 126248 3530
+rect 125545 2831 126248 2835
 << metal4 >>
 rect 165594 702300 170594 704800
 rect 175894 702300 180894 704800
@@ -1501,10 +1506,10 @@
 rect 50443 642329 50870 642330
 rect 26789 642076 27418 642084
 rect 26713 3535 27418 642076
-rect 26713 3534 127431 3535
-rect 26713 2831 126727 3534
-rect 127430 2831 127431 3534
-rect 26713 2830 127431 2831
+rect 26713 3534 126493 3535
+rect 26713 2831 125545 3534
+rect 126248 2831 126493 3534
+rect 26713 2830 126493 2831
 << metal5 >>
 rect 165594 702300 170594 704800
 rect 175894 702300 180894 704800
@@ -1537,7 +1542,7 @@
 timestamp 1646875120
 transform 1 0 15929 0 1 645492
 box -424 16 33306 40167
-use sky130_fd_sc_hd__tapvpwrvgnd_1  sky130_fd_sc_hd__tapvpwrvgnd_1_0 
+use sky130_fd_sc_hd__tapvpwrvgnd_1  sky130_fd_sc_hd__tapvpwrvgnd_1_0 ~/proj/caravan-project/pdk/sky130A/libs.ref/sky130_fd_sc_hd/mag
 timestamp 1646787781
 transform 1 0 54234 0 1 642706
 box -38 -48 130 592
diff --git a/verilog/rtl/example_por.v b/verilog/rtl/example_por/example_por.v
similarity index 100%
rename from verilog/rtl/example_por.v
rename to verilog/rtl/example_por/example_por.v
diff --git a/verilog/rtl/uprj_analog_netlists.v b/verilog/rtl/example_por/uprj_analog_netlists.v
similarity index 100%
rename from verilog/rtl/uprj_analog_netlists.v
rename to verilog/rtl/example_por/uprj_analog_netlists.v
diff --git a/verilog/rtl/user_analog_proj_example.v b/verilog/rtl/example_por/user_analog_proj_example.v
similarity index 100%
rename from verilog/rtl/user_analog_proj_example.v
rename to verilog/rtl/example_por/user_analog_proj_example.v
diff --git a/verilog/rtl/example_por/user_analog_project_wrapper.v b/verilog/rtl/example_por/user_analog_project_wrapper.v
new file mode 100644
index 0000000..7a73f76
--- /dev/null
+++ b/verilog/rtl/example_por/user_analog_project_wrapper.v
@@ -0,0 +1,182 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+/*
+ *-------------------------------------------------------------
+ *
+ * user_analog_project_wrapper
+ *
+ * This wrapper enumerates all of the pins available to the
+ * user for the user analog project.
+ *
+ *-------------------------------------------------------------
+ */
+
+module user_analog_project_wrapper (
+`ifdef USE_POWER_PINS
+    inout vdda1,	// User area 1 3.3V supply
+    inout vdda2,	// User area 2 3.3V supply
+    inout vssa1,	// User area 1 analog ground
+    inout vssa2,	// User area 2 analog ground
+    inout vccd1,	// User area 1 1.8V supply
+    inout vccd2,	// User area 2 1.8v supply
+    inout vssd1,	// User area 1 digital ground
+    inout vssd2,	// User area 2 digital ground
+`endif
+
+    // Wishbone Slave ports (WB MI A)
+    input wb_clk_i,
+    input wb_rst_i,
+    input wbs_stb_i,
+    input wbs_cyc_i,
+    input wbs_we_i,
+    input [3:0] wbs_sel_i,
+    input [31:0] wbs_dat_i,
+    input [31:0] wbs_adr_i,
+    output wbs_ack_o,
+    output [31:0] wbs_dat_o,
+
+    // Logic Analyzer Signals
+    input  [127:0] la_data_in,
+    output [127:0] la_data_out,
+    input  [127:0] la_oenb,
+
+    /* GPIOs.  There are 27 GPIOs, on either side of the analog.
+     * These have the following mapping to the GPIO padframe pins
+     * and memory-mapped registers, since the numbering remains the
+     * same as caravel but skips over the analog I/O:
+     *
+     * io_in/out/oeb/in_3v3 [26:14]  <--->  mprj_io[37:25]
+     * io_in/out/oeb/in_3v3 [13:0]   <--->  mprj_io[13:0]	
+     *
+     * When the GPIOs are configured by the Management SoC for
+     * user use, they have three basic bidirectional controls:
+     * in, out, and oeb (output enable, sense inverted).  For
+     * analog projects, a 3.3V copy of the signal input is
+     * available.  out and oeb must be 1.8V signals.
+     */
+
+    input  [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in,
+    input  [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3,
+    output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out,
+    output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb,
+
+    /* Analog (direct connection to GPIO pad---not for high voltage or
+     * high frequency use).  The management SoC must turn off both
+     * input and output buffers on these GPIOs to allow analog access.
+     * These signals may drive a voltage up to the value of VDDIO
+     * (3.3V typical, 5.5V maximum).
+     * 
+     * Note that analog I/O is not available on the 7 lowest-numbered
+     * GPIO pads, and so the analog_io indexing is offset from the
+     * GPIO indexing by 7, as follows:
+     *
+     * gpio_analog/noesd [17:7]  <--->  mprj_io[35:25]
+     * gpio_analog/noesd [6:0]   <--->  mprj_io[13:7]	
+     *
+     */
+    
+    inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_analog,
+    inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_noesd,
+
+    /* Analog signals, direct through to pad.  These have no ESD at all,
+     * so ESD protection is the responsibility of the designer.
+     *
+     * user_analog[10:0]  <--->  mprj_io[24:14]
+     *
+     */
+    inout [`ANALOG_PADS-1:0] io_analog,
+
+    /* Additional power supply ESD clamps, one per analog pad.  The
+     * high side should be connected to a 3.3-5.5V power supply.
+     * The low side should be connected to ground.
+     *
+     * clamp_high[2:0]   <--->  mprj_io[20:18]
+     * clamp_low[2:0]    <--->  mprj_io[20:18]
+     *
+     */
+    inout [2:0] io_clamp_high,
+    inout [2:0] io_clamp_low,
+
+    // Independent clock (on independent integer divider)
+    input   user_clock2,
+
+    // User maskable interrupt signals
+    output [2:0] user_irq
+);
+
+/*--------------------------------------*/
+/* User project is instantiated  here   */
+/*--------------------------------------*/
+
+user_analog_proj_example mprj (
+    `ifdef USE_POWER_PINS
+        .vdda1(vdda1),  // User area 1 3.3V power
+        .vdda2(vdda2),  // User area 2 3.3V power
+        .vssa1(vssa1),  // User area 1 analog ground
+        .vssa2(vssa2),  // User area 2 analog ground
+        .vccd1(vccd1),  // User area 1 1.8V power
+        .vccd2(vccd2),  // User area 2 1.8V power
+        .vssd1(vssd1),  // User area 1 digital ground
+        .vssd2(vssd2),  // User area 2 digital ground
+    `endif
+
+    .wb_clk_i(wb_clk_i),
+    .wb_rst_i(wb_rst_i),
+
+    // MGMT SoC Wishbone Slave
+
+    .wbs_cyc_i(wbs_cyc_i),
+    .wbs_stb_i(wbs_stb_i),
+    .wbs_we_i(wbs_we_i),
+    .wbs_sel_i(wbs_sel_i),
+    .wbs_adr_i(wbs_adr_i),
+    .wbs_dat_i(wbs_dat_i),
+    .wbs_ack_o(wbs_ack_o),
+    .wbs_dat_o(wbs_dat_o),
+
+    // Logic Analyzer
+
+    .la_data_in(la_data_in),
+    .la_data_out(la_data_out),
+    .la_oenb (la_oenb),
+
+    // IO Pads
+    .io_in (io_in),
+    .io_in_3v3 (io_in_3v3),
+    .io_out(io_out),
+    .io_oeb(io_oeb),
+
+    // GPIO-analog
+    .gpio_analog(gpio_analog),
+    .gpio_noesd(gpio_noesd),
+
+    // Dedicated analog
+    .io_analog(io_analog),
+    .io_clamp_high(io_clamp_high),
+    .io_clamp_low(io_clamp_low),
+
+    // Clock
+    .user_clock2(user_clock2),
+
+    // IRQ
+    .irq(user_irq)
+);
+
+endmodule	// user_analog_project_wrapper
+
+`default_nettype wire