)]}'
{
  "commit": "24aa8936da61a833e27747a8772e26255189b204",
  "tree": "6c25a6c30e07abf7f918460b9c1bb2d1cd7523f4",
  "parents": [
    "255346d4f639e1c61f19eb751bfc2292e20f8399"
  ],
  "author": {
    "name": "Derek H-M",
    "email": "derekcom16@gmail.com",
    "time": "Wed Mar 09 23:06:35 2022 -0800"
  },
  "committer": {
    "name": "Derek H-M",
    "email": "derekcom16@gmail.com",
    "time": "Wed Mar 09 23:06:35 2022 -0800"
  },
  "message": "Update top level spice netlist in netgen directory\n\n* Add some verilog models, but they are not necessary actually.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "c3851a38c39397863c74709a8dcd36576f8131dc",
      "old_mode": 33188,
      "old_path": "netgen/user_analog_project_wrapper.spice",
      "new_id": "278e5208832f1452f80975592dde0e9c8049d0bf",
      "new_mode": 33188,
      "new_path": "netgen/user_analog_project_wrapper.spice"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "f7c4d5440e7e524997270ac035abf835fd10632b",
      "new_mode": 33261,
      "new_path": "verilog/rtl/cfg_shift_register.v"
    },
    {
      "type": "modify",
      "old_id": "7a73f7652e076589d7908122a3e80d2f75644fbc",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_analog_project_wrapper.v",
      "new_id": "2611196354139f1182f285914381d1bf4b7b63a8",
      "new_mode": 33261,
      "new_path": "verilog/rtl/user_analog_project_wrapper.v"
    }
  ]
}