diff --git a/def/user_proj_dac.def.gz b/def/user_proj_dac.def.gz
index 836c578..858a643 100644
--- a/def/user_proj_dac.def.gz
+++ b/def/user_proj_dac.def.gz
Binary files differ
diff --git a/def/user_project_wrapper.def.gz b/def/user_project_wrapper.def.gz
index 2e9245d..ddaf113 100644
--- a/def/user_project_wrapper.def.gz
+++ b/def/user_project_wrapper.def.gz
Binary files differ
diff --git a/gds/user_proj_dac.gds.gz b/gds/user_proj_dac.gds.gz
index 9c48589..6e8fe03 100644
--- a/gds/user_proj_dac.gds.gz
+++ b/gds/user_proj_dac.gds.gz
Binary files differ
diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz
index 0b9c3a4..48ef687 100644
--- a/gds/user_project_wrapper.gds.gz
+++ b/gds/user_project_wrapper.gds.gz
Binary files differ
diff --git a/lef/user_proj_dac.lef.gz b/lef/user_proj_dac.lef.gz
index 9f86244..132c834 100644
--- a/lef/user_proj_dac.lef.gz
+++ b/lef/user_proj_dac.lef.gz
Binary files differ
diff --git a/lef/user_project_wrapper.lef.gz b/lef/user_project_wrapper.lef.gz
index f3cbb3c..236b8bc 100644
--- a/lef/user_project_wrapper.lef.gz
+++ b/lef/user_project_wrapper.lef.gz
Binary files differ
diff --git a/mag/user_proj_dac.mag.gz b/mag/user_proj_dac.mag.gz
index 8997ad8..02e2ee3 100644
--- a/mag/user_proj_dac.mag.gz
+++ b/mag/user_proj_dac.mag.gz
Binary files differ
diff --git a/mag/user_project_wrapper.mag.gz b/mag/user_project_wrapper.mag.gz
index 63f19a6..97c55e7 100644
--- a/mag/user_project_wrapper.mag.gz
+++ b/mag/user_project_wrapper.mag.gz
Binary files differ
diff --git a/maglef/user_proj_dac.mag.gz b/maglef/user_proj_dac.mag.gz
index d07cc30..98aebc9 100644
--- a/maglef/user_proj_dac.mag.gz
+++ b/maglef/user_proj_dac.mag.gz
Binary files differ
diff --git a/maglef/user_project_wrapper.mag.gz b/maglef/user_project_wrapper.mag.gz
index b67edb4..ae75e68 100644
--- a/maglef/user_project_wrapper.mag.gz
+++ b/maglef/user_project_wrapper.mag.gz
Binary files differ
diff --git a/openlane/user_proj_dac/config.tcl b/openlane/user_proj_dac/config.tcl
index fffdb1b..586bc3c 100755
--- a/openlane/user_proj_dac/config.tcl
+++ b/openlane/user_proj_dac/config.tcl
@@ -38,17 +38,18 @@
 
 # Setup placing and routing
 set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 2000 2000"
+set ::env(DIE_AREA) "0 0 1500 2000"
 set ::env(FP_CORE_UTIL) 25
 set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
 set ::env(ROUTING_CORES) 4
 
 # Need to blacklist decap_12, otherwise LI1 density too high in Caravel
-set ::env(DECAP_CELL) "\
-	sky130_fd_sc_hd__decap_3 \
-	sky130_fd_sc_hd__decap_4 \
-	sky130_fd_sc_hd__decap_6 \
-	sky130_fd_sc_hd__decap_8"
+#set ::env(DECAP_CELL) "\
+#	sky130_fd_sc_hd__decap_3 \
+#	sky130_fd_sc_hd__decap_4 \
+#	sky130_fd_sc_hd__decap_6 \
+#	sky130_fd_sc_hd__decap_8 \
+#	sky130_ef_sc_hd__decap_12"
 
 # Pin config
 set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index 6551e66..b1ce88b 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1,2 +1,2 @@
-dac0 500 500 N
+dac0 750 500 N
 drv0 1730 2950 N
diff --git a/signoff/user_proj_dac/final_summary_report.csv b/signoff/user_proj_dac/final_summary_report.csv
index a7befb1..8284284 100644
--- a/signoff/user_proj_dac/final_summary_report.csv
+++ b/signoff/user_proj_dac/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/home/harald/caravel_mpw5/iic-audiodac-v1/openlane/user_proj_dac,user_proj_dac,user_proj_dac,flow_completed,3h24m9s,-1,37834.0,4.0,9458.5,13.09,3576.09,37834,0,0,0,0,0,0,0,88,0,0,-1,3310240,529478,0.0,-28.69,-1,0.0,-1,0.0,-489.65,-1,0.0,-1,2136566927.0,0.0,20.96,18.1,2.79,0.47,-1,19627,31115,941,12252,0,0,0,29468,0,0,0,0,0,0,0,4,10884,11024,43,1454,56133,0,57587,19.607843137254903,51,50,AREA 0,5,25,1,153.6,153.18,0.3,0.0,sky130_fd_sc_hd,4,4
+0,/home/harald/caravel_mpw5/iic-audiodac-v1/openlane/user_proj_dac,user_proj_dac,user_proj_dac,flow_completed,1h53m56s,-1,50445.33333333334,3.0,12611.333333333336,17.49,2830.81,37834,0,0,0,0,0,0,0,82,0,0,-1,3411205,534133,0.0,-29.62,-1,0.0,-1,0.0,-506.64,-1,0.0,-1,2234555362.0,0.0,24.47,28.93,1.84,2.26,-1,19627,31115,941,12252,0,0,0,29468,0,0,0,0,0,0,0,4,10884,11024,43,1454,41917,0,43371,19.607843137254903,51,50,AREA 0,5,25,1,153.6,153.18,0.3,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index 85d5efd..d31b0d5 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/home/harald/caravel_mpw5/iic-audiodac-v1/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h42m55s,-1,0.38916562889165623,10.2784,0.19458281444582812,-1,547.68,2,0,0,0,0,0,0,0,0,0,-1,-1,770493,2326,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,40141.04,1.74,2.86,0.43,0.01,-1,27,645,27,645,0,0,0,2,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,19.607843137254903,51,50,AREA 0,5,50,1,180,180,0.55,0.0,sky130_fd_sc_hd,4,0
+0,/home/harald/caravel_mpw5/iic-audiodac-v1/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h36m17s,-1,0.38916562889165623,10.2784,0.19458281444582812,-1,490.9,2,0,0,0,0,0,0,0,0,0,-1,-1,818953,2167,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,40141.04,1.67,2.51,0.47,0.0,-1,27,645,27,645,0,0,0,2,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,19.607843137254903,51,50,AREA 0,5,50,1,180,180,0.55,0.0,sky130_fd_sc_hd,4,0
diff --git a/spi/lvs/user_proj_dac.spice.gz b/spi/lvs/user_proj_dac.spice.gz
index 37777ac..456e136 100644
--- a/spi/lvs/user_proj_dac.spice.gz
+++ b/spi/lvs/user_proj_dac.spice.gz
Binary files differ
diff --git a/spi/lvs/user_project_wrapper.spice.gz b/spi/lvs/user_project_wrapper.spice.gz
index 1217ff8..21c7bc0 100644
--- a/spi/lvs/user_project_wrapper.spice.gz
+++ b/spi/lvs/user_project_wrapper.spice.gz
Binary files differ
diff --git a/verilog/gl/user_proj_dac.v.gz b/verilog/gl/user_proj_dac.v.gz
index 07a0df4..33f5ec4 100644
--- a/verilog/gl/user_proj_dac.v.gz
+++ b/verilog/gl/user_proj_dac.v.gz
Binary files differ
diff --git a/verilog/gl/user_project_wrapper.v.gz b/verilog/gl/user_project_wrapper.v.gz
index 619eaad..8351563 100644
--- a/verilog/gl/user_project_wrapper.v.gz
+++ b/verilog/gl/user_project_wrapper.v.gz
Binary files differ